17e2d23ecSStefan Wahren // SPDX-License-Identifier: GPL-2.0 2660fc733SEric Anholt /* 3660fc733SEric Anholt * bcm2835 sdhost driver. 4660fc733SEric Anholt * 5660fc733SEric Anholt * The 2835 has two SD controllers: The Arasan sdhci controller 6660fc733SEric Anholt * (supported by the iproc driver) and a custom sdhost controller 7660fc733SEric Anholt * (supported by this driver). 8660fc733SEric Anholt * 9660fc733SEric Anholt * The sdhci controller supports both sdcard and sdio. The sdhost 10660fc733SEric Anholt * controller supports the sdcard only, but has better performance. 11660fc733SEric Anholt * Also note that the rpi3 has sdio wifi, so driving the sdcard with 12660fc733SEric Anholt * the sdhost controller allows to use the sdhci controller for wifi 13660fc733SEric Anholt * support. 14660fc733SEric Anholt * 15660fc733SEric Anholt * The configuration is done by devicetree via pin muxing. Both 16660fc733SEric Anholt * SD controller are available on the same pins (2 pin groups = pin 22 17660fc733SEric Anholt * to 27 + pin 48 to 53). So it's possible to use both SD controllers 18660fc733SEric Anholt * at the same time with different pin groups. 19660fc733SEric Anholt * 20660fc733SEric Anholt * Author: Phil Elwell <phil@raspberrypi.org> 21660fc733SEric Anholt * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 22660fc733SEric Anholt * 23660fc733SEric Anholt * Based on 24660fc733SEric Anholt * mmc-bcm2835.c by Gellert Weisz 25660fc733SEric Anholt * which is, in turn, based on 26660fc733SEric Anholt * sdhci-bcm2708.c by Broadcom 27660fc733SEric Anholt * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 28660fc733SEric Anholt * sdhci.c and sdhci-pci.c by Pierre Ossman 29660fc733SEric Anholt */ 30660fc733SEric Anholt #include <linux/clk.h> 31660fc733SEric Anholt #include <linux/delay.h> 32660fc733SEric Anholt #include <linux/device.h> 33660fc733SEric Anholt #include <linux/dmaengine.h> 34660fc733SEric Anholt #include <linux/dma-mapping.h> 35660fc733SEric Anholt #include <linux/err.h> 36660fc733SEric Anholt #include <linux/highmem.h> 37660fc733SEric Anholt #include <linux/interrupt.h> 38660fc733SEric Anholt #include <linux/io.h> 39660fc733SEric Anholt #include <linux/iopoll.h> 40660fc733SEric Anholt #include <linux/module.h> 41660fc733SEric Anholt #include <linux/of_address.h> 42660fc733SEric Anholt #include <linux/of_irq.h> 43660fc733SEric Anholt #include <linux/platform_device.h> 44660fc733SEric Anholt #include <linux/scatterlist.h> 45660fc733SEric Anholt #include <linux/time.h> 46660fc733SEric Anholt #include <linux/workqueue.h> 47660fc733SEric Anholt 48660fc733SEric Anholt #include <linux/mmc/host.h> 49660fc733SEric Anholt #include <linux/mmc/mmc.h> 50660fc733SEric Anholt #include <linux/mmc/sd.h> 51660fc733SEric Anholt 52660fc733SEric Anholt #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 53660fc733SEric Anholt #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 54660fc733SEric Anholt #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 55660fc733SEric Anholt #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 56660fc733SEric Anholt #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 57660fc733SEric Anholt #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 58660fc733SEric Anholt #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 59660fc733SEric Anholt #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 60660fc733SEric Anholt #define SDHSTS 0x20 /* SD host status - 11 R/W */ 61660fc733SEric Anholt #define SDVDD 0x30 /* SD card power control - 1 R/W */ 62660fc733SEric Anholt #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 63660fc733SEric Anholt #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 64660fc733SEric Anholt #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 65660fc733SEric Anholt #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 66660fc733SEric Anholt #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 67660fc733SEric Anholt 68660fc733SEric Anholt #define SDCMD_NEW_FLAG 0x8000 69660fc733SEric Anholt #define SDCMD_FAIL_FLAG 0x4000 70660fc733SEric Anholt #define SDCMD_BUSYWAIT 0x800 71660fc733SEric Anholt #define SDCMD_NO_RESPONSE 0x400 72660fc733SEric Anholt #define SDCMD_LONG_RESPONSE 0x200 73660fc733SEric Anholt #define SDCMD_WRITE_CMD 0x80 74660fc733SEric Anholt #define SDCMD_READ_CMD 0x40 75660fc733SEric Anholt #define SDCMD_CMD_MASK 0x3f 76660fc733SEric Anholt 77660fc733SEric Anholt #define SDCDIV_MAX_CDIV 0x7ff 78660fc733SEric Anholt 79660fc733SEric Anholt #define SDHSTS_BUSY_IRPT 0x400 80660fc733SEric Anholt #define SDHSTS_BLOCK_IRPT 0x200 81660fc733SEric Anholt #define SDHSTS_SDIO_IRPT 0x100 82660fc733SEric Anholt #define SDHSTS_REW_TIME_OUT 0x80 83660fc733SEric Anholt #define SDHSTS_CMD_TIME_OUT 0x40 84660fc733SEric Anholt #define SDHSTS_CRC16_ERROR 0x20 85660fc733SEric Anholt #define SDHSTS_CRC7_ERROR 0x10 86660fc733SEric Anholt #define SDHSTS_FIFO_ERROR 0x08 87660fc733SEric Anholt /* Reserved */ 88660fc733SEric Anholt /* Reserved */ 89660fc733SEric Anholt #define SDHSTS_DATA_FLAG 0x01 90660fc733SEric Anholt 91660fc733SEric Anholt #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 92660fc733SEric Anholt SDHSTS_CRC16_ERROR | \ 93660fc733SEric Anholt SDHSTS_REW_TIME_OUT | \ 94660fc733SEric Anholt SDHSTS_FIFO_ERROR) 95660fc733SEric Anholt 96660fc733SEric Anholt #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 97660fc733SEric Anholt SDHSTS_TRANSFER_ERROR_MASK) 98660fc733SEric Anholt 99660fc733SEric Anholt #define SDHCFG_BUSY_IRPT_EN BIT(10) 100660fc733SEric Anholt #define SDHCFG_BLOCK_IRPT_EN BIT(8) 101660fc733SEric Anholt #define SDHCFG_SDIO_IRPT_EN BIT(5) 102660fc733SEric Anholt #define SDHCFG_DATA_IRPT_EN BIT(4) 103660fc733SEric Anholt #define SDHCFG_SLOW_CARD BIT(3) 104660fc733SEric Anholt #define SDHCFG_WIDE_EXT_BUS BIT(2) 105660fc733SEric Anholt #define SDHCFG_WIDE_INT_BUS BIT(1) 106660fc733SEric Anholt #define SDHCFG_REL_CMD_LINE BIT(0) 107660fc733SEric Anholt 108660fc733SEric Anholt #define SDVDD_POWER_OFF 0 109660fc733SEric Anholt #define SDVDD_POWER_ON 1 110660fc733SEric Anholt 111660fc733SEric Anholt #define SDEDM_FORCE_DATA_MODE BIT(19) 112660fc733SEric Anholt #define SDEDM_CLOCK_PULSE BIT(20) 113660fc733SEric Anholt #define SDEDM_BYPASS BIT(21) 114660fc733SEric Anholt 115660fc733SEric Anholt #define SDEDM_WRITE_THRESHOLD_SHIFT 9 116660fc733SEric Anholt #define SDEDM_READ_THRESHOLD_SHIFT 14 117660fc733SEric Anholt #define SDEDM_THRESHOLD_MASK 0x1f 118660fc733SEric Anholt 119660fc733SEric Anholt #define SDEDM_FSM_MASK 0xf 120660fc733SEric Anholt #define SDEDM_FSM_IDENTMODE 0x0 121660fc733SEric Anholt #define SDEDM_FSM_DATAMODE 0x1 122660fc733SEric Anholt #define SDEDM_FSM_READDATA 0x2 123660fc733SEric Anholt #define SDEDM_FSM_WRITEDATA 0x3 124660fc733SEric Anholt #define SDEDM_FSM_READWAIT 0x4 125660fc733SEric Anholt #define SDEDM_FSM_READCRC 0x5 126660fc733SEric Anholt #define SDEDM_FSM_WRITECRC 0x6 127660fc733SEric Anholt #define SDEDM_FSM_WRITEWAIT1 0x7 128660fc733SEric Anholt #define SDEDM_FSM_POWERDOWN 0x8 129660fc733SEric Anholt #define SDEDM_FSM_POWERUP 0x9 130660fc733SEric Anholt #define SDEDM_FSM_WRITESTART1 0xa 131660fc733SEric Anholt #define SDEDM_FSM_WRITESTART2 0xb 132660fc733SEric Anholt #define SDEDM_FSM_GENPULSES 0xc 133660fc733SEric Anholt #define SDEDM_FSM_WRITEWAIT2 0xd 134660fc733SEric Anholt #define SDEDM_FSM_STARTPOWDOWN 0xf 135660fc733SEric Anholt 136660fc733SEric Anholt #define SDDATA_FIFO_WORDS 16 137660fc733SEric Anholt 138660fc733SEric Anholt #define FIFO_READ_THRESHOLD 4 139660fc733SEric Anholt #define FIFO_WRITE_THRESHOLD 4 140660fc733SEric Anholt #define SDDATA_FIFO_PIO_BURST 8 141660fc733SEric Anholt 142660fc733SEric Anholt #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */ 143660fc733SEric Anholt 144660fc733SEric Anholt struct bcm2835_host { 145660fc733SEric Anholt spinlock_t lock; 146660fc733SEric Anholt struct mutex mutex; 147660fc733SEric Anholt 148660fc733SEric Anholt void __iomem *ioaddr; 149660fc733SEric Anholt u32 phys_addr; 150660fc733SEric Anholt 151660fc733SEric Anholt struct mmc_host *mmc; 152660fc733SEric Anholt struct platform_device *pdev; 153660fc733SEric Anholt 154660fc733SEric Anholt int clock; /* Current clock speed */ 155660fc733SEric Anholt unsigned int max_clk; /* Max possible freq */ 156660fc733SEric Anholt struct work_struct dma_work; 157660fc733SEric Anholt struct delayed_work timeout_work; /* Timer for timeouts */ 158660fc733SEric Anholt struct sg_mapping_iter sg_miter; /* SG state for PIO */ 159660fc733SEric Anholt unsigned int blocks; /* remaining PIO blocks */ 160660fc733SEric Anholt int irq; /* Device IRQ */ 161660fc733SEric Anholt 162660fc733SEric Anholt u32 ns_per_fifo_word; 163660fc733SEric Anholt 164660fc733SEric Anholt /* cached registers */ 165660fc733SEric Anholt u32 hcfg; 166660fc733SEric Anholt u32 cdiv; 167660fc733SEric Anholt 168660fc733SEric Anholt struct mmc_request *mrq; /* Current request */ 169660fc733SEric Anholt struct mmc_command *cmd; /* Current command */ 170660fc733SEric Anholt struct mmc_data *data; /* Current data request */ 171660fc733SEric Anholt bool data_complete:1;/* Data finished before cmd */ 172660fc733SEric Anholt bool use_busy:1; /* Wait for busy interrupt */ 173660fc733SEric Anholt bool use_sbc:1; /* Send CMD23 */ 174660fc733SEric Anholt 175660fc733SEric Anholt /* for threaded irq handler */ 176660fc733SEric Anholt bool irq_block; 177660fc733SEric Anholt bool irq_busy; 178660fc733SEric Anholt bool irq_data; 179660fc733SEric Anholt 180660fc733SEric Anholt /* DMA part */ 181660fc733SEric Anholt struct dma_chan *dma_chan_rxtx; 182660fc733SEric Anholt struct dma_chan *dma_chan; 183660fc733SEric Anholt struct dma_slave_config dma_cfg_rx; 184660fc733SEric Anholt struct dma_slave_config dma_cfg_tx; 185660fc733SEric Anholt struct dma_async_tx_descriptor *dma_desc; 186660fc733SEric Anholt u32 dma_dir; 187660fc733SEric Anholt u32 drain_words; 188660fc733SEric Anholt struct page *drain_page; 189660fc733SEric Anholt u32 drain_offset; 190660fc733SEric Anholt bool use_dma; 191660fc733SEric Anholt }; 192660fc733SEric Anholt 193660fc733SEric Anholt static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd, 194660fc733SEric Anholt const char *label) 195660fc733SEric Anholt { 196660fc733SEric Anholt struct device *dev = &host->pdev->dev; 197660fc733SEric Anholt 198660fc733SEric Anholt if (!cmd) 199660fc733SEric Anholt return; 200660fc733SEric Anholt 201660fc733SEric Anholt dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", 202660fc733SEric Anholt (cmd == host->cmd) ? '>' : ' ', 203660fc733SEric Anholt label, cmd->opcode, cmd->arg, cmd->flags, 204660fc733SEric Anholt cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], 205660fc733SEric Anholt cmd->error); 206660fc733SEric Anholt } 207660fc733SEric Anholt 208660fc733SEric Anholt static void bcm2835_dumpregs(struct bcm2835_host *host) 209660fc733SEric Anholt { 210660fc733SEric Anholt struct mmc_request *mrq = host->mrq; 211660fc733SEric Anholt struct device *dev = &host->pdev->dev; 212660fc733SEric Anholt 213660fc733SEric Anholt if (mrq) { 214660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->sbc, "sbc"); 215660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->cmd, "cmd"); 216660fc733SEric Anholt if (mrq->data) { 217660fc733SEric Anholt dev_dbg(dev, "data blocks %x blksz %x - err %d\n", 218660fc733SEric Anholt mrq->data->blocks, 219660fc733SEric Anholt mrq->data->blksz, 220660fc733SEric Anholt mrq->data->error); 221660fc733SEric Anholt } 222660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->stop, "stop"); 223660fc733SEric Anholt } 224660fc733SEric Anholt 225660fc733SEric Anholt dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 226660fc733SEric Anholt dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 227660fc733SEric Anholt dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 228660fc733SEric Anholt dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 229660fc733SEric Anholt dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 230660fc733SEric Anholt dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 231660fc733SEric Anholt dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 232660fc733SEric Anholt dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 233660fc733SEric Anholt dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 234660fc733SEric Anholt dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 235660fc733SEric Anholt dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 236660fc733SEric Anholt dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 237660fc733SEric Anholt dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 238660fc733SEric Anholt dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 239660fc733SEric Anholt dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 240660fc733SEric Anholt dev_dbg(dev, "===========================================\n"); 241660fc733SEric Anholt } 242660fc733SEric Anholt 243660fc733SEric Anholt static void bcm2835_reset_internal(struct bcm2835_host *host) 244660fc733SEric Anholt { 245660fc733SEric Anholt u32 temp; 246660fc733SEric Anholt 247660fc733SEric Anholt writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 248660fc733SEric Anholt writel(0, host->ioaddr + SDCMD); 249660fc733SEric Anholt writel(0, host->ioaddr + SDARG); 250660fc733SEric Anholt writel(0xf00000, host->ioaddr + SDTOUT); 251660fc733SEric Anholt writel(0, host->ioaddr + SDCDIV); 252660fc733SEric Anholt writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */ 253660fc733SEric Anholt writel(0, host->ioaddr + SDHCFG); 254660fc733SEric Anholt writel(0, host->ioaddr + SDHBCT); 255660fc733SEric Anholt writel(0, host->ioaddr + SDHBLC); 256660fc733SEric Anholt 257660fc733SEric Anholt /* Limit fifo usage due to silicon bug */ 258660fc733SEric Anholt temp = readl(host->ioaddr + SDEDM); 259660fc733SEric Anholt temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 260660fc733SEric Anholt (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 261660fc733SEric Anholt temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 262660fc733SEric Anholt (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 263660fc733SEric Anholt writel(temp, host->ioaddr + SDEDM); 264660fc733SEric Anholt msleep(20); 265660fc733SEric Anholt writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 266660fc733SEric Anholt msleep(20); 267660fc733SEric Anholt host->clock = 0; 268660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 269660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 270660fc733SEric Anholt } 271660fc733SEric Anholt 272660fc733SEric Anholt static void bcm2835_reset(struct mmc_host *mmc) 273660fc733SEric Anholt { 274660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 275660fc733SEric Anholt 276660fc733SEric Anholt if (host->dma_chan) 277660fc733SEric Anholt dmaengine_terminate_sync(host->dma_chan); 278f6000a4eSMichal Suchanek host->dma_chan = NULL; 279660fc733SEric Anholt bcm2835_reset_internal(host); 280660fc733SEric Anholt } 281660fc733SEric Anholt 282660fc733SEric Anholt static void bcm2835_finish_command(struct bcm2835_host *host); 283660fc733SEric Anholt 284660fc733SEric Anholt static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 285660fc733SEric Anholt { 286660fc733SEric Anholt int timediff; 287660fc733SEric Anholt u32 alternate_idle; 288660fc733SEric Anholt 289660fc733SEric Anholt alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ? 290660fc733SEric Anholt SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 291660fc733SEric Anholt 292660fc733SEric Anholt timediff = 0; 293660fc733SEric Anholt 294660fc733SEric Anholt while (1) { 295660fc733SEric Anholt u32 edm, fsm; 296660fc733SEric Anholt 297660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 298660fc733SEric Anholt fsm = edm & SDEDM_FSM_MASK; 299660fc733SEric Anholt 300660fc733SEric Anholt if ((fsm == SDEDM_FSM_IDENTMODE) || 301660fc733SEric Anholt (fsm == SDEDM_FSM_DATAMODE)) 302660fc733SEric Anholt break; 303660fc733SEric Anholt if (fsm == alternate_idle) { 304660fc733SEric Anholt writel(edm | SDEDM_FORCE_DATA_MODE, 305660fc733SEric Anholt host->ioaddr + SDEDM); 306660fc733SEric Anholt break; 307660fc733SEric Anholt } 308660fc733SEric Anholt 309660fc733SEric Anholt timediff++; 310660fc733SEric Anholt if (timediff == 100000) { 311660fc733SEric Anholt dev_err(&host->pdev->dev, 312660fc733SEric Anholt "wait_transfer_complete - still waiting after %d retries\n", 313660fc733SEric Anholt timediff); 314660fc733SEric Anholt bcm2835_dumpregs(host); 315660fc733SEric Anholt host->mrq->data->error = -ETIMEDOUT; 316660fc733SEric Anholt return; 317660fc733SEric Anholt } 318660fc733SEric Anholt cpu_relax(); 319660fc733SEric Anholt } 320660fc733SEric Anholt } 321660fc733SEric Anholt 322660fc733SEric Anholt static void bcm2835_dma_complete(void *param) 323660fc733SEric Anholt { 324660fc733SEric Anholt struct bcm2835_host *host = param; 325660fc733SEric Anholt 326660fc733SEric Anholt schedule_work(&host->dma_work); 327660fc733SEric Anholt } 328660fc733SEric Anholt 329660fc733SEric Anholt static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 330660fc733SEric Anholt { 331660fc733SEric Anholt unsigned long flags; 332660fc733SEric Anholt size_t blksize; 333660fc733SEric Anholt unsigned long wait_max; 334660fc733SEric Anholt 335660fc733SEric Anholt blksize = host->data->blksz; 336660fc733SEric Anholt 337660fc733SEric Anholt wait_max = jiffies + msecs_to_jiffies(500); 338660fc733SEric Anholt 339660fc733SEric Anholt local_irq_save(flags); 340660fc733SEric Anholt 341660fc733SEric Anholt while (blksize) { 342660fc733SEric Anholt int copy_words; 343660fc733SEric Anholt u32 hsts = 0; 344660fc733SEric Anholt size_t len; 345660fc733SEric Anholt u32 *buf; 346660fc733SEric Anholt 347660fc733SEric Anholt if (!sg_miter_next(&host->sg_miter)) { 348660fc733SEric Anholt host->data->error = -EINVAL; 349660fc733SEric Anholt break; 350660fc733SEric Anholt } 351660fc733SEric Anholt 352660fc733SEric Anholt len = min(host->sg_miter.length, blksize); 353660fc733SEric Anholt if (len % 4) { 354660fc733SEric Anholt host->data->error = -EINVAL; 355660fc733SEric Anholt break; 356660fc733SEric Anholt } 357660fc733SEric Anholt 358660fc733SEric Anholt blksize -= len; 359660fc733SEric Anholt host->sg_miter.consumed = len; 360660fc733SEric Anholt 361660fc733SEric Anholt buf = (u32 *)host->sg_miter.addr; 362660fc733SEric Anholt 363660fc733SEric Anholt copy_words = len / 4; 364660fc733SEric Anholt 365660fc733SEric Anholt while (copy_words) { 366660fc733SEric Anholt int burst_words, words; 367660fc733SEric Anholt u32 edm; 368660fc733SEric Anholt 369660fc733SEric Anholt burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 370660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 371660fc733SEric Anholt if (is_read) 372660fc733SEric Anholt words = ((edm >> 4) & 0x1f); 373660fc733SEric Anholt else 374660fc733SEric Anholt words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f); 375660fc733SEric Anholt 376660fc733SEric Anholt if (words < burst_words) { 377660fc733SEric Anholt int fsm_state = (edm & SDEDM_FSM_MASK); 378660fc733SEric Anholt struct device *dev = &host->pdev->dev; 379660fc733SEric Anholt 380660fc733SEric Anholt if ((is_read && 381660fc733SEric Anholt (fsm_state != SDEDM_FSM_READDATA && 382660fc733SEric Anholt fsm_state != SDEDM_FSM_READWAIT && 383660fc733SEric Anholt fsm_state != SDEDM_FSM_READCRC)) || 384660fc733SEric Anholt (!is_read && 385660fc733SEric Anholt (fsm_state != SDEDM_FSM_WRITEDATA && 386660fc733SEric Anholt fsm_state != SDEDM_FSM_WRITESTART1 && 387660fc733SEric Anholt fsm_state != SDEDM_FSM_WRITESTART2))) { 388660fc733SEric Anholt hsts = readl(host->ioaddr + SDHSTS); 389660fc733SEric Anholt dev_err(dev, "fsm %x, hsts %08x\n", 390660fc733SEric Anholt fsm_state, hsts); 391660fc733SEric Anholt if (hsts & SDHSTS_ERROR_MASK) 392660fc733SEric Anholt break; 393660fc733SEric Anholt } 394660fc733SEric Anholt 395660fc733SEric Anholt if (time_after(jiffies, wait_max)) { 396660fc733SEric Anholt dev_err(dev, "PIO %s timeout - EDM %08x\n", 397660fc733SEric Anholt is_read ? "read" : "write", 398660fc733SEric Anholt edm); 399660fc733SEric Anholt hsts = SDHSTS_REW_TIME_OUT; 400660fc733SEric Anholt break; 401660fc733SEric Anholt } 402660fc733SEric Anholt ndelay((burst_words - words) * 403660fc733SEric Anholt host->ns_per_fifo_word); 404660fc733SEric Anholt continue; 405660fc733SEric Anholt } else if (words > copy_words) { 406660fc733SEric Anholt words = copy_words; 407660fc733SEric Anholt } 408660fc733SEric Anholt 409660fc733SEric Anholt copy_words -= words; 410660fc733SEric Anholt 411660fc733SEric Anholt while (words) { 412660fc733SEric Anholt if (is_read) 413660fc733SEric Anholt *(buf++) = readl(host->ioaddr + SDDATA); 414660fc733SEric Anholt else 415660fc733SEric Anholt writel(*(buf++), host->ioaddr + SDDATA); 416660fc733SEric Anholt words--; 417660fc733SEric Anholt } 418660fc733SEric Anholt } 419660fc733SEric Anholt 420660fc733SEric Anholt if (hsts & SDHSTS_ERROR_MASK) 421660fc733SEric Anholt break; 422660fc733SEric Anholt } 423660fc733SEric Anholt 424660fc733SEric Anholt sg_miter_stop(&host->sg_miter); 425660fc733SEric Anholt 426660fc733SEric Anholt local_irq_restore(flags); 427660fc733SEric Anholt } 428660fc733SEric Anholt 429660fc733SEric Anholt static void bcm2835_transfer_pio(struct bcm2835_host *host) 430660fc733SEric Anholt { 431660fc733SEric Anholt struct device *dev = &host->pdev->dev; 432660fc733SEric Anholt u32 sdhsts; 433660fc733SEric Anholt bool is_read; 434660fc733SEric Anholt 435660fc733SEric Anholt is_read = (host->data->flags & MMC_DATA_READ) != 0; 436660fc733SEric Anholt bcm2835_transfer_block_pio(host, is_read); 437660fc733SEric Anholt 438660fc733SEric Anholt sdhsts = readl(host->ioaddr + SDHSTS); 439660fc733SEric Anholt if (sdhsts & (SDHSTS_CRC16_ERROR | 440660fc733SEric Anholt SDHSTS_CRC7_ERROR | 441660fc733SEric Anholt SDHSTS_FIFO_ERROR)) { 442660fc733SEric Anholt dev_err(dev, "%s transfer error - HSTS %08x\n", 443660fc733SEric Anholt is_read ? "read" : "write", sdhsts); 444660fc733SEric Anholt host->data->error = -EILSEQ; 445660fc733SEric Anholt } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 446660fc733SEric Anholt SDHSTS_REW_TIME_OUT))) { 447660fc733SEric Anholt dev_err(dev, "%s timeout error - HSTS %08x\n", 448660fc733SEric Anholt is_read ? "read" : "write", sdhsts); 449660fc733SEric Anholt host->data->error = -ETIMEDOUT; 450660fc733SEric Anholt } 451660fc733SEric Anholt } 452660fc733SEric Anholt 453660fc733SEric Anholt static 454660fc733SEric Anholt void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data) 455660fc733SEric Anholt { 4566dc6f261SStefan Wahren int sg_len, dir_data, dir_slave; 457660fc733SEric Anholt struct dma_async_tx_descriptor *desc = NULL; 458660fc733SEric Anholt struct dma_chan *dma_chan; 459660fc733SEric Anholt 460660fc733SEric Anholt dma_chan = host->dma_chan_rxtx; 461660fc733SEric Anholt if (data->flags & MMC_DATA_READ) { 462660fc733SEric Anholt dir_data = DMA_FROM_DEVICE; 463660fc733SEric Anholt dir_slave = DMA_DEV_TO_MEM; 464660fc733SEric Anholt } else { 465660fc733SEric Anholt dir_data = DMA_TO_DEVICE; 466660fc733SEric Anholt dir_slave = DMA_MEM_TO_DEV; 467660fc733SEric Anholt } 468660fc733SEric Anholt 469660fc733SEric Anholt /* The block doesn't manage the FIFO DREQs properly for 470660fc733SEric Anholt * multi-block transfers, so don't attempt to DMA the final 471660fc733SEric Anholt * few words. Unfortunately this requires the final sg entry 472660fc733SEric Anholt * to be trimmed. N.B. This code demands that the overspill 473660fc733SEric Anholt * is contained in a single sg entry. 474660fc733SEric Anholt */ 475660fc733SEric Anholt 476660fc733SEric Anholt host->drain_words = 0; 477660fc733SEric Anholt if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) { 478660fc733SEric Anholt struct scatterlist *sg; 479660fc733SEric Anholt u32 len; 480660fc733SEric Anholt int i; 481660fc733SEric Anholt 482660fc733SEric Anholt len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4, 483660fc733SEric Anholt (u32)data->blocks * data->blksz); 484660fc733SEric Anholt 485660fc733SEric Anholt for_each_sg(data->sg, sg, data->sg_len, i) { 486660fc733SEric Anholt if (sg_is_last(sg)) { 487660fc733SEric Anholt WARN_ON(sg->length < len); 488660fc733SEric Anholt sg->length -= len; 489660fc733SEric Anholt host->drain_page = sg_page(sg); 490660fc733SEric Anholt host->drain_offset = sg->offset + sg->length; 491660fc733SEric Anholt } 492660fc733SEric Anholt } 493660fc733SEric Anholt host->drain_words = len / 4; 494660fc733SEric Anholt } 495660fc733SEric Anholt 496660fc733SEric Anholt /* The parameters have already been validated, so this will not fail */ 497660fc733SEric Anholt (void)dmaengine_slave_config(dma_chan, 498660fc733SEric Anholt (dir_data == DMA_FROM_DEVICE) ? 499660fc733SEric Anholt &host->dma_cfg_rx : 500660fc733SEric Anholt &host->dma_cfg_tx); 501660fc733SEric Anholt 5026dc6f261SStefan Wahren sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len, 503660fc733SEric Anholt dir_data); 5046dc6f261SStefan Wahren if (!sg_len) 5056dc6f261SStefan Wahren return; 506660fc733SEric Anholt 5076dc6f261SStefan Wahren desc = dmaengine_prep_slave_sg(dma_chan, data->sg, sg_len, dir_slave, 5086dc6f261SStefan Wahren DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 509660fc733SEric Anholt 5102f5da678SStefan Wahren if (!desc) { 5112f5da678SStefan Wahren dma_unmap_sg(dma_chan->device->dev, data->sg, sg_len, dir_data); 5122f5da678SStefan Wahren return; 5132f5da678SStefan Wahren } 5142f5da678SStefan Wahren 515660fc733SEric Anholt desc->callback = bcm2835_dma_complete; 516660fc733SEric Anholt desc->callback_param = host; 517660fc733SEric Anholt host->dma_desc = desc; 518660fc733SEric Anholt host->dma_chan = dma_chan; 519660fc733SEric Anholt host->dma_dir = dir_data; 520660fc733SEric Anholt } 521660fc733SEric Anholt 522660fc733SEric Anholt static void bcm2835_start_dma(struct bcm2835_host *host) 523660fc733SEric Anholt { 524660fc733SEric Anholt dmaengine_submit(host->dma_desc); 525660fc733SEric Anholt dma_async_issue_pending(host->dma_chan); 526660fc733SEric Anholt } 527660fc733SEric Anholt 528660fc733SEric Anholt static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 529660fc733SEric Anholt { 530660fc733SEric Anholt u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 531660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 532660fc733SEric Anholt 533660fc733SEric Anholt if (host->dma_desc) { 534660fc733SEric Anholt host->hcfg = (host->hcfg & ~all_irqs) | 535660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 536660fc733SEric Anholt } else { 537660fc733SEric Anholt host->hcfg = (host->hcfg & ~all_irqs) | 538660fc733SEric Anholt SDHCFG_DATA_IRPT_EN | 539660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 540660fc733SEric Anholt } 541660fc733SEric Anholt 542660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 543660fc733SEric Anholt } 544660fc733SEric Anholt 545660fc733SEric Anholt static 546660fc733SEric Anholt void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) 547660fc733SEric Anholt { 548660fc733SEric Anholt struct mmc_data *data = cmd->data; 549660fc733SEric Anholt 550660fc733SEric Anholt WARN_ON(host->data); 551660fc733SEric Anholt 552660fc733SEric Anholt host->data = data; 553660fc733SEric Anholt if (!data) 554660fc733SEric Anholt return; 555660fc733SEric Anholt 556660fc733SEric Anholt host->data_complete = false; 557660fc733SEric Anholt host->data->bytes_xfered = 0; 558660fc733SEric Anholt 559660fc733SEric Anholt if (!host->dma_desc) { 560660fc733SEric Anholt /* Use PIO */ 561660fc733SEric Anholt int flags = SG_MITER_ATOMIC; 562660fc733SEric Anholt 563660fc733SEric Anholt if (data->flags & MMC_DATA_READ) 564660fc733SEric Anholt flags |= SG_MITER_TO_SG; 565660fc733SEric Anholt else 566660fc733SEric Anholt flags |= SG_MITER_FROM_SG; 567660fc733SEric Anholt sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 568660fc733SEric Anholt host->blocks = data->blocks; 569660fc733SEric Anholt } 570660fc733SEric Anholt 571660fc733SEric Anholt bcm2835_set_transfer_irqs(host); 572660fc733SEric Anholt 573660fc733SEric Anholt writel(data->blksz, host->ioaddr + SDHBCT); 574660fc733SEric Anholt writel(data->blocks, host->ioaddr + SDHBLC); 575660fc733SEric Anholt } 576660fc733SEric Anholt 577660fc733SEric Anholt static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms) 578660fc733SEric Anholt { 579660fc733SEric Anholt struct device *dev = &host->pdev->dev; 580660fc733SEric Anholt u32 value; 581660fc733SEric Anholt int ret; 582660fc733SEric Anholt 583660fc733SEric Anholt ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 584660fc733SEric Anholt !(value & SDCMD_NEW_FLAG), 1, 10); 585660fc733SEric Anholt if (ret == -ETIMEDOUT) 586660fc733SEric Anholt /* if it takes a while make poll interval bigger */ 587660fc733SEric Anholt ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 588660fc733SEric Anholt !(value & SDCMD_NEW_FLAG), 589660fc733SEric Anholt 10, max_ms * 1000); 590660fc733SEric Anholt if (ret == -ETIMEDOUT) 591660fc733SEric Anholt dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms); 592660fc733SEric Anholt 593660fc733SEric Anholt return value; 594660fc733SEric Anholt } 595660fc733SEric Anholt 596660fc733SEric Anholt static void bcm2835_finish_request(struct bcm2835_host *host) 597660fc733SEric Anholt { 598660fc733SEric Anholt struct dma_chan *terminate_chan = NULL; 599660fc733SEric Anholt struct mmc_request *mrq; 600660fc733SEric Anholt 60137fefadeSStefan Wahren cancel_delayed_work_sync(&host->timeout_work); 602660fc733SEric Anholt 603660fc733SEric Anholt mrq = host->mrq; 604660fc733SEric Anholt 605660fc733SEric Anholt host->mrq = NULL; 606660fc733SEric Anholt host->cmd = NULL; 607660fc733SEric Anholt host->data = NULL; 608660fc733SEric Anholt 609660fc733SEric Anholt host->dma_desc = NULL; 610660fc733SEric Anholt terminate_chan = host->dma_chan; 611660fc733SEric Anholt host->dma_chan = NULL; 612660fc733SEric Anholt 613660fc733SEric Anholt if (terminate_chan) { 614660fc733SEric Anholt int err = dmaengine_terminate_all(terminate_chan); 615660fc733SEric Anholt 616660fc733SEric Anholt if (err) 617660fc733SEric Anholt dev_err(&host->pdev->dev, 618660fc733SEric Anholt "failed to terminate DMA (%d)\n", err); 619660fc733SEric Anholt } 620660fc733SEric Anholt 621660fc733SEric Anholt mmc_request_done(host->mmc, mrq); 622660fc733SEric Anholt } 623660fc733SEric Anholt 624660fc733SEric Anholt static 625660fc733SEric Anholt bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd) 626660fc733SEric Anholt { 627660fc733SEric Anholt struct device *dev = &host->pdev->dev; 628660fc733SEric Anholt u32 sdcmd, sdhsts; 629660fc733SEric Anholt unsigned long timeout; 630660fc733SEric Anholt 631660fc733SEric Anholt WARN_ON(host->cmd); 632660fc733SEric Anholt 633660fc733SEric Anholt sdcmd = bcm2835_read_wait_sdcmd(host, 100); 634660fc733SEric Anholt if (sdcmd & SDCMD_NEW_FLAG) { 635660fc733SEric Anholt dev_err(dev, "previous command never completed.\n"); 636660fc733SEric Anholt bcm2835_dumpregs(host); 637660fc733SEric Anholt cmd->error = -EILSEQ; 638660fc733SEric Anholt bcm2835_finish_request(host); 639660fc733SEric Anholt return false; 640660fc733SEric Anholt } 641660fc733SEric Anholt 642660fc733SEric Anholt if (!cmd->data && cmd->busy_timeout > 9000) 643660fc733SEric Anholt timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 644660fc733SEric Anholt else 645660fc733SEric Anholt timeout = 10 * HZ; 646660fc733SEric Anholt schedule_delayed_work(&host->timeout_work, timeout); 647660fc733SEric Anholt 648660fc733SEric Anholt host->cmd = cmd; 649660fc733SEric Anholt 650660fc733SEric Anholt /* Clear any error flags */ 651660fc733SEric Anholt sdhsts = readl(host->ioaddr + SDHSTS); 652660fc733SEric Anholt if (sdhsts & SDHSTS_ERROR_MASK) 653660fc733SEric Anholt writel(sdhsts, host->ioaddr + SDHSTS); 654660fc733SEric Anholt 655660fc733SEric Anholt if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 656660fc733SEric Anholt dev_err(dev, "unsupported response type!\n"); 657660fc733SEric Anholt cmd->error = -EINVAL; 658660fc733SEric Anholt bcm2835_finish_request(host); 659660fc733SEric Anholt return false; 660660fc733SEric Anholt } 661660fc733SEric Anholt 662660fc733SEric Anholt bcm2835_prepare_data(host, cmd); 663660fc733SEric Anholt 664660fc733SEric Anholt writel(cmd->arg, host->ioaddr + SDARG); 665660fc733SEric Anholt 666660fc733SEric Anholt sdcmd = cmd->opcode & SDCMD_CMD_MASK; 667660fc733SEric Anholt 668660fc733SEric Anholt host->use_busy = false; 669660fc733SEric Anholt if (!(cmd->flags & MMC_RSP_PRESENT)) { 670660fc733SEric Anholt sdcmd |= SDCMD_NO_RESPONSE; 671660fc733SEric Anholt } else { 672660fc733SEric Anholt if (cmd->flags & MMC_RSP_136) 673660fc733SEric Anholt sdcmd |= SDCMD_LONG_RESPONSE; 674660fc733SEric Anholt if (cmd->flags & MMC_RSP_BUSY) { 675660fc733SEric Anholt sdcmd |= SDCMD_BUSYWAIT; 676660fc733SEric Anholt host->use_busy = true; 677660fc733SEric Anholt } 678660fc733SEric Anholt } 679660fc733SEric Anholt 680660fc733SEric Anholt if (cmd->data) { 681660fc733SEric Anholt if (cmd->data->flags & MMC_DATA_WRITE) 682660fc733SEric Anholt sdcmd |= SDCMD_WRITE_CMD; 683660fc733SEric Anholt if (cmd->data->flags & MMC_DATA_READ) 684660fc733SEric Anholt sdcmd |= SDCMD_READ_CMD; 685660fc733SEric Anholt } 686660fc733SEric Anholt 687660fc733SEric Anholt writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 688660fc733SEric Anholt 689660fc733SEric Anholt return true; 690660fc733SEric Anholt } 691660fc733SEric Anholt 692660fc733SEric Anholt static void bcm2835_transfer_complete(struct bcm2835_host *host) 693660fc733SEric Anholt { 694660fc733SEric Anholt struct mmc_data *data; 695660fc733SEric Anholt 696660fc733SEric Anholt WARN_ON(!host->data_complete); 697660fc733SEric Anholt 698660fc733SEric Anholt data = host->data; 699660fc733SEric Anholt host->data = NULL; 700660fc733SEric Anholt 701660fc733SEric Anholt /* Need to send CMD12 if - 702660fc733SEric Anholt * a) open-ended multiblock transfer (no CMD23) 703660fc733SEric Anholt * b) error in multiblock transfer 704660fc733SEric Anholt */ 705660fc733SEric Anholt if (host->mrq->stop && (data->error || !host->use_sbc)) { 706660fc733SEric Anholt if (bcm2835_send_command(host, host->mrq->stop)) { 707660fc733SEric Anholt /* No busy, so poll for completion */ 708660fc733SEric Anholt if (!host->use_busy) 709660fc733SEric Anholt bcm2835_finish_command(host); 710660fc733SEric Anholt } 711660fc733SEric Anholt } else { 712660fc733SEric Anholt bcm2835_wait_transfer_complete(host); 713660fc733SEric Anholt bcm2835_finish_request(host); 714660fc733SEric Anholt } 715660fc733SEric Anholt } 716660fc733SEric Anholt 717660fc733SEric Anholt static void bcm2835_finish_data(struct bcm2835_host *host) 718660fc733SEric Anholt { 719660fc733SEric Anholt struct device *dev = &host->pdev->dev; 720660fc733SEric Anholt struct mmc_data *data; 721660fc733SEric Anholt 722660fc733SEric Anholt data = host->data; 723660fc733SEric Anholt 724660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 725660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 726660fc733SEric Anholt 727660fc733SEric Anholt data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks); 728660fc733SEric Anholt 729660fc733SEric Anholt host->data_complete = true; 730660fc733SEric Anholt 731660fc733SEric Anholt if (host->cmd) { 732660fc733SEric Anholt /* Data managed to finish before the 733660fc733SEric Anholt * command completed. Make sure we do 734660fc733SEric Anholt * things in the proper order. 735660fc733SEric Anholt */ 736660fc733SEric Anholt dev_dbg(dev, "Finished early - HSTS %08x\n", 737660fc733SEric Anholt readl(host->ioaddr + SDHSTS)); 738660fc733SEric Anholt } else { 739660fc733SEric Anholt bcm2835_transfer_complete(host); 740660fc733SEric Anholt } 741660fc733SEric Anholt } 742660fc733SEric Anholt 743660fc733SEric Anholt static void bcm2835_finish_command(struct bcm2835_host *host) 744660fc733SEric Anholt { 745660fc733SEric Anholt struct device *dev = &host->pdev->dev; 746660fc733SEric Anholt struct mmc_command *cmd = host->cmd; 747660fc733SEric Anholt u32 sdcmd; 748660fc733SEric Anholt 749660fc733SEric Anholt sdcmd = bcm2835_read_wait_sdcmd(host, 100); 750660fc733SEric Anholt 751660fc733SEric Anholt /* Check for errors */ 752660fc733SEric Anholt if (sdcmd & SDCMD_NEW_FLAG) { 753660fc733SEric Anholt dev_err(dev, "command never completed.\n"); 754660fc733SEric Anholt bcm2835_dumpregs(host); 755660fc733SEric Anholt host->cmd->error = -EIO; 756660fc733SEric Anholt bcm2835_finish_request(host); 757660fc733SEric Anholt return; 758660fc733SEric Anholt } else if (sdcmd & SDCMD_FAIL_FLAG) { 759660fc733SEric Anholt u32 sdhsts = readl(host->ioaddr + SDHSTS); 760660fc733SEric Anholt 761660fc733SEric Anholt /* Clear the errors */ 762660fc733SEric Anholt writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 763660fc733SEric Anholt 764660fc733SEric Anholt if (!(sdhsts & SDHSTS_CRC7_ERROR) || 765660fc733SEric Anholt (host->cmd->opcode != MMC_SEND_OP_COND)) { 76607d40576SPhil Elwell u32 edm, fsm; 76707d40576SPhil Elwell 768660fc733SEric Anholt if (sdhsts & SDHSTS_CMD_TIME_OUT) { 769660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 770660fc733SEric Anholt } else { 771660fc733SEric Anholt dev_err(dev, "unexpected command %d error\n", 772660fc733SEric Anholt host->cmd->opcode); 773660fc733SEric Anholt bcm2835_dumpregs(host); 774660fc733SEric Anholt host->cmd->error = -EILSEQ; 775660fc733SEric Anholt } 77607d40576SPhil Elwell edm = readl(host->ioaddr + SDEDM); 77707d40576SPhil Elwell fsm = edm & SDEDM_FSM_MASK; 77807d40576SPhil Elwell if (fsm == SDEDM_FSM_READWAIT || 77907d40576SPhil Elwell fsm == SDEDM_FSM_WRITESTART1) 78007d40576SPhil Elwell /* Kick the FSM out of its wait */ 78107d40576SPhil Elwell writel(edm | SDEDM_FORCE_DATA_MODE, 78207d40576SPhil Elwell host->ioaddr + SDEDM); 783660fc733SEric Anholt bcm2835_finish_request(host); 784660fc733SEric Anholt return; 785660fc733SEric Anholt } 786660fc733SEric Anholt } 787660fc733SEric Anholt 788660fc733SEric Anholt if (cmd->flags & MMC_RSP_PRESENT) { 789660fc733SEric Anholt if (cmd->flags & MMC_RSP_136) { 790660fc733SEric Anholt int i; 791660fc733SEric Anholt 792660fc733SEric Anholt for (i = 0; i < 4; i++) { 793660fc733SEric Anholt cmd->resp[3 - i] = 794660fc733SEric Anholt readl(host->ioaddr + SDRSP0 + i * 4); 795660fc733SEric Anholt } 796660fc733SEric Anholt } else { 797660fc733SEric Anholt cmd->resp[0] = readl(host->ioaddr + SDRSP0); 798660fc733SEric Anholt } 799660fc733SEric Anholt } 800660fc733SEric Anholt 801660fc733SEric Anholt if (cmd == host->mrq->sbc) { 802660fc733SEric Anholt /* Finished CMD23, now send actual command. */ 803660fc733SEric Anholt host->cmd = NULL; 804660fc733SEric Anholt if (bcm2835_send_command(host, host->mrq->cmd)) { 805660fc733SEric Anholt if (host->data && host->dma_desc) 806660fc733SEric Anholt /* DMA transfer starts now, PIO starts 807660fc733SEric Anholt * after irq 808660fc733SEric Anholt */ 809660fc733SEric Anholt bcm2835_start_dma(host); 810660fc733SEric Anholt 811660fc733SEric Anholt if (!host->use_busy) 812660fc733SEric Anholt bcm2835_finish_command(host); 813660fc733SEric Anholt } 814660fc733SEric Anholt } else if (cmd == host->mrq->stop) { 815660fc733SEric Anholt /* Finished CMD12 */ 816660fc733SEric Anholt bcm2835_finish_request(host); 817660fc733SEric Anholt } else { 818660fc733SEric Anholt /* Processed actual command. */ 819660fc733SEric Anholt host->cmd = NULL; 820660fc733SEric Anholt if (!host->data) 821660fc733SEric Anholt bcm2835_finish_request(host); 822660fc733SEric Anholt else if (host->data_complete) 823660fc733SEric Anholt bcm2835_transfer_complete(host); 824660fc733SEric Anholt } 825660fc733SEric Anholt } 826660fc733SEric Anholt 827660fc733SEric Anholt static void bcm2835_timeout(struct work_struct *work) 828660fc733SEric Anholt { 829660fc733SEric Anholt struct delayed_work *d = to_delayed_work(work); 830660fc733SEric Anholt struct bcm2835_host *host = 831660fc733SEric Anholt container_of(d, struct bcm2835_host, timeout_work); 832660fc733SEric Anholt struct device *dev = &host->pdev->dev; 833660fc733SEric Anholt 834660fc733SEric Anholt mutex_lock(&host->mutex); 835660fc733SEric Anholt 836660fc733SEric Anholt if (host->mrq) { 837660fc733SEric Anholt dev_err(dev, "timeout waiting for hardware interrupt.\n"); 838660fc733SEric Anholt bcm2835_dumpregs(host); 839660fc733SEric Anholt 840f6000a4eSMichal Suchanek bcm2835_reset(host->mmc); 841f6000a4eSMichal Suchanek 842660fc733SEric Anholt if (host->data) { 843660fc733SEric Anholt host->data->error = -ETIMEDOUT; 844660fc733SEric Anholt bcm2835_finish_data(host); 845660fc733SEric Anholt } else { 846660fc733SEric Anholt if (host->cmd) 847660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 848660fc733SEric Anholt else 849660fc733SEric Anholt host->mrq->cmd->error = -ETIMEDOUT; 850660fc733SEric Anholt 851660fc733SEric Anholt bcm2835_finish_request(host); 852660fc733SEric Anholt } 853660fc733SEric Anholt } 854660fc733SEric Anholt 855660fc733SEric Anholt mutex_unlock(&host->mutex); 856660fc733SEric Anholt } 857660fc733SEric Anholt 858660fc733SEric Anholt static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 859660fc733SEric Anholt { 860660fc733SEric Anholt struct device *dev = &host->pdev->dev; 861660fc733SEric Anholt 862660fc733SEric Anholt if (!(intmask & SDHSTS_ERROR_MASK)) 863660fc733SEric Anholt return false; 864660fc733SEric Anholt 865660fc733SEric Anholt if (!host->cmd) 866660fc733SEric Anholt return true; 867660fc733SEric Anholt 868660fc733SEric Anholt dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask); 869660fc733SEric Anholt if (intmask & SDHSTS_CRC7_ERROR) { 870660fc733SEric Anholt host->cmd->error = -EILSEQ; 871660fc733SEric Anholt } else if (intmask & (SDHSTS_CRC16_ERROR | 872660fc733SEric Anholt SDHSTS_FIFO_ERROR)) { 873660fc733SEric Anholt if (host->mrq->data) 874660fc733SEric Anholt host->mrq->data->error = -EILSEQ; 875660fc733SEric Anholt else 876660fc733SEric Anholt host->cmd->error = -EILSEQ; 877660fc733SEric Anholt } else if (intmask & SDHSTS_REW_TIME_OUT) { 878660fc733SEric Anholt if (host->mrq->data) 879660fc733SEric Anholt host->mrq->data->error = -ETIMEDOUT; 880660fc733SEric Anholt else 881660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 882660fc733SEric Anholt } else if (intmask & SDHSTS_CMD_TIME_OUT) { 883660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 884660fc733SEric Anholt } 885660fc733SEric Anholt bcm2835_dumpregs(host); 886660fc733SEric Anholt return true; 887660fc733SEric Anholt } 888660fc733SEric Anholt 889660fc733SEric Anholt static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 890660fc733SEric Anholt { 891660fc733SEric Anholt if (!host->data) 892660fc733SEric Anholt return; 893660fc733SEric Anholt if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 894660fc733SEric Anholt host->data->error = -EILSEQ; 895660fc733SEric Anholt if (intmask & SDHSTS_REW_TIME_OUT) 896660fc733SEric Anholt host->data->error = -ETIMEDOUT; 897660fc733SEric Anholt } 898660fc733SEric Anholt 899660fc733SEric Anholt static void bcm2835_busy_irq(struct bcm2835_host *host) 900660fc733SEric Anholt { 901660fc733SEric Anholt if (WARN_ON(!host->cmd)) { 902660fc733SEric Anholt bcm2835_dumpregs(host); 903660fc733SEric Anholt return; 904660fc733SEric Anholt } 905660fc733SEric Anholt 906660fc733SEric Anholt if (WARN_ON(!host->use_busy)) { 907660fc733SEric Anholt bcm2835_dumpregs(host); 908660fc733SEric Anholt return; 909660fc733SEric Anholt } 910660fc733SEric Anholt host->use_busy = false; 911660fc733SEric Anholt 912660fc733SEric Anholt bcm2835_finish_command(host); 913660fc733SEric Anholt } 914660fc733SEric Anholt 915660fc733SEric Anholt static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 916660fc733SEric Anholt { 917660fc733SEric Anholt /* There are no dedicated data/space available interrupt 918660fc733SEric Anholt * status bits, so it is necessary to use the single shared 919660fc733SEric Anholt * data/space available FIFO status bits. It is therefore not 920660fc733SEric Anholt * an error to get here when there is no data transfer in 921660fc733SEric Anholt * progress. 922660fc733SEric Anholt */ 923660fc733SEric Anholt if (!host->data) 924660fc733SEric Anholt return; 925660fc733SEric Anholt 926660fc733SEric Anholt bcm2835_check_data_error(host, intmask); 927660fc733SEric Anholt if (host->data->error) 928660fc733SEric Anholt goto finished; 929660fc733SEric Anholt 930660fc733SEric Anholt if (host->data->flags & MMC_DATA_WRITE) { 931660fc733SEric Anholt /* Use the block interrupt for writes after the first block */ 932660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 933660fc733SEric Anholt host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 934660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 935660fc733SEric Anholt bcm2835_transfer_pio(host); 936660fc733SEric Anholt } else { 937660fc733SEric Anholt bcm2835_transfer_pio(host); 938660fc733SEric Anholt host->blocks--; 939660fc733SEric Anholt if ((host->blocks == 0) || host->data->error) 940660fc733SEric Anholt goto finished; 941660fc733SEric Anholt } 942660fc733SEric Anholt return; 943660fc733SEric Anholt 944660fc733SEric Anholt finished: 945660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 946660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 947660fc733SEric Anholt } 948660fc733SEric Anholt 949660fc733SEric Anholt static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 950660fc733SEric Anholt { 951660fc733SEric Anholt if (!host->data) 952660fc733SEric Anholt return; 953660fc733SEric Anholt if ((host->blocks == 0) || host->data->error) 954660fc733SEric Anholt bcm2835_finish_data(host); 955660fc733SEric Anholt } 956660fc733SEric Anholt 957660fc733SEric Anholt static void bcm2835_block_irq(struct bcm2835_host *host) 958660fc733SEric Anholt { 959660fc733SEric Anholt if (WARN_ON(!host->data)) { 960660fc733SEric Anholt bcm2835_dumpregs(host); 961660fc733SEric Anholt return; 962660fc733SEric Anholt } 963660fc733SEric Anholt 964660fc733SEric Anholt if (!host->dma_desc) { 965660fc733SEric Anholt WARN_ON(!host->blocks); 966660fc733SEric Anholt if (host->data->error || (--host->blocks == 0)) 967660fc733SEric Anholt bcm2835_finish_data(host); 968660fc733SEric Anholt else 969660fc733SEric Anholt bcm2835_transfer_pio(host); 970660fc733SEric Anholt } else if (host->data->flags & MMC_DATA_WRITE) { 971660fc733SEric Anholt bcm2835_finish_data(host); 972660fc733SEric Anholt } 973660fc733SEric Anholt } 974660fc733SEric Anholt 975660fc733SEric Anholt static irqreturn_t bcm2835_irq(int irq, void *dev_id) 976660fc733SEric Anholt { 977660fc733SEric Anholt irqreturn_t result = IRQ_NONE; 978660fc733SEric Anholt struct bcm2835_host *host = dev_id; 979660fc733SEric Anholt u32 intmask; 980660fc733SEric Anholt 981660fc733SEric Anholt spin_lock(&host->lock); 982660fc733SEric Anholt 983660fc733SEric Anholt intmask = readl(host->ioaddr + SDHSTS); 984660fc733SEric Anholt 985660fc733SEric Anholt writel(SDHSTS_BUSY_IRPT | 986660fc733SEric Anholt SDHSTS_BLOCK_IRPT | 987660fc733SEric Anholt SDHSTS_SDIO_IRPT | 988660fc733SEric Anholt SDHSTS_DATA_FLAG, 989660fc733SEric Anholt host->ioaddr + SDHSTS); 990660fc733SEric Anholt 991660fc733SEric Anholt if (intmask & SDHSTS_BLOCK_IRPT) { 992660fc733SEric Anholt bcm2835_check_data_error(host, intmask); 993660fc733SEric Anholt host->irq_block = true; 994660fc733SEric Anholt result = IRQ_WAKE_THREAD; 995660fc733SEric Anholt } 996660fc733SEric Anholt 997660fc733SEric Anholt if (intmask & SDHSTS_BUSY_IRPT) { 998660fc733SEric Anholt if (!bcm2835_check_cmd_error(host, intmask)) { 999660fc733SEric Anholt host->irq_busy = true; 1000660fc733SEric Anholt result = IRQ_WAKE_THREAD; 1001660fc733SEric Anholt } else { 1002660fc733SEric Anholt result = IRQ_HANDLED; 1003660fc733SEric Anholt } 1004660fc733SEric Anholt } 1005660fc733SEric Anholt 1006660fc733SEric Anholt /* There is no true data interrupt status bit, so it is 1007660fc733SEric Anholt * necessary to qualify the data flag with the interrupt 1008660fc733SEric Anholt * enable bit. 1009660fc733SEric Anholt */ 1010660fc733SEric Anholt if ((intmask & SDHSTS_DATA_FLAG) && 1011660fc733SEric Anholt (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 1012660fc733SEric Anholt bcm2835_data_irq(host, intmask); 1013660fc733SEric Anholt host->irq_data = true; 1014660fc733SEric Anholt result = IRQ_WAKE_THREAD; 1015660fc733SEric Anholt } 1016660fc733SEric Anholt 1017660fc733SEric Anholt spin_unlock(&host->lock); 1018660fc733SEric Anholt 1019660fc733SEric Anholt return result; 1020660fc733SEric Anholt } 1021660fc733SEric Anholt 1022660fc733SEric Anholt static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 1023660fc733SEric Anholt { 1024660fc733SEric Anholt struct bcm2835_host *host = dev_id; 1025660fc733SEric Anholt unsigned long flags; 1026660fc733SEric Anholt bool block, busy, data; 1027660fc733SEric Anholt 1028660fc733SEric Anholt spin_lock_irqsave(&host->lock, flags); 1029660fc733SEric Anholt 1030660fc733SEric Anholt block = host->irq_block; 1031660fc733SEric Anholt busy = host->irq_busy; 1032660fc733SEric Anholt data = host->irq_data; 1033660fc733SEric Anholt host->irq_block = false; 1034660fc733SEric Anholt host->irq_busy = false; 1035660fc733SEric Anholt host->irq_data = false; 1036660fc733SEric Anholt 1037660fc733SEric Anholt spin_unlock_irqrestore(&host->lock, flags); 1038660fc733SEric Anholt 1039660fc733SEric Anholt mutex_lock(&host->mutex); 1040660fc733SEric Anholt 1041660fc733SEric Anholt if (block) 1042660fc733SEric Anholt bcm2835_block_irq(host); 1043660fc733SEric Anholt if (busy) 1044660fc733SEric Anholt bcm2835_busy_irq(host); 1045660fc733SEric Anholt if (data) 1046660fc733SEric Anholt bcm2835_data_threaded_irq(host); 1047660fc733SEric Anholt 1048660fc733SEric Anholt mutex_unlock(&host->mutex); 1049660fc733SEric Anholt 1050660fc733SEric Anholt return IRQ_HANDLED; 1051660fc733SEric Anholt } 1052660fc733SEric Anholt 1053660fc733SEric Anholt static void bcm2835_dma_complete_work(struct work_struct *work) 1054660fc733SEric Anholt { 1055660fc733SEric Anholt struct bcm2835_host *host = 1056660fc733SEric Anholt container_of(work, struct bcm2835_host, dma_work); 1057af19b7ceSStefan Wahren struct mmc_data *data; 1058660fc733SEric Anholt 1059660fc733SEric Anholt mutex_lock(&host->mutex); 1060660fc733SEric Anholt 1061af19b7ceSStefan Wahren data = host->data; 1062af19b7ceSStefan Wahren 1063660fc733SEric Anholt if (host->dma_chan) { 1064660fc733SEric Anholt dma_unmap_sg(host->dma_chan->device->dev, 1065660fc733SEric Anholt data->sg, data->sg_len, 1066660fc733SEric Anholt host->dma_dir); 1067660fc733SEric Anholt 1068660fc733SEric Anholt host->dma_chan = NULL; 1069660fc733SEric Anholt } 1070660fc733SEric Anholt 1071660fc733SEric Anholt if (host->drain_words) { 1072660fc733SEric Anholt unsigned long flags; 1073660fc733SEric Anholt void *page; 1074660fc733SEric Anholt u32 *buf; 1075660fc733SEric Anholt 1076660fc733SEric Anholt if (host->drain_offset & PAGE_MASK) { 1077660fc733SEric Anholt host->drain_page += host->drain_offset >> PAGE_SHIFT; 1078660fc733SEric Anholt host->drain_offset &= ~PAGE_MASK; 1079660fc733SEric Anholt } 1080660fc733SEric Anholt local_irq_save(flags); 1081660fc733SEric Anholt page = kmap_atomic(host->drain_page); 1082660fc733SEric Anholt buf = page + host->drain_offset; 1083660fc733SEric Anholt 1084660fc733SEric Anholt while (host->drain_words) { 1085660fc733SEric Anholt u32 edm = readl(host->ioaddr + SDEDM); 1086660fc733SEric Anholt 1087660fc733SEric Anholt if ((edm >> 4) & 0x1f) 1088660fc733SEric Anholt *(buf++) = readl(host->ioaddr + SDDATA); 1089660fc733SEric Anholt host->drain_words--; 1090660fc733SEric Anholt } 1091660fc733SEric Anholt 1092660fc733SEric Anholt kunmap_atomic(page); 1093660fc733SEric Anholt local_irq_restore(flags); 1094660fc733SEric Anholt } 1095660fc733SEric Anholt 1096660fc733SEric Anholt bcm2835_finish_data(host); 1097660fc733SEric Anholt 1098660fc733SEric Anholt mutex_unlock(&host->mutex); 1099660fc733SEric Anholt } 1100660fc733SEric Anholt 1101660fc733SEric Anholt static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 1102660fc733SEric Anholt { 1103660fc733SEric Anholt int div; 1104660fc733SEric Anholt 1105660fc733SEric Anholt /* The SDCDIV register has 11 bits, and holds (div - 2). But 1106660fc733SEric Anholt * in data mode the max is 50MHz wihout a minimum, and only 1107660fc733SEric Anholt * the bottom 3 bits are used. Since the switch over is 1108660fc733SEric Anholt * automatic (unless we have marked the card as slow...), 1109660fc733SEric Anholt * chosen values have to make sense in both modes. Ident mode 1110660fc733SEric Anholt * must be 100-400KHz, so can range check the requested 1111660fc733SEric Anholt * clock. CMD15 must be used to return to data mode, so this 1112660fc733SEric Anholt * can be monitored. 1113660fc733SEric Anholt * 1114660fc733SEric Anholt * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 1115660fc733SEric Anholt * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 1116660fc733SEric Anholt * 1117660fc733SEric Anholt * 623->400KHz/27.8MHz 1118660fc733SEric Anholt * reset value (507)->491159/50MHz 1119660fc733SEric Anholt * 1120660fc733SEric Anholt * BUT, the 3-bit clock divisor in data mode is too small if 1121660fc733SEric Anholt * the core clock is higher than 250MHz, so instead use the 1122660fc733SEric Anholt * SLOW_CARD configuration bit to force the use of the ident 1123660fc733SEric Anholt * clock divisor at all times. 1124660fc733SEric Anholt */ 1125660fc733SEric Anholt 1126660fc733SEric Anholt if (clock < 100000) { 1127660fc733SEric Anholt /* Can't stop the clock, but make it as slow as possible 1128660fc733SEric Anholt * to show willing 1129660fc733SEric Anholt */ 1130660fc733SEric Anholt host->cdiv = SDCDIV_MAX_CDIV; 1131660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 1132660fc733SEric Anholt return; 1133660fc733SEric Anholt } 1134660fc733SEric Anholt 1135660fc733SEric Anholt div = host->max_clk / clock; 1136660fc733SEric Anholt if (div < 2) 1137660fc733SEric Anholt div = 2; 1138660fc733SEric Anholt if ((host->max_clk / div) > clock) 1139660fc733SEric Anholt div++; 1140660fc733SEric Anholt div -= 2; 1141660fc733SEric Anholt 1142660fc733SEric Anholt if (div > SDCDIV_MAX_CDIV) 1143660fc733SEric Anholt div = SDCDIV_MAX_CDIV; 1144660fc733SEric Anholt 1145660fc733SEric Anholt clock = host->max_clk / (div + 2); 1146660fc733SEric Anholt host->mmc->actual_clock = clock; 1147660fc733SEric Anholt 1148660fc733SEric Anholt /* Calibrate some delays */ 1149660fc733SEric Anholt 1150660fc733SEric Anholt host->ns_per_fifo_word = (1000000000 / clock) * 1151660fc733SEric Anholt ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32); 1152660fc733SEric Anholt 1153660fc733SEric Anholt host->cdiv = div; 1154660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 1155660fc733SEric Anholt 1156660fc733SEric Anholt /* Set the timeout to 500ms */ 1157660fc733SEric Anholt writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT); 1158660fc733SEric Anholt } 1159660fc733SEric Anholt 1160660fc733SEric Anholt static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq) 1161660fc733SEric Anholt { 1162660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 1163660fc733SEric Anholt struct device *dev = &host->pdev->dev; 1164660fc733SEric Anholt u32 edm, fsm; 1165660fc733SEric Anholt 1166660fc733SEric Anholt /* Reset the error statuses in case this is a retry */ 1167660fc733SEric Anholt if (mrq->sbc) 1168660fc733SEric Anholt mrq->sbc->error = 0; 1169660fc733SEric Anholt if (mrq->cmd) 1170660fc733SEric Anholt mrq->cmd->error = 0; 1171660fc733SEric Anholt if (mrq->data) 1172660fc733SEric Anholt mrq->data->error = 0; 1173660fc733SEric Anholt if (mrq->stop) 1174660fc733SEric Anholt mrq->stop->error = 0; 1175660fc733SEric Anholt 1176660fc733SEric Anholt if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1177660fc733SEric Anholt dev_err(dev, "unsupported block size (%d bytes)\n", 1178660fc733SEric Anholt mrq->data->blksz); 1179c00a231bSGustavo A. R. Silva 1180c00a231bSGustavo A. R. Silva if (mrq->cmd) 1181660fc733SEric Anholt mrq->cmd->error = -EINVAL; 1182c00a231bSGustavo A. R. Silva 1183660fc733SEric Anholt mmc_request_done(mmc, mrq); 1184660fc733SEric Anholt return; 1185660fc733SEric Anholt } 1186660fc733SEric Anholt 1187660fc733SEric Anholt mutex_lock(&host->mutex); 1188660fc733SEric Anholt 1189660fc733SEric Anholt WARN_ON(host->mrq); 1190660fc733SEric Anholt host->mrq = mrq; 1191660fc733SEric Anholt 1192660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 1193660fc733SEric Anholt fsm = edm & SDEDM_FSM_MASK; 1194660fc733SEric Anholt 1195660fc733SEric Anholt if ((fsm != SDEDM_FSM_IDENTMODE) && 1196660fc733SEric Anholt (fsm != SDEDM_FSM_DATAMODE)) { 1197660fc733SEric Anholt dev_err(dev, "previous command (%d) not complete (EDM %08x)\n", 1198660fc733SEric Anholt readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, 1199660fc733SEric Anholt edm); 1200660fc733SEric Anholt bcm2835_dumpregs(host); 1201c00a231bSGustavo A. R. Silva 1202c00a231bSGustavo A. R. Silva if (mrq->cmd) 1203660fc733SEric Anholt mrq->cmd->error = -EILSEQ; 1204c00a231bSGustavo A. R. Silva 1205660fc733SEric Anholt bcm2835_finish_request(host); 1206660fc733SEric Anholt mutex_unlock(&host->mutex); 1207660fc733SEric Anholt return; 1208660fc733SEric Anholt } 1209660fc733SEric Anholt 1210af19b7ceSStefan Wahren if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD)) 1211af19b7ceSStefan Wahren bcm2835_prepare_dma(host, mrq->data); 1212af19b7ceSStefan Wahren 1213bf3240baSStefan Wahren host->use_sbc = !!mrq->sbc && host->mrq->data && 1214bf3240baSStefan Wahren (host->mrq->data->flags & MMC_DATA_READ); 1215660fc733SEric Anholt if (host->use_sbc) { 1216660fc733SEric Anholt if (bcm2835_send_command(host, mrq->sbc)) { 1217660fc733SEric Anholt if (!host->use_busy) 1218660fc733SEric Anholt bcm2835_finish_command(host); 1219660fc733SEric Anholt } 1220c00a231bSGustavo A. R. Silva } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) { 1221660fc733SEric Anholt if (host->data && host->dma_desc) { 1222660fc733SEric Anholt /* DMA transfer starts now, PIO starts after irq */ 1223660fc733SEric Anholt bcm2835_start_dma(host); 1224660fc733SEric Anholt } 1225660fc733SEric Anholt 1226660fc733SEric Anholt if (!host->use_busy) 1227660fc733SEric Anholt bcm2835_finish_command(host); 1228660fc733SEric Anholt } 1229660fc733SEric Anholt 1230660fc733SEric Anholt mutex_unlock(&host->mutex); 1231660fc733SEric Anholt } 1232660fc733SEric Anholt 1233660fc733SEric Anholt static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1234660fc733SEric Anholt { 1235660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 1236660fc733SEric Anholt 1237660fc733SEric Anholt mutex_lock(&host->mutex); 1238660fc733SEric Anholt 1239660fc733SEric Anholt if (!ios->clock || ios->clock != host->clock) { 1240660fc733SEric Anholt bcm2835_set_clock(host, ios->clock); 1241660fc733SEric Anholt host->clock = ios->clock; 1242660fc733SEric Anholt } 1243660fc733SEric Anholt 1244660fc733SEric Anholt /* set bus width */ 1245660fc733SEric Anholt host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 1246660fc733SEric Anholt if (ios->bus_width == MMC_BUS_WIDTH_4) 1247660fc733SEric Anholt host->hcfg |= SDHCFG_WIDE_EXT_BUS; 1248660fc733SEric Anholt 1249660fc733SEric Anholt host->hcfg |= SDHCFG_WIDE_INT_BUS; 1250660fc733SEric Anholt 1251660fc733SEric Anholt /* Disable clever clock switching, to cope with fast core clocks */ 1252660fc733SEric Anholt host->hcfg |= SDHCFG_SLOW_CARD; 1253660fc733SEric Anholt 1254660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 1255660fc733SEric Anholt 1256660fc733SEric Anholt mutex_unlock(&host->mutex); 1257660fc733SEric Anholt } 1258660fc733SEric Anholt 12592c9e89a1SJulia Lawall static const struct mmc_host_ops bcm2835_ops = { 1260660fc733SEric Anholt .request = bcm2835_request, 1261660fc733SEric Anholt .set_ios = bcm2835_set_ios, 1262660fc733SEric Anholt .hw_reset = bcm2835_reset, 1263660fc733SEric Anholt }; 1264660fc733SEric Anholt 1265660fc733SEric Anholt static int bcm2835_add_host(struct bcm2835_host *host) 1266660fc733SEric Anholt { 1267660fc733SEric Anholt struct mmc_host *mmc = host->mmc; 1268660fc733SEric Anholt struct device *dev = &host->pdev->dev; 1269660fc733SEric Anholt char pio_limit_string[20]; 1270660fc733SEric Anholt int ret; 1271660fc733SEric Anholt 1272118032beSPhil Elwell if (!mmc->f_max || mmc->f_max > host->max_clk) 1273660fc733SEric Anholt mmc->f_max = host->max_clk; 1274660fc733SEric Anholt mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; 1275660fc733SEric Anholt 1276660fc733SEric Anholt mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000); 1277660fc733SEric Anholt 1278660fc733SEric Anholt dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n", 1279660fc733SEric Anholt mmc->f_max, mmc->f_min, mmc->max_busy_timeout); 1280660fc733SEric Anholt 1281660fc733SEric Anholt /* host controller capabilities */ 1282660fc733SEric Anholt mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 1283660fc733SEric Anholt MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | 1284660fc733SEric Anholt MMC_CAP_CMD23; 1285660fc733SEric Anholt 1286660fc733SEric Anholt spin_lock_init(&host->lock); 1287660fc733SEric Anholt mutex_init(&host->mutex); 1288660fc733SEric Anholt 1289e5c1e63cSLukas Wunner if (!host->dma_chan_rxtx) { 1290660fc733SEric Anholt dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n"); 1291660fc733SEric Anholt host->use_dma = false; 1292660fc733SEric Anholt } else { 1293660fc733SEric Anholt host->use_dma = true; 1294660fc733SEric Anholt 1295660fc733SEric Anholt host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1296660fc733SEric Anholt host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1297660fc733SEric Anholt host->dma_cfg_tx.slave_id = 13; /* DREQ channel */ 1298660fc733SEric Anholt host->dma_cfg_tx.direction = DMA_MEM_TO_DEV; 1299660fc733SEric Anholt host->dma_cfg_tx.src_addr = 0; 1300660fc733SEric Anholt host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA; 1301660fc733SEric Anholt 1302660fc733SEric Anholt host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1303660fc733SEric Anholt host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1304660fc733SEric Anholt host->dma_cfg_rx.slave_id = 13; /* DREQ channel */ 1305660fc733SEric Anholt host->dma_cfg_rx.direction = DMA_DEV_TO_MEM; 1306660fc733SEric Anholt host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA; 1307660fc733SEric Anholt host->dma_cfg_rx.dst_addr = 0; 1308660fc733SEric Anholt 1309660fc733SEric Anholt if (dmaengine_slave_config(host->dma_chan_rxtx, 1310660fc733SEric Anholt &host->dma_cfg_tx) != 0 || 1311660fc733SEric Anholt dmaengine_slave_config(host->dma_chan_rxtx, 1312660fc733SEric Anholt &host->dma_cfg_rx) != 0) 1313660fc733SEric Anholt host->use_dma = false; 1314660fc733SEric Anholt } 1315660fc733SEric Anholt 1316660fc733SEric Anholt mmc->max_segs = 128; 1317660fc733SEric Anholt mmc->max_req_size = 524288; 1318660fc733SEric Anholt mmc->max_seg_size = mmc->max_req_size; 1319660fc733SEric Anholt mmc->max_blk_size = 1024; 1320660fc733SEric Anholt mmc->max_blk_count = 65535; 1321660fc733SEric Anholt 1322660fc733SEric Anholt /* report supported voltage ranges */ 1323660fc733SEric Anholt mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1324660fc733SEric Anholt 1325660fc733SEric Anholt INIT_WORK(&host->dma_work, bcm2835_dma_complete_work); 1326660fc733SEric Anholt INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout); 1327660fc733SEric Anholt 1328660fc733SEric Anholt /* Set interrupt enables */ 1329660fc733SEric Anholt host->hcfg = SDHCFG_BUSY_IRPT_EN; 1330660fc733SEric Anholt 1331660fc733SEric Anholt bcm2835_reset_internal(host); 1332660fc733SEric Anholt 1333660fc733SEric Anholt ret = request_threaded_irq(host->irq, bcm2835_irq, 1334660fc733SEric Anholt bcm2835_threaded_irq, 1335660fc733SEric Anholt 0, mmc_hostname(mmc), host); 1336660fc733SEric Anholt if (ret) { 1337660fc733SEric Anholt dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret); 1338660fc733SEric Anholt return ret; 1339660fc733SEric Anholt } 1340660fc733SEric Anholt 1341660fc733SEric Anholt ret = mmc_add_host(mmc); 1342660fc733SEric Anholt if (ret) { 1343660fc733SEric Anholt free_irq(host->irq, host); 1344660fc733SEric Anholt return ret; 1345660fc733SEric Anholt } 1346660fc733SEric Anholt 1347660fc733SEric Anholt pio_limit_string[0] = '\0'; 1348660fc733SEric Anholt if (host->use_dma && (PIO_THRESHOLD > 0)) 1349660fc733SEric Anholt sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD); 1350660fc733SEric Anholt dev_info(dev, "loaded - DMA %s%s\n", 1351660fc733SEric Anholt host->use_dma ? "enabled" : "disabled", pio_limit_string); 1352660fc733SEric Anholt 1353660fc733SEric Anholt return 0; 1354660fc733SEric Anholt } 1355660fc733SEric Anholt 1356660fc733SEric Anholt static int bcm2835_probe(struct platform_device *pdev) 1357660fc733SEric Anholt { 1358660fc733SEric Anholt struct device *dev = &pdev->dev; 1359660fc733SEric Anholt struct clk *clk; 1360660fc733SEric Anholt struct resource *iomem; 1361660fc733SEric Anholt struct bcm2835_host *host; 1362660fc733SEric Anholt struct mmc_host *mmc; 1363660fc733SEric Anholt const __be32 *regaddr_p; 1364660fc733SEric Anholt int ret; 1365660fc733SEric Anholt 1366660fc733SEric Anholt dev_dbg(dev, "%s\n", __func__); 1367660fc733SEric Anholt mmc = mmc_alloc_host(sizeof(*host), dev); 1368660fc733SEric Anholt if (!mmc) 1369660fc733SEric Anholt return -ENOMEM; 1370660fc733SEric Anholt 1371660fc733SEric Anholt mmc->ops = &bcm2835_ops; 1372660fc733SEric Anholt host = mmc_priv(mmc); 1373660fc733SEric Anholt host->mmc = mmc; 1374660fc733SEric Anholt host->pdev = pdev; 1375660fc733SEric Anholt spin_lock_init(&host->lock); 1376660fc733SEric Anholt 1377660fc733SEric Anholt iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1378660fc733SEric Anholt host->ioaddr = devm_ioremap_resource(dev, iomem); 1379660fc733SEric Anholt if (IS_ERR(host->ioaddr)) { 1380660fc733SEric Anholt ret = PTR_ERR(host->ioaddr); 1381660fc733SEric Anholt goto err; 1382660fc733SEric Anholt } 1383660fc733SEric Anholt 1384660fc733SEric Anholt /* Parse OF address directly to get the physical address for 1385660fc733SEric Anholt * DMA to our registers. 1386660fc733SEric Anholt */ 1387660fc733SEric Anholt regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 1388660fc733SEric Anholt if (!regaddr_p) { 1389660fc733SEric Anholt dev_err(dev, "Can't get phys address\n"); 1390660fc733SEric Anholt ret = -EINVAL; 1391660fc733SEric Anholt goto err; 1392660fc733SEric Anholt } 1393660fc733SEric Anholt 1394660fc733SEric Anholt host->phys_addr = be32_to_cpup(regaddr_p); 1395660fc733SEric Anholt 1396660fc733SEric Anholt host->dma_chan = NULL; 1397660fc733SEric Anholt host->dma_desc = NULL; 1398660fc733SEric Anholt 1399660fc733SEric Anholt host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx"); 1400660fc733SEric Anholt 1401660fc733SEric Anholt clk = devm_clk_get(dev, NULL); 1402660fc733SEric Anholt if (IS_ERR(clk)) { 1403660fc733SEric Anholt ret = PTR_ERR(clk); 1404660fc733SEric Anholt if (ret != -EPROBE_DEFER) 1405660fc733SEric Anholt dev_err(dev, "could not get clk: %d\n", ret); 1406660fc733SEric Anholt goto err; 1407660fc733SEric Anholt } 1408660fc733SEric Anholt 1409660fc733SEric Anholt host->max_clk = clk_get_rate(clk); 1410660fc733SEric Anholt 1411660fc733SEric Anholt host->irq = platform_get_irq(pdev, 0); 1412660fc733SEric Anholt if (host->irq <= 0) { 1413660fc733SEric Anholt dev_err(dev, "get IRQ failed\n"); 1414660fc733SEric Anholt ret = -EINVAL; 1415660fc733SEric Anholt goto err; 1416660fc733SEric Anholt } 1417660fc733SEric Anholt 1418660fc733SEric Anholt ret = mmc_of_parse(mmc); 1419660fc733SEric Anholt if (ret) 1420660fc733SEric Anholt goto err; 1421660fc733SEric Anholt 1422660fc733SEric Anholt ret = bcm2835_add_host(host); 1423660fc733SEric Anholt if (ret) 1424660fc733SEric Anholt goto err; 1425660fc733SEric Anholt 1426660fc733SEric Anholt platform_set_drvdata(pdev, host); 1427660fc733SEric Anholt 1428660fc733SEric Anholt dev_dbg(dev, "%s -> OK\n", __func__); 1429660fc733SEric Anholt 1430660fc733SEric Anholt return 0; 1431660fc733SEric Anholt 1432660fc733SEric Anholt err: 1433660fc733SEric Anholt dev_dbg(dev, "%s -> err %d\n", __func__, ret); 14348c9620b1SLukas Wunner if (host->dma_chan_rxtx) 14358c9620b1SLukas Wunner dma_release_channel(host->dma_chan_rxtx); 1436660fc733SEric Anholt mmc_free_host(mmc); 1437660fc733SEric Anholt 1438660fc733SEric Anholt return ret; 1439660fc733SEric Anholt } 1440660fc733SEric Anholt 1441660fc733SEric Anholt static int bcm2835_remove(struct platform_device *pdev) 1442660fc733SEric Anholt { 1443660fc733SEric Anholt struct bcm2835_host *host = platform_get_drvdata(pdev); 1444660fc733SEric Anholt 1445660fc733SEric Anholt mmc_remove_host(host->mmc); 1446660fc733SEric Anholt 1447660fc733SEric Anholt writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 1448660fc733SEric Anholt 1449660fc733SEric Anholt free_irq(host->irq, host); 1450660fc733SEric Anholt 1451660fc733SEric Anholt cancel_work_sync(&host->dma_work); 1452660fc733SEric Anholt cancel_delayed_work_sync(&host->timeout_work); 1453660fc733SEric Anholt 14545eae252dSStefan Wahren if (host->dma_chan_rxtx) 14555eae252dSStefan Wahren dma_release_channel(host->dma_chan_rxtx); 14565eae252dSStefan Wahren 1457660fc733SEric Anholt mmc_free_host(host->mmc); 1458660fc733SEric Anholt platform_set_drvdata(pdev, NULL); 1459660fc733SEric Anholt 1460660fc733SEric Anholt return 0; 1461660fc733SEric Anholt } 1462660fc733SEric Anholt 1463660fc733SEric Anholt static const struct of_device_id bcm2835_match[] = { 1464660fc733SEric Anholt { .compatible = "brcm,bcm2835-sdhost" }, 1465660fc733SEric Anholt { } 1466660fc733SEric Anholt }; 1467660fc733SEric Anholt MODULE_DEVICE_TABLE(of, bcm2835_match); 1468660fc733SEric Anholt 1469660fc733SEric Anholt static struct platform_driver bcm2835_driver = { 1470660fc733SEric Anholt .probe = bcm2835_probe, 1471660fc733SEric Anholt .remove = bcm2835_remove, 1472660fc733SEric Anholt .driver = { 1473660fc733SEric Anholt .name = "sdhost-bcm2835", 1474660fc733SEric Anholt .of_match_table = bcm2835_match, 1475660fc733SEric Anholt }, 1476660fc733SEric Anholt }; 1477660fc733SEric Anholt module_platform_driver(bcm2835_driver); 1478660fc733SEric Anholt 1479660fc733SEric Anholt MODULE_ALIAS("platform:sdhost-bcm2835"); 1480660fc733SEric Anholt MODULE_DESCRIPTION("BCM2835 SDHost driver"); 1481660fc733SEric Anholt MODULE_LICENSE("GPL v2"); 1482660fc733SEric Anholt MODULE_AUTHOR("Phil Elwell"); 1483