1660fc733SEric Anholt /* 2660fc733SEric Anholt * bcm2835 sdhost driver. 3660fc733SEric Anholt * 4660fc733SEric Anholt * The 2835 has two SD controllers: The Arasan sdhci controller 5660fc733SEric Anholt * (supported by the iproc driver) and a custom sdhost controller 6660fc733SEric Anholt * (supported by this driver). 7660fc733SEric Anholt * 8660fc733SEric Anholt * The sdhci controller supports both sdcard and sdio. The sdhost 9660fc733SEric Anholt * controller supports the sdcard only, but has better performance. 10660fc733SEric Anholt * Also note that the rpi3 has sdio wifi, so driving the sdcard with 11660fc733SEric Anholt * the sdhost controller allows to use the sdhci controller for wifi 12660fc733SEric Anholt * support. 13660fc733SEric Anholt * 14660fc733SEric Anholt * The configuration is done by devicetree via pin muxing. Both 15660fc733SEric Anholt * SD controller are available on the same pins (2 pin groups = pin 22 16660fc733SEric Anholt * to 27 + pin 48 to 53). So it's possible to use both SD controllers 17660fc733SEric Anholt * at the same time with different pin groups. 18660fc733SEric Anholt * 19660fc733SEric Anholt * Author: Phil Elwell <phil@raspberrypi.org> 20660fc733SEric Anholt * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 21660fc733SEric Anholt * 22660fc733SEric Anholt * Based on 23660fc733SEric Anholt * mmc-bcm2835.c by Gellert Weisz 24660fc733SEric Anholt * which is, in turn, based on 25660fc733SEric Anholt * sdhci-bcm2708.c by Broadcom 26660fc733SEric Anholt * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 27660fc733SEric Anholt * sdhci.c and sdhci-pci.c by Pierre Ossman 28660fc733SEric Anholt * 29660fc733SEric Anholt * This program is free software; you can redistribute it and/or modify it 30660fc733SEric Anholt * under the terms and conditions of the GNU General Public License, 31660fc733SEric Anholt * version 2, as published by the Free Software Foundation. 32660fc733SEric Anholt * 33660fc733SEric Anholt * This program is distributed in the hope it will be useful, but WITHOUT 34660fc733SEric Anholt * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 35660fc733SEric Anholt * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 36660fc733SEric Anholt * more details. 37660fc733SEric Anholt * 38660fc733SEric Anholt * You should have received a copy of the GNU General Public License 39660fc733SEric Anholt * along with this program. If not, see <http://www.gnu.org/licenses/>. 40660fc733SEric Anholt */ 41660fc733SEric Anholt #include <linux/clk.h> 42660fc733SEric Anholt #include <linux/delay.h> 43660fc733SEric Anholt #include <linux/device.h> 44660fc733SEric Anholt #include <linux/dmaengine.h> 45660fc733SEric Anholt #include <linux/dma-mapping.h> 46660fc733SEric Anholt #include <linux/err.h> 47660fc733SEric Anholt #include <linux/highmem.h> 48660fc733SEric Anholt #include <linux/interrupt.h> 49660fc733SEric Anholt #include <linux/io.h> 50660fc733SEric Anholt #include <linux/iopoll.h> 51660fc733SEric Anholt #include <linux/module.h> 52660fc733SEric Anholt #include <linux/of_address.h> 53660fc733SEric Anholt #include <linux/of_irq.h> 54660fc733SEric Anholt #include <linux/platform_device.h> 55660fc733SEric Anholt #include <linux/scatterlist.h> 56660fc733SEric Anholt #include <linux/time.h> 57660fc733SEric Anholt #include <linux/workqueue.h> 58660fc733SEric Anholt 59660fc733SEric Anholt #include <linux/mmc/host.h> 60660fc733SEric Anholt #include <linux/mmc/mmc.h> 61660fc733SEric Anholt #include <linux/mmc/sd.h> 62660fc733SEric Anholt 63660fc733SEric Anholt #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 64660fc733SEric Anholt #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 65660fc733SEric Anholt #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 66660fc733SEric Anholt #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 67660fc733SEric Anholt #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 68660fc733SEric Anholt #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 69660fc733SEric Anholt #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 70660fc733SEric Anholt #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 71660fc733SEric Anholt #define SDHSTS 0x20 /* SD host status - 11 R/W */ 72660fc733SEric Anholt #define SDVDD 0x30 /* SD card power control - 1 R/W */ 73660fc733SEric Anholt #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 74660fc733SEric Anholt #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 75660fc733SEric Anholt #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 76660fc733SEric Anholt #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 77660fc733SEric Anholt #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 78660fc733SEric Anholt 79660fc733SEric Anholt #define SDCMD_NEW_FLAG 0x8000 80660fc733SEric Anholt #define SDCMD_FAIL_FLAG 0x4000 81660fc733SEric Anholt #define SDCMD_BUSYWAIT 0x800 82660fc733SEric Anholt #define SDCMD_NO_RESPONSE 0x400 83660fc733SEric Anholt #define SDCMD_LONG_RESPONSE 0x200 84660fc733SEric Anholt #define SDCMD_WRITE_CMD 0x80 85660fc733SEric Anholt #define SDCMD_READ_CMD 0x40 86660fc733SEric Anholt #define SDCMD_CMD_MASK 0x3f 87660fc733SEric Anholt 88660fc733SEric Anholt #define SDCDIV_MAX_CDIV 0x7ff 89660fc733SEric Anholt 90660fc733SEric Anholt #define SDHSTS_BUSY_IRPT 0x400 91660fc733SEric Anholt #define SDHSTS_BLOCK_IRPT 0x200 92660fc733SEric Anholt #define SDHSTS_SDIO_IRPT 0x100 93660fc733SEric Anholt #define SDHSTS_REW_TIME_OUT 0x80 94660fc733SEric Anholt #define SDHSTS_CMD_TIME_OUT 0x40 95660fc733SEric Anholt #define SDHSTS_CRC16_ERROR 0x20 96660fc733SEric Anholt #define SDHSTS_CRC7_ERROR 0x10 97660fc733SEric Anholt #define SDHSTS_FIFO_ERROR 0x08 98660fc733SEric Anholt /* Reserved */ 99660fc733SEric Anholt /* Reserved */ 100660fc733SEric Anholt #define SDHSTS_DATA_FLAG 0x01 101660fc733SEric Anholt 102660fc733SEric Anholt #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 103660fc733SEric Anholt SDHSTS_CRC16_ERROR | \ 104660fc733SEric Anholt SDHSTS_REW_TIME_OUT | \ 105660fc733SEric Anholt SDHSTS_FIFO_ERROR) 106660fc733SEric Anholt 107660fc733SEric Anholt #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 108660fc733SEric Anholt SDHSTS_TRANSFER_ERROR_MASK) 109660fc733SEric Anholt 110660fc733SEric Anholt #define SDHCFG_BUSY_IRPT_EN BIT(10) 111660fc733SEric Anholt #define SDHCFG_BLOCK_IRPT_EN BIT(8) 112660fc733SEric Anholt #define SDHCFG_SDIO_IRPT_EN BIT(5) 113660fc733SEric Anholt #define SDHCFG_DATA_IRPT_EN BIT(4) 114660fc733SEric Anholt #define SDHCFG_SLOW_CARD BIT(3) 115660fc733SEric Anholt #define SDHCFG_WIDE_EXT_BUS BIT(2) 116660fc733SEric Anholt #define SDHCFG_WIDE_INT_BUS BIT(1) 117660fc733SEric Anholt #define SDHCFG_REL_CMD_LINE BIT(0) 118660fc733SEric Anholt 119660fc733SEric Anholt #define SDVDD_POWER_OFF 0 120660fc733SEric Anholt #define SDVDD_POWER_ON 1 121660fc733SEric Anholt 122660fc733SEric Anholt #define SDEDM_FORCE_DATA_MODE BIT(19) 123660fc733SEric Anholt #define SDEDM_CLOCK_PULSE BIT(20) 124660fc733SEric Anholt #define SDEDM_BYPASS BIT(21) 125660fc733SEric Anholt 126660fc733SEric Anholt #define SDEDM_WRITE_THRESHOLD_SHIFT 9 127660fc733SEric Anholt #define SDEDM_READ_THRESHOLD_SHIFT 14 128660fc733SEric Anholt #define SDEDM_THRESHOLD_MASK 0x1f 129660fc733SEric Anholt 130660fc733SEric Anholt #define SDEDM_FSM_MASK 0xf 131660fc733SEric Anholt #define SDEDM_FSM_IDENTMODE 0x0 132660fc733SEric Anholt #define SDEDM_FSM_DATAMODE 0x1 133660fc733SEric Anholt #define SDEDM_FSM_READDATA 0x2 134660fc733SEric Anholt #define SDEDM_FSM_WRITEDATA 0x3 135660fc733SEric Anholt #define SDEDM_FSM_READWAIT 0x4 136660fc733SEric Anholt #define SDEDM_FSM_READCRC 0x5 137660fc733SEric Anholt #define SDEDM_FSM_WRITECRC 0x6 138660fc733SEric Anholt #define SDEDM_FSM_WRITEWAIT1 0x7 139660fc733SEric Anholt #define SDEDM_FSM_POWERDOWN 0x8 140660fc733SEric Anholt #define SDEDM_FSM_POWERUP 0x9 141660fc733SEric Anholt #define SDEDM_FSM_WRITESTART1 0xa 142660fc733SEric Anholt #define SDEDM_FSM_WRITESTART2 0xb 143660fc733SEric Anholt #define SDEDM_FSM_GENPULSES 0xc 144660fc733SEric Anholt #define SDEDM_FSM_WRITEWAIT2 0xd 145660fc733SEric Anholt #define SDEDM_FSM_STARTPOWDOWN 0xf 146660fc733SEric Anholt 147660fc733SEric Anholt #define SDDATA_FIFO_WORDS 16 148660fc733SEric Anholt 149660fc733SEric Anholt #define FIFO_READ_THRESHOLD 4 150660fc733SEric Anholt #define FIFO_WRITE_THRESHOLD 4 151660fc733SEric Anholt #define SDDATA_FIFO_PIO_BURST 8 152660fc733SEric Anholt 153660fc733SEric Anholt #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */ 154660fc733SEric Anholt 155660fc733SEric Anholt struct bcm2835_host { 156660fc733SEric Anholt spinlock_t lock; 157660fc733SEric Anholt struct mutex mutex; 158660fc733SEric Anholt 159660fc733SEric Anholt void __iomem *ioaddr; 160660fc733SEric Anholt u32 phys_addr; 161660fc733SEric Anholt 162660fc733SEric Anholt struct mmc_host *mmc; 163660fc733SEric Anholt struct platform_device *pdev; 164660fc733SEric Anholt 165660fc733SEric Anholt int clock; /* Current clock speed */ 166660fc733SEric Anholt unsigned int max_clk; /* Max possible freq */ 167660fc733SEric Anholt struct work_struct dma_work; 168660fc733SEric Anholt struct delayed_work timeout_work; /* Timer for timeouts */ 169660fc733SEric Anholt struct sg_mapping_iter sg_miter; /* SG state for PIO */ 170660fc733SEric Anholt unsigned int blocks; /* remaining PIO blocks */ 171660fc733SEric Anholt int irq; /* Device IRQ */ 172660fc733SEric Anholt 173660fc733SEric Anholt u32 ns_per_fifo_word; 174660fc733SEric Anholt 175660fc733SEric Anholt /* cached registers */ 176660fc733SEric Anholt u32 hcfg; 177660fc733SEric Anholt u32 cdiv; 178660fc733SEric Anholt 179660fc733SEric Anholt struct mmc_request *mrq; /* Current request */ 180660fc733SEric Anholt struct mmc_command *cmd; /* Current command */ 181660fc733SEric Anholt struct mmc_data *data; /* Current data request */ 182660fc733SEric Anholt bool data_complete:1;/* Data finished before cmd */ 183660fc733SEric Anholt bool use_busy:1; /* Wait for busy interrupt */ 184660fc733SEric Anholt bool use_sbc:1; /* Send CMD23 */ 185660fc733SEric Anholt 186660fc733SEric Anholt /* for threaded irq handler */ 187660fc733SEric Anholt bool irq_block; 188660fc733SEric Anholt bool irq_busy; 189660fc733SEric Anholt bool irq_data; 190660fc733SEric Anholt 191660fc733SEric Anholt /* DMA part */ 192660fc733SEric Anholt struct dma_chan *dma_chan_rxtx; 193660fc733SEric Anholt struct dma_chan *dma_chan; 194660fc733SEric Anholt struct dma_slave_config dma_cfg_rx; 195660fc733SEric Anholt struct dma_slave_config dma_cfg_tx; 196660fc733SEric Anholt struct dma_async_tx_descriptor *dma_desc; 197660fc733SEric Anholt u32 dma_dir; 198660fc733SEric Anholt u32 drain_words; 199660fc733SEric Anholt struct page *drain_page; 200660fc733SEric Anholt u32 drain_offset; 201660fc733SEric Anholt bool use_dma; 202660fc733SEric Anholt }; 203660fc733SEric Anholt 204660fc733SEric Anholt static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd, 205660fc733SEric Anholt const char *label) 206660fc733SEric Anholt { 207660fc733SEric Anholt struct device *dev = &host->pdev->dev; 208660fc733SEric Anholt 209660fc733SEric Anholt if (!cmd) 210660fc733SEric Anholt return; 211660fc733SEric Anholt 212660fc733SEric Anholt dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", 213660fc733SEric Anholt (cmd == host->cmd) ? '>' : ' ', 214660fc733SEric Anholt label, cmd->opcode, cmd->arg, cmd->flags, 215660fc733SEric Anholt cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], 216660fc733SEric Anholt cmd->error); 217660fc733SEric Anholt } 218660fc733SEric Anholt 219660fc733SEric Anholt static void bcm2835_dumpregs(struct bcm2835_host *host) 220660fc733SEric Anholt { 221660fc733SEric Anholt struct mmc_request *mrq = host->mrq; 222660fc733SEric Anholt struct device *dev = &host->pdev->dev; 223660fc733SEric Anholt 224660fc733SEric Anholt if (mrq) { 225660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->sbc, "sbc"); 226660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->cmd, "cmd"); 227660fc733SEric Anholt if (mrq->data) { 228660fc733SEric Anholt dev_dbg(dev, "data blocks %x blksz %x - err %d\n", 229660fc733SEric Anholt mrq->data->blocks, 230660fc733SEric Anholt mrq->data->blksz, 231660fc733SEric Anholt mrq->data->error); 232660fc733SEric Anholt } 233660fc733SEric Anholt bcm2835_dumpcmd(host, mrq->stop, "stop"); 234660fc733SEric Anholt } 235660fc733SEric Anholt 236660fc733SEric Anholt dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 237660fc733SEric Anholt dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 238660fc733SEric Anholt dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 239660fc733SEric Anholt dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 240660fc733SEric Anholt dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 241660fc733SEric Anholt dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 242660fc733SEric Anholt dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 243660fc733SEric Anholt dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 244660fc733SEric Anholt dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 245660fc733SEric Anholt dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 246660fc733SEric Anholt dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 247660fc733SEric Anholt dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 248660fc733SEric Anholt dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 249660fc733SEric Anholt dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 250660fc733SEric Anholt dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 251660fc733SEric Anholt dev_dbg(dev, "===========================================\n"); 252660fc733SEric Anholt } 253660fc733SEric Anholt 254660fc733SEric Anholt static void bcm2835_reset_internal(struct bcm2835_host *host) 255660fc733SEric Anholt { 256660fc733SEric Anholt u32 temp; 257660fc733SEric Anholt 258660fc733SEric Anholt writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 259660fc733SEric Anholt writel(0, host->ioaddr + SDCMD); 260660fc733SEric Anholt writel(0, host->ioaddr + SDARG); 261660fc733SEric Anholt writel(0xf00000, host->ioaddr + SDTOUT); 262660fc733SEric Anholt writel(0, host->ioaddr + SDCDIV); 263660fc733SEric Anholt writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */ 264660fc733SEric Anholt writel(0, host->ioaddr + SDHCFG); 265660fc733SEric Anholt writel(0, host->ioaddr + SDHBCT); 266660fc733SEric Anholt writel(0, host->ioaddr + SDHBLC); 267660fc733SEric Anholt 268660fc733SEric Anholt /* Limit fifo usage due to silicon bug */ 269660fc733SEric Anholt temp = readl(host->ioaddr + SDEDM); 270660fc733SEric Anholt temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 271660fc733SEric Anholt (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 272660fc733SEric Anholt temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 273660fc733SEric Anholt (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 274660fc733SEric Anholt writel(temp, host->ioaddr + SDEDM); 275660fc733SEric Anholt msleep(20); 276660fc733SEric Anholt writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 277660fc733SEric Anholt msleep(20); 278660fc733SEric Anholt host->clock = 0; 279660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 280660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 281660fc733SEric Anholt } 282660fc733SEric Anholt 283660fc733SEric Anholt static void bcm2835_reset(struct mmc_host *mmc) 284660fc733SEric Anholt { 285660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 286660fc733SEric Anholt 287660fc733SEric Anholt if (host->dma_chan) 288660fc733SEric Anholt dmaengine_terminate_sync(host->dma_chan); 289660fc733SEric Anholt bcm2835_reset_internal(host); 290660fc733SEric Anholt } 291660fc733SEric Anholt 292660fc733SEric Anholt static void bcm2835_finish_command(struct bcm2835_host *host); 293660fc733SEric Anholt 294660fc733SEric Anholt static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 295660fc733SEric Anholt { 296660fc733SEric Anholt int timediff; 297660fc733SEric Anholt u32 alternate_idle; 298660fc733SEric Anholt 299660fc733SEric Anholt alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ? 300660fc733SEric Anholt SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 301660fc733SEric Anholt 302660fc733SEric Anholt timediff = 0; 303660fc733SEric Anholt 304660fc733SEric Anholt while (1) { 305660fc733SEric Anholt u32 edm, fsm; 306660fc733SEric Anholt 307660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 308660fc733SEric Anholt fsm = edm & SDEDM_FSM_MASK; 309660fc733SEric Anholt 310660fc733SEric Anholt if ((fsm == SDEDM_FSM_IDENTMODE) || 311660fc733SEric Anholt (fsm == SDEDM_FSM_DATAMODE)) 312660fc733SEric Anholt break; 313660fc733SEric Anholt if (fsm == alternate_idle) { 314660fc733SEric Anholt writel(edm | SDEDM_FORCE_DATA_MODE, 315660fc733SEric Anholt host->ioaddr + SDEDM); 316660fc733SEric Anholt break; 317660fc733SEric Anholt } 318660fc733SEric Anholt 319660fc733SEric Anholt timediff++; 320660fc733SEric Anholt if (timediff == 100000) { 321660fc733SEric Anholt dev_err(&host->pdev->dev, 322660fc733SEric Anholt "wait_transfer_complete - still waiting after %d retries\n", 323660fc733SEric Anholt timediff); 324660fc733SEric Anholt bcm2835_dumpregs(host); 325660fc733SEric Anholt host->mrq->data->error = -ETIMEDOUT; 326660fc733SEric Anholt return; 327660fc733SEric Anholt } 328660fc733SEric Anholt cpu_relax(); 329660fc733SEric Anholt } 330660fc733SEric Anholt } 331660fc733SEric Anholt 332660fc733SEric Anholt static void bcm2835_dma_complete(void *param) 333660fc733SEric Anholt { 334660fc733SEric Anholt struct bcm2835_host *host = param; 335660fc733SEric Anholt 336660fc733SEric Anholt schedule_work(&host->dma_work); 337660fc733SEric Anholt } 338660fc733SEric Anholt 339660fc733SEric Anholt static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 340660fc733SEric Anholt { 341660fc733SEric Anholt unsigned long flags; 342660fc733SEric Anholt size_t blksize; 343660fc733SEric Anholt unsigned long wait_max; 344660fc733SEric Anholt 345660fc733SEric Anholt blksize = host->data->blksz; 346660fc733SEric Anholt 347660fc733SEric Anholt wait_max = jiffies + msecs_to_jiffies(500); 348660fc733SEric Anholt 349660fc733SEric Anholt local_irq_save(flags); 350660fc733SEric Anholt 351660fc733SEric Anholt while (blksize) { 352660fc733SEric Anholt int copy_words; 353660fc733SEric Anholt u32 hsts = 0; 354660fc733SEric Anholt size_t len; 355660fc733SEric Anholt u32 *buf; 356660fc733SEric Anholt 357660fc733SEric Anholt if (!sg_miter_next(&host->sg_miter)) { 358660fc733SEric Anholt host->data->error = -EINVAL; 359660fc733SEric Anholt break; 360660fc733SEric Anholt } 361660fc733SEric Anholt 362660fc733SEric Anholt len = min(host->sg_miter.length, blksize); 363660fc733SEric Anholt if (len % 4) { 364660fc733SEric Anholt host->data->error = -EINVAL; 365660fc733SEric Anholt break; 366660fc733SEric Anholt } 367660fc733SEric Anholt 368660fc733SEric Anholt blksize -= len; 369660fc733SEric Anholt host->sg_miter.consumed = len; 370660fc733SEric Anholt 371660fc733SEric Anholt buf = (u32 *)host->sg_miter.addr; 372660fc733SEric Anholt 373660fc733SEric Anholt copy_words = len / 4; 374660fc733SEric Anholt 375660fc733SEric Anholt while (copy_words) { 376660fc733SEric Anholt int burst_words, words; 377660fc733SEric Anholt u32 edm; 378660fc733SEric Anholt 379660fc733SEric Anholt burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 380660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 381660fc733SEric Anholt if (is_read) 382660fc733SEric Anholt words = ((edm >> 4) & 0x1f); 383660fc733SEric Anholt else 384660fc733SEric Anholt words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f); 385660fc733SEric Anholt 386660fc733SEric Anholt if (words < burst_words) { 387660fc733SEric Anholt int fsm_state = (edm & SDEDM_FSM_MASK); 388660fc733SEric Anholt struct device *dev = &host->pdev->dev; 389660fc733SEric Anholt 390660fc733SEric Anholt if ((is_read && 391660fc733SEric Anholt (fsm_state != SDEDM_FSM_READDATA && 392660fc733SEric Anholt fsm_state != SDEDM_FSM_READWAIT && 393660fc733SEric Anholt fsm_state != SDEDM_FSM_READCRC)) || 394660fc733SEric Anholt (!is_read && 395660fc733SEric Anholt (fsm_state != SDEDM_FSM_WRITEDATA && 396660fc733SEric Anholt fsm_state != SDEDM_FSM_WRITESTART1 && 397660fc733SEric Anholt fsm_state != SDEDM_FSM_WRITESTART2))) { 398660fc733SEric Anholt hsts = readl(host->ioaddr + SDHSTS); 399660fc733SEric Anholt dev_err(dev, "fsm %x, hsts %08x\n", 400660fc733SEric Anholt fsm_state, hsts); 401660fc733SEric Anholt if (hsts & SDHSTS_ERROR_MASK) 402660fc733SEric Anholt break; 403660fc733SEric Anholt } 404660fc733SEric Anholt 405660fc733SEric Anholt if (time_after(jiffies, wait_max)) { 406660fc733SEric Anholt dev_err(dev, "PIO %s timeout - EDM %08x\n", 407660fc733SEric Anholt is_read ? "read" : "write", 408660fc733SEric Anholt edm); 409660fc733SEric Anholt hsts = SDHSTS_REW_TIME_OUT; 410660fc733SEric Anholt break; 411660fc733SEric Anholt } 412660fc733SEric Anholt ndelay((burst_words - words) * 413660fc733SEric Anholt host->ns_per_fifo_word); 414660fc733SEric Anholt continue; 415660fc733SEric Anholt } else if (words > copy_words) { 416660fc733SEric Anholt words = copy_words; 417660fc733SEric Anholt } 418660fc733SEric Anholt 419660fc733SEric Anholt copy_words -= words; 420660fc733SEric Anholt 421660fc733SEric Anholt while (words) { 422660fc733SEric Anholt if (is_read) 423660fc733SEric Anholt *(buf++) = readl(host->ioaddr + SDDATA); 424660fc733SEric Anholt else 425660fc733SEric Anholt writel(*(buf++), host->ioaddr + SDDATA); 426660fc733SEric Anholt words--; 427660fc733SEric Anholt } 428660fc733SEric Anholt } 429660fc733SEric Anholt 430660fc733SEric Anholt if (hsts & SDHSTS_ERROR_MASK) 431660fc733SEric Anholt break; 432660fc733SEric Anholt } 433660fc733SEric Anholt 434660fc733SEric Anholt sg_miter_stop(&host->sg_miter); 435660fc733SEric Anholt 436660fc733SEric Anholt local_irq_restore(flags); 437660fc733SEric Anholt } 438660fc733SEric Anholt 439660fc733SEric Anholt static void bcm2835_transfer_pio(struct bcm2835_host *host) 440660fc733SEric Anholt { 441660fc733SEric Anholt struct device *dev = &host->pdev->dev; 442660fc733SEric Anholt u32 sdhsts; 443660fc733SEric Anholt bool is_read; 444660fc733SEric Anholt 445660fc733SEric Anholt is_read = (host->data->flags & MMC_DATA_READ) != 0; 446660fc733SEric Anholt bcm2835_transfer_block_pio(host, is_read); 447660fc733SEric Anholt 448660fc733SEric Anholt sdhsts = readl(host->ioaddr + SDHSTS); 449660fc733SEric Anholt if (sdhsts & (SDHSTS_CRC16_ERROR | 450660fc733SEric Anholt SDHSTS_CRC7_ERROR | 451660fc733SEric Anholt SDHSTS_FIFO_ERROR)) { 452660fc733SEric Anholt dev_err(dev, "%s transfer error - HSTS %08x\n", 453660fc733SEric Anholt is_read ? "read" : "write", sdhsts); 454660fc733SEric Anholt host->data->error = -EILSEQ; 455660fc733SEric Anholt } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 456660fc733SEric Anholt SDHSTS_REW_TIME_OUT))) { 457660fc733SEric Anholt dev_err(dev, "%s timeout error - HSTS %08x\n", 458660fc733SEric Anholt is_read ? "read" : "write", sdhsts); 459660fc733SEric Anholt host->data->error = -ETIMEDOUT; 460660fc733SEric Anholt } 461660fc733SEric Anholt } 462660fc733SEric Anholt 463660fc733SEric Anholt static 464660fc733SEric Anholt void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data) 465660fc733SEric Anholt { 466660fc733SEric Anholt int len, dir_data, dir_slave; 467660fc733SEric Anholt struct dma_async_tx_descriptor *desc = NULL; 468660fc733SEric Anholt struct dma_chan *dma_chan; 469660fc733SEric Anholt 470660fc733SEric Anholt dma_chan = host->dma_chan_rxtx; 471660fc733SEric Anholt if (data->flags & MMC_DATA_READ) { 472660fc733SEric Anholt dir_data = DMA_FROM_DEVICE; 473660fc733SEric Anholt dir_slave = DMA_DEV_TO_MEM; 474660fc733SEric Anholt } else { 475660fc733SEric Anholt dir_data = DMA_TO_DEVICE; 476660fc733SEric Anholt dir_slave = DMA_MEM_TO_DEV; 477660fc733SEric Anholt } 478660fc733SEric Anholt 479660fc733SEric Anholt /* The block doesn't manage the FIFO DREQs properly for 480660fc733SEric Anholt * multi-block transfers, so don't attempt to DMA the final 481660fc733SEric Anholt * few words. Unfortunately this requires the final sg entry 482660fc733SEric Anholt * to be trimmed. N.B. This code demands that the overspill 483660fc733SEric Anholt * is contained in a single sg entry. 484660fc733SEric Anholt */ 485660fc733SEric Anholt 486660fc733SEric Anholt host->drain_words = 0; 487660fc733SEric Anholt if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) { 488660fc733SEric Anholt struct scatterlist *sg; 489660fc733SEric Anholt u32 len; 490660fc733SEric Anholt int i; 491660fc733SEric Anholt 492660fc733SEric Anholt len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4, 493660fc733SEric Anholt (u32)data->blocks * data->blksz); 494660fc733SEric Anholt 495660fc733SEric Anholt for_each_sg(data->sg, sg, data->sg_len, i) { 496660fc733SEric Anholt if (sg_is_last(sg)) { 497660fc733SEric Anholt WARN_ON(sg->length < len); 498660fc733SEric Anholt sg->length -= len; 499660fc733SEric Anholt host->drain_page = sg_page(sg); 500660fc733SEric Anholt host->drain_offset = sg->offset + sg->length; 501660fc733SEric Anholt } 502660fc733SEric Anholt } 503660fc733SEric Anholt host->drain_words = len / 4; 504660fc733SEric Anholt } 505660fc733SEric Anholt 506660fc733SEric Anholt /* The parameters have already been validated, so this will not fail */ 507660fc733SEric Anholt (void)dmaengine_slave_config(dma_chan, 508660fc733SEric Anholt (dir_data == DMA_FROM_DEVICE) ? 509660fc733SEric Anholt &host->dma_cfg_rx : 510660fc733SEric Anholt &host->dma_cfg_tx); 511660fc733SEric Anholt 512660fc733SEric Anholt len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len, 513660fc733SEric Anholt dir_data); 514660fc733SEric Anholt 515660fc733SEric Anholt if (len > 0) { 516660fc733SEric Anholt desc = dmaengine_prep_slave_sg(dma_chan, data->sg, 517660fc733SEric Anholt len, dir_slave, 518660fc733SEric Anholt DMA_PREP_INTERRUPT | 519660fc733SEric Anholt DMA_CTRL_ACK); 520660fc733SEric Anholt } 521660fc733SEric Anholt 522660fc733SEric Anholt if (desc) { 523660fc733SEric Anholt desc->callback = bcm2835_dma_complete; 524660fc733SEric Anholt desc->callback_param = host; 525660fc733SEric Anholt host->dma_desc = desc; 526660fc733SEric Anholt host->dma_chan = dma_chan; 527660fc733SEric Anholt host->dma_dir = dir_data; 528660fc733SEric Anholt } 529660fc733SEric Anholt } 530660fc733SEric Anholt 531660fc733SEric Anholt static void bcm2835_start_dma(struct bcm2835_host *host) 532660fc733SEric Anholt { 533660fc733SEric Anholt dmaengine_submit(host->dma_desc); 534660fc733SEric Anholt dma_async_issue_pending(host->dma_chan); 535660fc733SEric Anholt } 536660fc733SEric Anholt 537660fc733SEric Anholt static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 538660fc733SEric Anholt { 539660fc733SEric Anholt u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 540660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 541660fc733SEric Anholt 542660fc733SEric Anholt if (host->dma_desc) { 543660fc733SEric Anholt host->hcfg = (host->hcfg & ~all_irqs) | 544660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 545660fc733SEric Anholt } else { 546660fc733SEric Anholt host->hcfg = (host->hcfg & ~all_irqs) | 547660fc733SEric Anholt SDHCFG_DATA_IRPT_EN | 548660fc733SEric Anholt SDHCFG_BUSY_IRPT_EN; 549660fc733SEric Anholt } 550660fc733SEric Anholt 551660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 552660fc733SEric Anholt } 553660fc733SEric Anholt 554660fc733SEric Anholt static 555660fc733SEric Anholt void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) 556660fc733SEric Anholt { 557660fc733SEric Anholt struct mmc_data *data = cmd->data; 558660fc733SEric Anholt 559660fc733SEric Anholt WARN_ON(host->data); 560660fc733SEric Anholt 561660fc733SEric Anholt host->data = data; 562660fc733SEric Anholt if (!data) 563660fc733SEric Anholt return; 564660fc733SEric Anholt 565660fc733SEric Anholt host->data_complete = false; 566660fc733SEric Anholt host->data->bytes_xfered = 0; 567660fc733SEric Anholt 568660fc733SEric Anholt if (!host->dma_desc) { 569660fc733SEric Anholt /* Use PIO */ 570660fc733SEric Anholt int flags = SG_MITER_ATOMIC; 571660fc733SEric Anholt 572660fc733SEric Anholt if (data->flags & MMC_DATA_READ) 573660fc733SEric Anholt flags |= SG_MITER_TO_SG; 574660fc733SEric Anholt else 575660fc733SEric Anholt flags |= SG_MITER_FROM_SG; 576660fc733SEric Anholt sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 577660fc733SEric Anholt host->blocks = data->blocks; 578660fc733SEric Anholt } 579660fc733SEric Anholt 580660fc733SEric Anholt bcm2835_set_transfer_irqs(host); 581660fc733SEric Anholt 582660fc733SEric Anholt writel(data->blksz, host->ioaddr + SDHBCT); 583660fc733SEric Anholt writel(data->blocks, host->ioaddr + SDHBLC); 584660fc733SEric Anholt } 585660fc733SEric Anholt 586660fc733SEric Anholt static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms) 587660fc733SEric Anholt { 588660fc733SEric Anholt struct device *dev = &host->pdev->dev; 589660fc733SEric Anholt u32 value; 590660fc733SEric Anholt int ret; 591660fc733SEric Anholt 592660fc733SEric Anholt ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 593660fc733SEric Anholt !(value & SDCMD_NEW_FLAG), 1, 10); 594660fc733SEric Anholt if (ret == -ETIMEDOUT) 595660fc733SEric Anholt /* if it takes a while make poll interval bigger */ 596660fc733SEric Anholt ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 597660fc733SEric Anholt !(value & SDCMD_NEW_FLAG), 598660fc733SEric Anholt 10, max_ms * 1000); 599660fc733SEric Anholt if (ret == -ETIMEDOUT) 600660fc733SEric Anholt dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms); 601660fc733SEric Anholt 602660fc733SEric Anholt return value; 603660fc733SEric Anholt } 604660fc733SEric Anholt 605660fc733SEric Anholt static void bcm2835_finish_request(struct bcm2835_host *host) 606660fc733SEric Anholt { 607660fc733SEric Anholt struct dma_chan *terminate_chan = NULL; 608660fc733SEric Anholt struct mmc_request *mrq; 609660fc733SEric Anholt 610660fc733SEric Anholt cancel_delayed_work(&host->timeout_work); 611660fc733SEric Anholt 612660fc733SEric Anholt mrq = host->mrq; 613660fc733SEric Anholt 614660fc733SEric Anholt host->mrq = NULL; 615660fc733SEric Anholt host->cmd = NULL; 616660fc733SEric Anholt host->data = NULL; 617660fc733SEric Anholt 618660fc733SEric Anholt host->dma_desc = NULL; 619660fc733SEric Anholt terminate_chan = host->dma_chan; 620660fc733SEric Anholt host->dma_chan = NULL; 621660fc733SEric Anholt 622660fc733SEric Anholt if (terminate_chan) { 623660fc733SEric Anholt int err = dmaengine_terminate_all(terminate_chan); 624660fc733SEric Anholt 625660fc733SEric Anholt if (err) 626660fc733SEric Anholt dev_err(&host->pdev->dev, 627660fc733SEric Anholt "failed to terminate DMA (%d)\n", err); 628660fc733SEric Anholt } 629660fc733SEric Anholt 630660fc733SEric Anholt mmc_request_done(host->mmc, mrq); 631660fc733SEric Anholt } 632660fc733SEric Anholt 633660fc733SEric Anholt static 634660fc733SEric Anholt bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd) 635660fc733SEric Anholt { 636660fc733SEric Anholt struct device *dev = &host->pdev->dev; 637660fc733SEric Anholt u32 sdcmd, sdhsts; 638660fc733SEric Anholt unsigned long timeout; 639660fc733SEric Anholt 640660fc733SEric Anholt WARN_ON(host->cmd); 641660fc733SEric Anholt 642660fc733SEric Anholt sdcmd = bcm2835_read_wait_sdcmd(host, 100); 643660fc733SEric Anholt if (sdcmd & SDCMD_NEW_FLAG) { 644660fc733SEric Anholt dev_err(dev, "previous command never completed.\n"); 645660fc733SEric Anholt bcm2835_dumpregs(host); 646660fc733SEric Anholt cmd->error = -EILSEQ; 647660fc733SEric Anholt bcm2835_finish_request(host); 648660fc733SEric Anholt return false; 649660fc733SEric Anholt } 650660fc733SEric Anholt 651660fc733SEric Anholt if (!cmd->data && cmd->busy_timeout > 9000) 652660fc733SEric Anholt timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 653660fc733SEric Anholt else 654660fc733SEric Anholt timeout = 10 * HZ; 655660fc733SEric Anholt schedule_delayed_work(&host->timeout_work, timeout); 656660fc733SEric Anholt 657660fc733SEric Anholt host->cmd = cmd; 658660fc733SEric Anholt 659660fc733SEric Anholt /* Clear any error flags */ 660660fc733SEric Anholt sdhsts = readl(host->ioaddr + SDHSTS); 661660fc733SEric Anholt if (sdhsts & SDHSTS_ERROR_MASK) 662660fc733SEric Anholt writel(sdhsts, host->ioaddr + SDHSTS); 663660fc733SEric Anholt 664660fc733SEric Anholt if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 665660fc733SEric Anholt dev_err(dev, "unsupported response type!\n"); 666660fc733SEric Anholt cmd->error = -EINVAL; 667660fc733SEric Anholt bcm2835_finish_request(host); 668660fc733SEric Anholt return false; 669660fc733SEric Anholt } 670660fc733SEric Anholt 671660fc733SEric Anholt bcm2835_prepare_data(host, cmd); 672660fc733SEric Anholt 673660fc733SEric Anholt writel(cmd->arg, host->ioaddr + SDARG); 674660fc733SEric Anholt 675660fc733SEric Anholt sdcmd = cmd->opcode & SDCMD_CMD_MASK; 676660fc733SEric Anholt 677660fc733SEric Anholt host->use_busy = false; 678660fc733SEric Anholt if (!(cmd->flags & MMC_RSP_PRESENT)) { 679660fc733SEric Anholt sdcmd |= SDCMD_NO_RESPONSE; 680660fc733SEric Anholt } else { 681660fc733SEric Anholt if (cmd->flags & MMC_RSP_136) 682660fc733SEric Anholt sdcmd |= SDCMD_LONG_RESPONSE; 683660fc733SEric Anholt if (cmd->flags & MMC_RSP_BUSY) { 684660fc733SEric Anholt sdcmd |= SDCMD_BUSYWAIT; 685660fc733SEric Anholt host->use_busy = true; 686660fc733SEric Anholt } 687660fc733SEric Anholt } 688660fc733SEric Anholt 689660fc733SEric Anholt if (cmd->data) { 690660fc733SEric Anholt if (cmd->data->flags & MMC_DATA_WRITE) 691660fc733SEric Anholt sdcmd |= SDCMD_WRITE_CMD; 692660fc733SEric Anholt if (cmd->data->flags & MMC_DATA_READ) 693660fc733SEric Anholt sdcmd |= SDCMD_READ_CMD; 694660fc733SEric Anholt } 695660fc733SEric Anholt 696660fc733SEric Anholt writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 697660fc733SEric Anholt 698660fc733SEric Anholt return true; 699660fc733SEric Anholt } 700660fc733SEric Anholt 701660fc733SEric Anholt static void bcm2835_transfer_complete(struct bcm2835_host *host) 702660fc733SEric Anholt { 703660fc733SEric Anholt struct mmc_data *data; 704660fc733SEric Anholt 705660fc733SEric Anholt WARN_ON(!host->data_complete); 706660fc733SEric Anholt 707660fc733SEric Anholt data = host->data; 708660fc733SEric Anholt host->data = NULL; 709660fc733SEric Anholt 710660fc733SEric Anholt /* Need to send CMD12 if - 711660fc733SEric Anholt * a) open-ended multiblock transfer (no CMD23) 712660fc733SEric Anholt * b) error in multiblock transfer 713660fc733SEric Anholt */ 714660fc733SEric Anholt if (host->mrq->stop && (data->error || !host->use_sbc)) { 715660fc733SEric Anholt if (bcm2835_send_command(host, host->mrq->stop)) { 716660fc733SEric Anholt /* No busy, so poll for completion */ 717660fc733SEric Anholt if (!host->use_busy) 718660fc733SEric Anholt bcm2835_finish_command(host); 719660fc733SEric Anholt } 720660fc733SEric Anholt } else { 721660fc733SEric Anholt bcm2835_wait_transfer_complete(host); 722660fc733SEric Anholt bcm2835_finish_request(host); 723660fc733SEric Anholt } 724660fc733SEric Anholt } 725660fc733SEric Anholt 726660fc733SEric Anholt static void bcm2835_finish_data(struct bcm2835_host *host) 727660fc733SEric Anholt { 728660fc733SEric Anholt struct device *dev = &host->pdev->dev; 729660fc733SEric Anholt struct mmc_data *data; 730660fc733SEric Anholt 731660fc733SEric Anholt data = host->data; 732660fc733SEric Anholt 733660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 734660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 735660fc733SEric Anholt 736660fc733SEric Anholt data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks); 737660fc733SEric Anholt 738660fc733SEric Anholt host->data_complete = true; 739660fc733SEric Anholt 740660fc733SEric Anholt if (host->cmd) { 741660fc733SEric Anholt /* Data managed to finish before the 742660fc733SEric Anholt * command completed. Make sure we do 743660fc733SEric Anholt * things in the proper order. 744660fc733SEric Anholt */ 745660fc733SEric Anholt dev_dbg(dev, "Finished early - HSTS %08x\n", 746660fc733SEric Anholt readl(host->ioaddr + SDHSTS)); 747660fc733SEric Anholt } else { 748660fc733SEric Anholt bcm2835_transfer_complete(host); 749660fc733SEric Anholt } 750660fc733SEric Anholt } 751660fc733SEric Anholt 752660fc733SEric Anholt static void bcm2835_finish_command(struct bcm2835_host *host) 753660fc733SEric Anholt { 754660fc733SEric Anholt struct device *dev = &host->pdev->dev; 755660fc733SEric Anholt struct mmc_command *cmd = host->cmd; 756660fc733SEric Anholt u32 sdcmd; 757660fc733SEric Anholt 758660fc733SEric Anholt sdcmd = bcm2835_read_wait_sdcmd(host, 100); 759660fc733SEric Anholt 760660fc733SEric Anholt /* Check for errors */ 761660fc733SEric Anholt if (sdcmd & SDCMD_NEW_FLAG) { 762660fc733SEric Anholt dev_err(dev, "command never completed.\n"); 763660fc733SEric Anholt bcm2835_dumpregs(host); 764660fc733SEric Anholt host->cmd->error = -EIO; 765660fc733SEric Anholt bcm2835_finish_request(host); 766660fc733SEric Anholt return; 767660fc733SEric Anholt } else if (sdcmd & SDCMD_FAIL_FLAG) { 768660fc733SEric Anholt u32 sdhsts = readl(host->ioaddr + SDHSTS); 769660fc733SEric Anholt 770660fc733SEric Anholt /* Clear the errors */ 771660fc733SEric Anholt writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 772660fc733SEric Anholt 773660fc733SEric Anholt if (!(sdhsts & SDHSTS_CRC7_ERROR) || 774660fc733SEric Anholt (host->cmd->opcode != MMC_SEND_OP_COND)) { 775660fc733SEric Anholt if (sdhsts & SDHSTS_CMD_TIME_OUT) { 776660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 777660fc733SEric Anholt } else { 778660fc733SEric Anholt dev_err(dev, "unexpected command %d error\n", 779660fc733SEric Anholt host->cmd->opcode); 780660fc733SEric Anholt bcm2835_dumpregs(host); 781660fc733SEric Anholt host->cmd->error = -EILSEQ; 782660fc733SEric Anholt } 783660fc733SEric Anholt bcm2835_finish_request(host); 784660fc733SEric Anholt return; 785660fc733SEric Anholt } 786660fc733SEric Anholt } 787660fc733SEric Anholt 788660fc733SEric Anholt if (cmd->flags & MMC_RSP_PRESENT) { 789660fc733SEric Anholt if (cmd->flags & MMC_RSP_136) { 790660fc733SEric Anholt int i; 791660fc733SEric Anholt 792660fc733SEric Anholt for (i = 0; i < 4; i++) { 793660fc733SEric Anholt cmd->resp[3 - i] = 794660fc733SEric Anholt readl(host->ioaddr + SDRSP0 + i * 4); 795660fc733SEric Anholt } 796660fc733SEric Anholt } else { 797660fc733SEric Anholt cmd->resp[0] = readl(host->ioaddr + SDRSP0); 798660fc733SEric Anholt } 799660fc733SEric Anholt } 800660fc733SEric Anholt 801660fc733SEric Anholt if (cmd == host->mrq->sbc) { 802660fc733SEric Anholt /* Finished CMD23, now send actual command. */ 803660fc733SEric Anholt host->cmd = NULL; 804660fc733SEric Anholt if (bcm2835_send_command(host, host->mrq->cmd)) { 805660fc733SEric Anholt if (host->data && host->dma_desc) 806660fc733SEric Anholt /* DMA transfer starts now, PIO starts 807660fc733SEric Anholt * after irq 808660fc733SEric Anholt */ 809660fc733SEric Anholt bcm2835_start_dma(host); 810660fc733SEric Anholt 811660fc733SEric Anholt if (!host->use_busy) 812660fc733SEric Anholt bcm2835_finish_command(host); 813660fc733SEric Anholt } 814660fc733SEric Anholt } else if (cmd == host->mrq->stop) { 815660fc733SEric Anholt /* Finished CMD12 */ 816660fc733SEric Anholt bcm2835_finish_request(host); 817660fc733SEric Anholt } else { 818660fc733SEric Anholt /* Processed actual command. */ 819660fc733SEric Anholt host->cmd = NULL; 820660fc733SEric Anholt if (!host->data) 821660fc733SEric Anholt bcm2835_finish_request(host); 822660fc733SEric Anholt else if (host->data_complete) 823660fc733SEric Anholt bcm2835_transfer_complete(host); 824660fc733SEric Anholt } 825660fc733SEric Anholt } 826660fc733SEric Anholt 827660fc733SEric Anholt static void bcm2835_timeout(struct work_struct *work) 828660fc733SEric Anholt { 829660fc733SEric Anholt struct delayed_work *d = to_delayed_work(work); 830660fc733SEric Anholt struct bcm2835_host *host = 831660fc733SEric Anholt container_of(d, struct bcm2835_host, timeout_work); 832660fc733SEric Anholt struct device *dev = &host->pdev->dev; 833660fc733SEric Anholt 834660fc733SEric Anholt mutex_lock(&host->mutex); 835660fc733SEric Anholt 836660fc733SEric Anholt if (host->mrq) { 837660fc733SEric Anholt dev_err(dev, "timeout waiting for hardware interrupt.\n"); 838660fc733SEric Anholt bcm2835_dumpregs(host); 839660fc733SEric Anholt 840660fc733SEric Anholt if (host->data) { 841660fc733SEric Anholt host->data->error = -ETIMEDOUT; 842660fc733SEric Anholt bcm2835_finish_data(host); 843660fc733SEric Anholt } else { 844660fc733SEric Anholt if (host->cmd) 845660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 846660fc733SEric Anholt else 847660fc733SEric Anholt host->mrq->cmd->error = -ETIMEDOUT; 848660fc733SEric Anholt 849660fc733SEric Anholt bcm2835_finish_request(host); 850660fc733SEric Anholt } 851660fc733SEric Anholt } 852660fc733SEric Anholt 853660fc733SEric Anholt mutex_unlock(&host->mutex); 854660fc733SEric Anholt } 855660fc733SEric Anholt 856660fc733SEric Anholt static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 857660fc733SEric Anholt { 858660fc733SEric Anholt struct device *dev = &host->pdev->dev; 859660fc733SEric Anholt 860660fc733SEric Anholt if (!(intmask & SDHSTS_ERROR_MASK)) 861660fc733SEric Anholt return false; 862660fc733SEric Anholt 863660fc733SEric Anholt if (!host->cmd) 864660fc733SEric Anholt return true; 865660fc733SEric Anholt 866660fc733SEric Anholt dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask); 867660fc733SEric Anholt if (intmask & SDHSTS_CRC7_ERROR) { 868660fc733SEric Anholt host->cmd->error = -EILSEQ; 869660fc733SEric Anholt } else if (intmask & (SDHSTS_CRC16_ERROR | 870660fc733SEric Anholt SDHSTS_FIFO_ERROR)) { 871660fc733SEric Anholt if (host->mrq->data) 872660fc733SEric Anholt host->mrq->data->error = -EILSEQ; 873660fc733SEric Anholt else 874660fc733SEric Anholt host->cmd->error = -EILSEQ; 875660fc733SEric Anholt } else if (intmask & SDHSTS_REW_TIME_OUT) { 876660fc733SEric Anholt if (host->mrq->data) 877660fc733SEric Anholt host->mrq->data->error = -ETIMEDOUT; 878660fc733SEric Anholt else 879660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 880660fc733SEric Anholt } else if (intmask & SDHSTS_CMD_TIME_OUT) { 881660fc733SEric Anholt host->cmd->error = -ETIMEDOUT; 882660fc733SEric Anholt } 883660fc733SEric Anholt bcm2835_dumpregs(host); 884660fc733SEric Anholt return true; 885660fc733SEric Anholt } 886660fc733SEric Anholt 887660fc733SEric Anholt static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 888660fc733SEric Anholt { 889660fc733SEric Anholt if (!host->data) 890660fc733SEric Anholt return; 891660fc733SEric Anholt if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 892660fc733SEric Anholt host->data->error = -EILSEQ; 893660fc733SEric Anholt if (intmask & SDHSTS_REW_TIME_OUT) 894660fc733SEric Anholt host->data->error = -ETIMEDOUT; 895660fc733SEric Anholt } 896660fc733SEric Anholt 897660fc733SEric Anholt static void bcm2835_busy_irq(struct bcm2835_host *host) 898660fc733SEric Anholt { 899660fc733SEric Anholt if (WARN_ON(!host->cmd)) { 900660fc733SEric Anholt bcm2835_dumpregs(host); 901660fc733SEric Anholt return; 902660fc733SEric Anholt } 903660fc733SEric Anholt 904660fc733SEric Anholt if (WARN_ON(!host->use_busy)) { 905660fc733SEric Anholt bcm2835_dumpregs(host); 906660fc733SEric Anholt return; 907660fc733SEric Anholt } 908660fc733SEric Anholt host->use_busy = false; 909660fc733SEric Anholt 910660fc733SEric Anholt bcm2835_finish_command(host); 911660fc733SEric Anholt } 912660fc733SEric Anholt 913660fc733SEric Anholt static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 914660fc733SEric Anholt { 915660fc733SEric Anholt /* There are no dedicated data/space available interrupt 916660fc733SEric Anholt * status bits, so it is necessary to use the single shared 917660fc733SEric Anholt * data/space available FIFO status bits. It is therefore not 918660fc733SEric Anholt * an error to get here when there is no data transfer in 919660fc733SEric Anholt * progress. 920660fc733SEric Anholt */ 921660fc733SEric Anholt if (!host->data) 922660fc733SEric Anholt return; 923660fc733SEric Anholt 924660fc733SEric Anholt bcm2835_check_data_error(host, intmask); 925660fc733SEric Anholt if (host->data->error) 926660fc733SEric Anholt goto finished; 927660fc733SEric Anholt 928660fc733SEric Anholt if (host->data->flags & MMC_DATA_WRITE) { 929660fc733SEric Anholt /* Use the block interrupt for writes after the first block */ 930660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 931660fc733SEric Anholt host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 932660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 933660fc733SEric Anholt bcm2835_transfer_pio(host); 934660fc733SEric Anholt } else { 935660fc733SEric Anholt bcm2835_transfer_pio(host); 936660fc733SEric Anholt host->blocks--; 937660fc733SEric Anholt if ((host->blocks == 0) || host->data->error) 938660fc733SEric Anholt goto finished; 939660fc733SEric Anholt } 940660fc733SEric Anholt return; 941660fc733SEric Anholt 942660fc733SEric Anholt finished: 943660fc733SEric Anholt host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 944660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 945660fc733SEric Anholt } 946660fc733SEric Anholt 947660fc733SEric Anholt static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 948660fc733SEric Anholt { 949660fc733SEric Anholt if (!host->data) 950660fc733SEric Anholt return; 951660fc733SEric Anholt if ((host->blocks == 0) || host->data->error) 952660fc733SEric Anholt bcm2835_finish_data(host); 953660fc733SEric Anholt } 954660fc733SEric Anholt 955660fc733SEric Anholt static void bcm2835_block_irq(struct bcm2835_host *host) 956660fc733SEric Anholt { 957660fc733SEric Anholt if (WARN_ON(!host->data)) { 958660fc733SEric Anholt bcm2835_dumpregs(host); 959660fc733SEric Anholt return; 960660fc733SEric Anholt } 961660fc733SEric Anholt 962660fc733SEric Anholt if (!host->dma_desc) { 963660fc733SEric Anholt WARN_ON(!host->blocks); 964660fc733SEric Anholt if (host->data->error || (--host->blocks == 0)) 965660fc733SEric Anholt bcm2835_finish_data(host); 966660fc733SEric Anholt else 967660fc733SEric Anholt bcm2835_transfer_pio(host); 968660fc733SEric Anholt } else if (host->data->flags & MMC_DATA_WRITE) { 969660fc733SEric Anholt bcm2835_finish_data(host); 970660fc733SEric Anholt } 971660fc733SEric Anholt } 972660fc733SEric Anholt 973660fc733SEric Anholt static irqreturn_t bcm2835_irq(int irq, void *dev_id) 974660fc733SEric Anholt { 975660fc733SEric Anholt irqreturn_t result = IRQ_NONE; 976660fc733SEric Anholt struct bcm2835_host *host = dev_id; 977660fc733SEric Anholt u32 intmask; 978660fc733SEric Anholt 979660fc733SEric Anholt spin_lock(&host->lock); 980660fc733SEric Anholt 981660fc733SEric Anholt intmask = readl(host->ioaddr + SDHSTS); 982660fc733SEric Anholt 983660fc733SEric Anholt writel(SDHSTS_BUSY_IRPT | 984660fc733SEric Anholt SDHSTS_BLOCK_IRPT | 985660fc733SEric Anholt SDHSTS_SDIO_IRPT | 986660fc733SEric Anholt SDHSTS_DATA_FLAG, 987660fc733SEric Anholt host->ioaddr + SDHSTS); 988660fc733SEric Anholt 989660fc733SEric Anholt if (intmask & SDHSTS_BLOCK_IRPT) { 990660fc733SEric Anholt bcm2835_check_data_error(host, intmask); 991660fc733SEric Anholt host->irq_block = true; 992660fc733SEric Anholt result = IRQ_WAKE_THREAD; 993660fc733SEric Anholt } 994660fc733SEric Anholt 995660fc733SEric Anholt if (intmask & SDHSTS_BUSY_IRPT) { 996660fc733SEric Anholt if (!bcm2835_check_cmd_error(host, intmask)) { 997660fc733SEric Anholt host->irq_busy = true; 998660fc733SEric Anholt result = IRQ_WAKE_THREAD; 999660fc733SEric Anholt } else { 1000660fc733SEric Anholt result = IRQ_HANDLED; 1001660fc733SEric Anholt } 1002660fc733SEric Anholt } 1003660fc733SEric Anholt 1004660fc733SEric Anholt /* There is no true data interrupt status bit, so it is 1005660fc733SEric Anholt * necessary to qualify the data flag with the interrupt 1006660fc733SEric Anholt * enable bit. 1007660fc733SEric Anholt */ 1008660fc733SEric Anholt if ((intmask & SDHSTS_DATA_FLAG) && 1009660fc733SEric Anholt (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 1010660fc733SEric Anholt bcm2835_data_irq(host, intmask); 1011660fc733SEric Anholt host->irq_data = true; 1012660fc733SEric Anholt result = IRQ_WAKE_THREAD; 1013660fc733SEric Anholt } 1014660fc733SEric Anholt 1015660fc733SEric Anholt spin_unlock(&host->lock); 1016660fc733SEric Anholt 1017660fc733SEric Anholt return result; 1018660fc733SEric Anholt } 1019660fc733SEric Anholt 1020660fc733SEric Anholt static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 1021660fc733SEric Anholt { 1022660fc733SEric Anholt struct bcm2835_host *host = dev_id; 1023660fc733SEric Anholt unsigned long flags; 1024660fc733SEric Anholt bool block, busy, data; 1025660fc733SEric Anholt 1026660fc733SEric Anholt spin_lock_irqsave(&host->lock, flags); 1027660fc733SEric Anholt 1028660fc733SEric Anholt block = host->irq_block; 1029660fc733SEric Anholt busy = host->irq_busy; 1030660fc733SEric Anholt data = host->irq_data; 1031660fc733SEric Anholt host->irq_block = false; 1032660fc733SEric Anholt host->irq_busy = false; 1033660fc733SEric Anholt host->irq_data = false; 1034660fc733SEric Anholt 1035660fc733SEric Anholt spin_unlock_irqrestore(&host->lock, flags); 1036660fc733SEric Anholt 1037660fc733SEric Anholt mutex_lock(&host->mutex); 1038660fc733SEric Anholt 1039660fc733SEric Anholt if (block) 1040660fc733SEric Anholt bcm2835_block_irq(host); 1041660fc733SEric Anholt if (busy) 1042660fc733SEric Anholt bcm2835_busy_irq(host); 1043660fc733SEric Anholt if (data) 1044660fc733SEric Anholt bcm2835_data_threaded_irq(host); 1045660fc733SEric Anholt 1046660fc733SEric Anholt mutex_unlock(&host->mutex); 1047660fc733SEric Anholt 1048660fc733SEric Anholt return IRQ_HANDLED; 1049660fc733SEric Anholt } 1050660fc733SEric Anholt 1051660fc733SEric Anholt static void bcm2835_dma_complete_work(struct work_struct *work) 1052660fc733SEric Anholt { 1053660fc733SEric Anholt struct bcm2835_host *host = 1054660fc733SEric Anholt container_of(work, struct bcm2835_host, dma_work); 1055660fc733SEric Anholt struct mmc_data *data = host->data; 1056660fc733SEric Anholt 1057660fc733SEric Anholt mutex_lock(&host->mutex); 1058660fc733SEric Anholt 1059660fc733SEric Anholt if (host->dma_chan) { 1060660fc733SEric Anholt dma_unmap_sg(host->dma_chan->device->dev, 1061660fc733SEric Anholt data->sg, data->sg_len, 1062660fc733SEric Anholt host->dma_dir); 1063660fc733SEric Anholt 1064660fc733SEric Anholt host->dma_chan = NULL; 1065660fc733SEric Anholt } 1066660fc733SEric Anholt 1067660fc733SEric Anholt if (host->drain_words) { 1068660fc733SEric Anholt unsigned long flags; 1069660fc733SEric Anholt void *page; 1070660fc733SEric Anholt u32 *buf; 1071660fc733SEric Anholt 1072660fc733SEric Anholt if (host->drain_offset & PAGE_MASK) { 1073660fc733SEric Anholt host->drain_page += host->drain_offset >> PAGE_SHIFT; 1074660fc733SEric Anholt host->drain_offset &= ~PAGE_MASK; 1075660fc733SEric Anholt } 1076660fc733SEric Anholt local_irq_save(flags); 1077660fc733SEric Anholt page = kmap_atomic(host->drain_page); 1078660fc733SEric Anholt buf = page + host->drain_offset; 1079660fc733SEric Anholt 1080660fc733SEric Anholt while (host->drain_words) { 1081660fc733SEric Anholt u32 edm = readl(host->ioaddr + SDEDM); 1082660fc733SEric Anholt 1083660fc733SEric Anholt if ((edm >> 4) & 0x1f) 1084660fc733SEric Anholt *(buf++) = readl(host->ioaddr + SDDATA); 1085660fc733SEric Anholt host->drain_words--; 1086660fc733SEric Anholt } 1087660fc733SEric Anholt 1088660fc733SEric Anholt kunmap_atomic(page); 1089660fc733SEric Anholt local_irq_restore(flags); 1090660fc733SEric Anholt } 1091660fc733SEric Anholt 1092660fc733SEric Anholt bcm2835_finish_data(host); 1093660fc733SEric Anholt 1094660fc733SEric Anholt mutex_unlock(&host->mutex); 1095660fc733SEric Anholt } 1096660fc733SEric Anholt 1097660fc733SEric Anholt static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 1098660fc733SEric Anholt { 1099660fc733SEric Anholt int div; 1100660fc733SEric Anholt 1101660fc733SEric Anholt /* The SDCDIV register has 11 bits, and holds (div - 2). But 1102660fc733SEric Anholt * in data mode the max is 50MHz wihout a minimum, and only 1103660fc733SEric Anholt * the bottom 3 bits are used. Since the switch over is 1104660fc733SEric Anholt * automatic (unless we have marked the card as slow...), 1105660fc733SEric Anholt * chosen values have to make sense in both modes. Ident mode 1106660fc733SEric Anholt * must be 100-400KHz, so can range check the requested 1107660fc733SEric Anholt * clock. CMD15 must be used to return to data mode, so this 1108660fc733SEric Anholt * can be monitored. 1109660fc733SEric Anholt * 1110660fc733SEric Anholt * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 1111660fc733SEric Anholt * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 1112660fc733SEric Anholt * 1113660fc733SEric Anholt * 623->400KHz/27.8MHz 1114660fc733SEric Anholt * reset value (507)->491159/50MHz 1115660fc733SEric Anholt * 1116660fc733SEric Anholt * BUT, the 3-bit clock divisor in data mode is too small if 1117660fc733SEric Anholt * the core clock is higher than 250MHz, so instead use the 1118660fc733SEric Anholt * SLOW_CARD configuration bit to force the use of the ident 1119660fc733SEric Anholt * clock divisor at all times. 1120660fc733SEric Anholt */ 1121660fc733SEric Anholt 1122660fc733SEric Anholt if (clock < 100000) { 1123660fc733SEric Anholt /* Can't stop the clock, but make it as slow as possible 1124660fc733SEric Anholt * to show willing 1125660fc733SEric Anholt */ 1126660fc733SEric Anholt host->cdiv = SDCDIV_MAX_CDIV; 1127660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 1128660fc733SEric Anholt return; 1129660fc733SEric Anholt } 1130660fc733SEric Anholt 1131660fc733SEric Anholt div = host->max_clk / clock; 1132660fc733SEric Anholt if (div < 2) 1133660fc733SEric Anholt div = 2; 1134660fc733SEric Anholt if ((host->max_clk / div) > clock) 1135660fc733SEric Anholt div++; 1136660fc733SEric Anholt div -= 2; 1137660fc733SEric Anholt 1138660fc733SEric Anholt if (div > SDCDIV_MAX_CDIV) 1139660fc733SEric Anholt div = SDCDIV_MAX_CDIV; 1140660fc733SEric Anholt 1141660fc733SEric Anholt clock = host->max_clk / (div + 2); 1142660fc733SEric Anholt host->mmc->actual_clock = clock; 1143660fc733SEric Anholt 1144660fc733SEric Anholt /* Calibrate some delays */ 1145660fc733SEric Anholt 1146660fc733SEric Anholt host->ns_per_fifo_word = (1000000000 / clock) * 1147660fc733SEric Anholt ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32); 1148660fc733SEric Anholt 1149660fc733SEric Anholt host->cdiv = div; 1150660fc733SEric Anholt writel(host->cdiv, host->ioaddr + SDCDIV); 1151660fc733SEric Anholt 1152660fc733SEric Anholt /* Set the timeout to 500ms */ 1153660fc733SEric Anholt writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT); 1154660fc733SEric Anholt } 1155660fc733SEric Anholt 1156660fc733SEric Anholt static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq) 1157660fc733SEric Anholt { 1158660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 1159660fc733SEric Anholt struct device *dev = &host->pdev->dev; 1160660fc733SEric Anholt u32 edm, fsm; 1161660fc733SEric Anholt 1162660fc733SEric Anholt /* Reset the error statuses in case this is a retry */ 1163660fc733SEric Anholt if (mrq->sbc) 1164660fc733SEric Anholt mrq->sbc->error = 0; 1165660fc733SEric Anholt if (mrq->cmd) 1166660fc733SEric Anholt mrq->cmd->error = 0; 1167660fc733SEric Anholt if (mrq->data) 1168660fc733SEric Anholt mrq->data->error = 0; 1169660fc733SEric Anholt if (mrq->stop) 1170660fc733SEric Anholt mrq->stop->error = 0; 1171660fc733SEric Anholt 1172660fc733SEric Anholt if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1173660fc733SEric Anholt dev_err(dev, "unsupported block size (%d bytes)\n", 1174660fc733SEric Anholt mrq->data->blksz); 1175660fc733SEric Anholt mrq->cmd->error = -EINVAL; 1176660fc733SEric Anholt mmc_request_done(mmc, mrq); 1177660fc733SEric Anholt return; 1178660fc733SEric Anholt } 1179660fc733SEric Anholt 1180660fc733SEric Anholt if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD)) 1181660fc733SEric Anholt bcm2835_prepare_dma(host, mrq->data); 1182660fc733SEric Anholt 1183660fc733SEric Anholt mutex_lock(&host->mutex); 1184660fc733SEric Anholt 1185660fc733SEric Anholt WARN_ON(host->mrq); 1186660fc733SEric Anholt host->mrq = mrq; 1187660fc733SEric Anholt 1188660fc733SEric Anholt edm = readl(host->ioaddr + SDEDM); 1189660fc733SEric Anholt fsm = edm & SDEDM_FSM_MASK; 1190660fc733SEric Anholt 1191660fc733SEric Anholt if ((fsm != SDEDM_FSM_IDENTMODE) && 1192660fc733SEric Anholt (fsm != SDEDM_FSM_DATAMODE)) { 1193660fc733SEric Anholt dev_err(dev, "previous command (%d) not complete (EDM %08x)\n", 1194660fc733SEric Anholt readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, 1195660fc733SEric Anholt edm); 1196660fc733SEric Anholt bcm2835_dumpregs(host); 1197660fc733SEric Anholt mrq->cmd->error = -EILSEQ; 1198660fc733SEric Anholt bcm2835_finish_request(host); 1199660fc733SEric Anholt mutex_unlock(&host->mutex); 1200660fc733SEric Anholt return; 1201660fc733SEric Anholt } 1202660fc733SEric Anholt 1203660fc733SEric Anholt host->use_sbc = !!mrq->sbc && (host->mrq->data->flags & MMC_DATA_READ); 1204660fc733SEric Anholt if (host->use_sbc) { 1205660fc733SEric Anholt if (bcm2835_send_command(host, mrq->sbc)) { 1206660fc733SEric Anholt if (!host->use_busy) 1207660fc733SEric Anholt bcm2835_finish_command(host); 1208660fc733SEric Anholt } 1209660fc733SEric Anholt } else if (bcm2835_send_command(host, mrq->cmd)) { 1210660fc733SEric Anholt if (host->data && host->dma_desc) { 1211660fc733SEric Anholt /* DMA transfer starts now, PIO starts after irq */ 1212660fc733SEric Anholt bcm2835_start_dma(host); 1213660fc733SEric Anholt } 1214660fc733SEric Anholt 1215660fc733SEric Anholt if (!host->use_busy) 1216660fc733SEric Anholt bcm2835_finish_command(host); 1217660fc733SEric Anholt } 1218660fc733SEric Anholt 1219660fc733SEric Anholt mutex_unlock(&host->mutex); 1220660fc733SEric Anholt } 1221660fc733SEric Anholt 1222660fc733SEric Anholt static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1223660fc733SEric Anholt { 1224660fc733SEric Anholt struct bcm2835_host *host = mmc_priv(mmc); 1225660fc733SEric Anholt 1226660fc733SEric Anholt mutex_lock(&host->mutex); 1227660fc733SEric Anholt 1228660fc733SEric Anholt if (!ios->clock || ios->clock != host->clock) { 1229660fc733SEric Anholt bcm2835_set_clock(host, ios->clock); 1230660fc733SEric Anholt host->clock = ios->clock; 1231660fc733SEric Anholt } 1232660fc733SEric Anholt 1233660fc733SEric Anholt /* set bus width */ 1234660fc733SEric Anholt host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 1235660fc733SEric Anholt if (ios->bus_width == MMC_BUS_WIDTH_4) 1236660fc733SEric Anholt host->hcfg |= SDHCFG_WIDE_EXT_BUS; 1237660fc733SEric Anholt 1238660fc733SEric Anholt host->hcfg |= SDHCFG_WIDE_INT_BUS; 1239660fc733SEric Anholt 1240660fc733SEric Anholt /* Disable clever clock switching, to cope with fast core clocks */ 1241660fc733SEric Anholt host->hcfg |= SDHCFG_SLOW_CARD; 1242660fc733SEric Anholt 1243660fc733SEric Anholt writel(host->hcfg, host->ioaddr + SDHCFG); 1244660fc733SEric Anholt 1245660fc733SEric Anholt mutex_unlock(&host->mutex); 1246660fc733SEric Anholt } 1247660fc733SEric Anholt 1248660fc733SEric Anholt static struct mmc_host_ops bcm2835_ops = { 1249660fc733SEric Anholt .request = bcm2835_request, 1250660fc733SEric Anholt .set_ios = bcm2835_set_ios, 1251660fc733SEric Anholt .hw_reset = bcm2835_reset, 1252660fc733SEric Anholt }; 1253660fc733SEric Anholt 1254660fc733SEric Anholt static int bcm2835_add_host(struct bcm2835_host *host) 1255660fc733SEric Anholt { 1256660fc733SEric Anholt struct mmc_host *mmc = host->mmc; 1257660fc733SEric Anholt struct device *dev = &host->pdev->dev; 1258660fc733SEric Anholt char pio_limit_string[20]; 1259660fc733SEric Anholt int ret; 1260660fc733SEric Anholt 1261660fc733SEric Anholt mmc->f_max = host->max_clk; 1262660fc733SEric Anholt mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; 1263660fc733SEric Anholt 1264660fc733SEric Anholt mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000); 1265660fc733SEric Anholt 1266660fc733SEric Anholt dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n", 1267660fc733SEric Anholt mmc->f_max, mmc->f_min, mmc->max_busy_timeout); 1268660fc733SEric Anholt 1269660fc733SEric Anholt /* host controller capabilities */ 1270660fc733SEric Anholt mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 1271660fc733SEric Anholt MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | 1272660fc733SEric Anholt MMC_CAP_CMD23; 1273660fc733SEric Anholt 1274660fc733SEric Anholt spin_lock_init(&host->lock); 1275660fc733SEric Anholt mutex_init(&host->mutex); 1276660fc733SEric Anholt 1277660fc733SEric Anholt if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) { 1278660fc733SEric Anholt dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n"); 1279660fc733SEric Anholt host->use_dma = false; 1280660fc733SEric Anholt } else { 1281660fc733SEric Anholt host->use_dma = true; 1282660fc733SEric Anholt 1283660fc733SEric Anholt host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1284660fc733SEric Anholt host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1285660fc733SEric Anholt host->dma_cfg_tx.slave_id = 13; /* DREQ channel */ 1286660fc733SEric Anholt host->dma_cfg_tx.direction = DMA_MEM_TO_DEV; 1287660fc733SEric Anholt host->dma_cfg_tx.src_addr = 0; 1288660fc733SEric Anholt host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA; 1289660fc733SEric Anholt 1290660fc733SEric Anholt host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1291660fc733SEric Anholt host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1292660fc733SEric Anholt host->dma_cfg_rx.slave_id = 13; /* DREQ channel */ 1293660fc733SEric Anholt host->dma_cfg_rx.direction = DMA_DEV_TO_MEM; 1294660fc733SEric Anholt host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA; 1295660fc733SEric Anholt host->dma_cfg_rx.dst_addr = 0; 1296660fc733SEric Anholt 1297660fc733SEric Anholt if (dmaengine_slave_config(host->dma_chan_rxtx, 1298660fc733SEric Anholt &host->dma_cfg_tx) != 0 || 1299660fc733SEric Anholt dmaengine_slave_config(host->dma_chan_rxtx, 1300660fc733SEric Anholt &host->dma_cfg_rx) != 0) 1301660fc733SEric Anholt host->use_dma = false; 1302660fc733SEric Anholt } 1303660fc733SEric Anholt 1304660fc733SEric Anholt mmc->max_segs = 128; 1305660fc733SEric Anholt mmc->max_req_size = 524288; 1306660fc733SEric Anholt mmc->max_seg_size = mmc->max_req_size; 1307660fc733SEric Anholt mmc->max_blk_size = 1024; 1308660fc733SEric Anholt mmc->max_blk_count = 65535; 1309660fc733SEric Anholt 1310660fc733SEric Anholt /* report supported voltage ranges */ 1311660fc733SEric Anholt mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1312660fc733SEric Anholt 1313660fc733SEric Anholt INIT_WORK(&host->dma_work, bcm2835_dma_complete_work); 1314660fc733SEric Anholt INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout); 1315660fc733SEric Anholt 1316660fc733SEric Anholt /* Set interrupt enables */ 1317660fc733SEric Anholt host->hcfg = SDHCFG_BUSY_IRPT_EN; 1318660fc733SEric Anholt 1319660fc733SEric Anholt bcm2835_reset_internal(host); 1320660fc733SEric Anholt 1321660fc733SEric Anholt ret = request_threaded_irq(host->irq, bcm2835_irq, 1322660fc733SEric Anholt bcm2835_threaded_irq, 1323660fc733SEric Anholt 0, mmc_hostname(mmc), host); 1324660fc733SEric Anholt if (ret) { 1325660fc733SEric Anholt dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret); 1326660fc733SEric Anholt return ret; 1327660fc733SEric Anholt } 1328660fc733SEric Anholt 1329660fc733SEric Anholt ret = mmc_add_host(mmc); 1330660fc733SEric Anholt if (ret) { 1331660fc733SEric Anholt free_irq(host->irq, host); 1332660fc733SEric Anholt return ret; 1333660fc733SEric Anholt } 1334660fc733SEric Anholt 1335660fc733SEric Anholt pio_limit_string[0] = '\0'; 1336660fc733SEric Anholt if (host->use_dma && (PIO_THRESHOLD > 0)) 1337660fc733SEric Anholt sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD); 1338660fc733SEric Anholt dev_info(dev, "loaded - DMA %s%s\n", 1339660fc733SEric Anholt host->use_dma ? "enabled" : "disabled", pio_limit_string); 1340660fc733SEric Anholt 1341660fc733SEric Anholt return 0; 1342660fc733SEric Anholt } 1343660fc733SEric Anholt 1344660fc733SEric Anholt static int bcm2835_probe(struct platform_device *pdev) 1345660fc733SEric Anholt { 1346660fc733SEric Anholt struct device *dev = &pdev->dev; 1347660fc733SEric Anholt struct clk *clk; 1348660fc733SEric Anholt struct resource *iomem; 1349660fc733SEric Anholt struct bcm2835_host *host; 1350660fc733SEric Anholt struct mmc_host *mmc; 1351660fc733SEric Anholt const __be32 *regaddr_p; 1352660fc733SEric Anholt int ret; 1353660fc733SEric Anholt 1354660fc733SEric Anholt dev_dbg(dev, "%s\n", __func__); 1355660fc733SEric Anholt mmc = mmc_alloc_host(sizeof(*host), dev); 1356660fc733SEric Anholt if (!mmc) 1357660fc733SEric Anholt return -ENOMEM; 1358660fc733SEric Anholt 1359660fc733SEric Anholt mmc->ops = &bcm2835_ops; 1360660fc733SEric Anholt host = mmc_priv(mmc); 1361660fc733SEric Anholt host->mmc = mmc; 1362660fc733SEric Anholt host->pdev = pdev; 1363660fc733SEric Anholt spin_lock_init(&host->lock); 1364660fc733SEric Anholt 1365660fc733SEric Anholt iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1366660fc733SEric Anholt host->ioaddr = devm_ioremap_resource(dev, iomem); 1367660fc733SEric Anholt if (IS_ERR(host->ioaddr)) { 1368660fc733SEric Anholt ret = PTR_ERR(host->ioaddr); 1369660fc733SEric Anholt goto err; 1370660fc733SEric Anholt } 1371660fc733SEric Anholt 1372660fc733SEric Anholt /* Parse OF address directly to get the physical address for 1373660fc733SEric Anholt * DMA to our registers. 1374660fc733SEric Anholt */ 1375660fc733SEric Anholt regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 1376660fc733SEric Anholt if (!regaddr_p) { 1377660fc733SEric Anholt dev_err(dev, "Can't get phys address\n"); 1378660fc733SEric Anholt ret = -EINVAL; 1379660fc733SEric Anholt goto err; 1380660fc733SEric Anholt } 1381660fc733SEric Anholt 1382660fc733SEric Anholt host->phys_addr = be32_to_cpup(regaddr_p); 1383660fc733SEric Anholt 1384660fc733SEric Anholt host->dma_chan = NULL; 1385660fc733SEric Anholt host->dma_desc = NULL; 1386660fc733SEric Anholt 1387660fc733SEric Anholt host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx"); 1388660fc733SEric Anholt 1389660fc733SEric Anholt clk = devm_clk_get(dev, NULL); 1390660fc733SEric Anholt if (IS_ERR(clk)) { 1391660fc733SEric Anholt ret = PTR_ERR(clk); 1392660fc733SEric Anholt if (ret != -EPROBE_DEFER) 1393660fc733SEric Anholt dev_err(dev, "could not get clk: %d\n", ret); 1394660fc733SEric Anholt goto err; 1395660fc733SEric Anholt } 1396660fc733SEric Anholt 1397660fc733SEric Anholt host->max_clk = clk_get_rate(clk); 1398660fc733SEric Anholt 1399660fc733SEric Anholt host->irq = platform_get_irq(pdev, 0); 1400660fc733SEric Anholt if (host->irq <= 0) { 1401660fc733SEric Anholt dev_err(dev, "get IRQ failed\n"); 1402660fc733SEric Anholt ret = -EINVAL; 1403660fc733SEric Anholt goto err; 1404660fc733SEric Anholt } 1405660fc733SEric Anholt 1406660fc733SEric Anholt ret = mmc_of_parse(mmc); 1407660fc733SEric Anholt if (ret) 1408660fc733SEric Anholt goto err; 1409660fc733SEric Anholt 1410660fc733SEric Anholt ret = bcm2835_add_host(host); 1411660fc733SEric Anholt if (ret) 1412660fc733SEric Anholt goto err; 1413660fc733SEric Anholt 1414660fc733SEric Anholt platform_set_drvdata(pdev, host); 1415660fc733SEric Anholt 1416660fc733SEric Anholt dev_dbg(dev, "%s -> OK\n", __func__); 1417660fc733SEric Anholt 1418660fc733SEric Anholt return 0; 1419660fc733SEric Anholt 1420660fc733SEric Anholt err: 1421660fc733SEric Anholt dev_dbg(dev, "%s -> err %d\n", __func__, ret); 1422660fc733SEric Anholt mmc_free_host(mmc); 1423660fc733SEric Anholt 1424660fc733SEric Anholt return ret; 1425660fc733SEric Anholt } 1426660fc733SEric Anholt 1427660fc733SEric Anholt static int bcm2835_remove(struct platform_device *pdev) 1428660fc733SEric Anholt { 1429660fc733SEric Anholt struct bcm2835_host *host = platform_get_drvdata(pdev); 1430660fc733SEric Anholt 1431660fc733SEric Anholt mmc_remove_host(host->mmc); 1432660fc733SEric Anholt 1433660fc733SEric Anholt writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 1434660fc733SEric Anholt 1435660fc733SEric Anholt free_irq(host->irq, host); 1436660fc733SEric Anholt 1437660fc733SEric Anholt cancel_work_sync(&host->dma_work); 1438660fc733SEric Anholt cancel_delayed_work_sync(&host->timeout_work); 1439660fc733SEric Anholt 1440660fc733SEric Anholt mmc_free_host(host->mmc); 1441660fc733SEric Anholt platform_set_drvdata(pdev, NULL); 1442660fc733SEric Anholt 1443660fc733SEric Anholt return 0; 1444660fc733SEric Anholt } 1445660fc733SEric Anholt 1446660fc733SEric Anholt static const struct of_device_id bcm2835_match[] = { 1447660fc733SEric Anholt { .compatible = "brcm,bcm2835-sdhost" }, 1448660fc733SEric Anholt { } 1449660fc733SEric Anholt }; 1450660fc733SEric Anholt MODULE_DEVICE_TABLE(of, bcm2835_match); 1451660fc733SEric Anholt 1452660fc733SEric Anholt static struct platform_driver bcm2835_driver = { 1453660fc733SEric Anholt .probe = bcm2835_probe, 1454660fc733SEric Anholt .remove = bcm2835_remove, 1455660fc733SEric Anholt .driver = { 1456660fc733SEric Anholt .name = "sdhost-bcm2835", 1457660fc733SEric Anholt .of_match_table = bcm2835_match, 1458660fc733SEric Anholt }, 1459660fc733SEric Anholt }; 1460660fc733SEric Anholt module_platform_driver(bcm2835_driver); 1461660fc733SEric Anholt 1462660fc733SEric Anholt MODULE_ALIAS("platform:sdhost-bcm2835"); 1463660fc733SEric Anholt MODULE_DESCRIPTION("BCM2835 SDHost driver"); 1464660fc733SEric Anholt MODULE_LICENSE("GPL v2"); 1465660fc733SEric Anholt MODULE_AUTHOR("Phil Elwell"); 1466