1*b2adf788SChiYuan Huang /* SPDX-License-Identifier: GPL-2.0-only */ 2*b2adf788SChiYuan Huang /* 3*b2adf788SChiYuan Huang * Copyright (C) 2022 Richtek Technology Corp. 4*b2adf788SChiYuan Huang * 5*b2adf788SChiYuan Huang * Author: ChiYuan Huang <cy_huang@richtek.com> 6*b2adf788SChiYuan Huang */ 7*b2adf788SChiYuan Huang 8*b2adf788SChiYuan Huang #ifndef __MFD_MT6370_H__ 9*b2adf788SChiYuan Huang #define __MFD_MT6370_H__ 10*b2adf788SChiYuan Huang 11*b2adf788SChiYuan Huang /* IRQ definitions */ 12*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHGON 0 13*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_TREG 4 14*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_AICR 5 15*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_MIVR 6 16*b2adf788SChiYuan Huang #define MT6370_IRQ_PWR_RDY 7 17*b2adf788SChiYuan Huang #define MT6370_IRQ_FL_CHG_VINOVP 11 18*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_VSYSUV 12 19*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_VSYSOV 13 20*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_VBATOV 14 21*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_VINOVPCHG 15 22*b2adf788SChiYuan Huang #define MT6370_IRQ_TS_BAT_COLD 20 23*b2adf788SChiYuan Huang #define MT6370_IRQ_TS_BAT_COOL 21 24*b2adf788SChiYuan Huang #define MT6370_IRQ_TS_BAT_WARM 22 25*b2adf788SChiYuan Huang #define MT6370_IRQ_TS_BAT_HOT 23 26*b2adf788SChiYuan Huang #define MT6370_IRQ_TS_STATC 24 27*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_FAULT 25 28*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_STATC 26 29*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_TMR 27 30*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_BATABS 28 31*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_ADPBAD 29 32*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_RVP 30 33*b2adf788SChiYuan Huang #define MT6370_IRQ_TSHUTDOWN 31 34*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_IINMEAS 32 35*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_ICCMEAS 33 36*b2adf788SChiYuan Huang #define MT6370_IRQ_CHGDET_DONE 34 37*b2adf788SChiYuan Huang #define MT6370_IRQ_WDTMR 35 38*b2adf788SChiYuan Huang #define MT6370_IRQ_SSFINISH 36 39*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_RECHG 37 40*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_TERM 38 41*b2adf788SChiYuan Huang #define MT6370_IRQ_CHG_IEOC 39 42*b2adf788SChiYuan Huang #define MT6370_IRQ_ADC_DONE 40 43*b2adf788SChiYuan Huang #define MT6370_IRQ_PUMPX_DONE 41 44*b2adf788SChiYuan Huang #define MT6370_IRQ_BST_BATUV 45 45*b2adf788SChiYuan Huang #define MT6370_IRQ_BST_MIDOV 46 46*b2adf788SChiYuan Huang #define MT6370_IRQ_BST_OLP 47 47*b2adf788SChiYuan Huang #define MT6370_IRQ_ATTACH 48 48*b2adf788SChiYuan Huang #define MT6370_IRQ_DETACH 49 49*b2adf788SChiYuan Huang #define MT6370_IRQ_HVDCP_STPDONE 51 50*b2adf788SChiYuan Huang #define MT6370_IRQ_HVDCP_VBUSDET_DONE 52 51*b2adf788SChiYuan Huang #define MT6370_IRQ_HVDCP_DET 53 52*b2adf788SChiYuan Huang #define MT6370_IRQ_CHGDET 54 53*b2adf788SChiYuan Huang #define MT6370_IRQ_DCDT 55 54*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHG_VGOK 59 55*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHG_WDTMR 60 56*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHG_UC 61 57*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHG_OC 62 58*b2adf788SChiYuan Huang #define MT6370_IRQ_DIRCHG_OV 63 59*b2adf788SChiYuan Huang #define MT6370_IRQ_OVPCTRL_SWON 67 60*b2adf788SChiYuan Huang #define MT6370_IRQ_OVPCTRL_UVP_D 68 61*b2adf788SChiYuan Huang #define MT6370_IRQ_OVPCTRL_UVP 69 62*b2adf788SChiYuan Huang #define MT6370_IRQ_OVPCTRL_OVP_D 70 63*b2adf788SChiYuan Huang #define MT6370_IRQ_OVPCTRL_OVP 71 64*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED_STRBPIN 72 65*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED_TORPIN 73 66*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED_TX 74 67*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED_LVF 75 68*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED2_SHORT 78 69*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED1_SHORT 79 70*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED2_STRB 80 71*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED1_STRB 81 72*b2adf788SChiYuan Huang #define mT6370_IRQ_FLED2_STRB_TO 82 73*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED1_STRB_TO 83 74*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED2_TOR 84 75*b2adf788SChiYuan Huang #define MT6370_IRQ_FLED1_TOR 85 76*b2adf788SChiYuan Huang #define MT6370_IRQ_OTP 93 77*b2adf788SChiYuan Huang #define MT6370_IRQ_VDDA_OVP 94 78*b2adf788SChiYuan Huang #define MT6370_IRQ_VDDA_UV 95 79*b2adf788SChiYuan Huang #define MT6370_IRQ_LDO_OC 103 80*b2adf788SChiYuan Huang #define MT6370_IRQ_BLED_OCP 118 81*b2adf788SChiYuan Huang #define MT6370_IRQ_BLED_OVP 119 82*b2adf788SChiYuan Huang #define MT6370_IRQ_DSV_VNEG_OCP 123 83*b2adf788SChiYuan Huang #define MT6370_IRQ_DSV_VPOS_OCP 124 84*b2adf788SChiYuan Huang #define MT6370_IRQ_DSV_BST_OCP 125 85*b2adf788SChiYuan Huang #define MT6370_IRQ_DSV_VNEG_SCP 126 86*b2adf788SChiYuan Huang #define MT6370_IRQ_DSV_VPOS_SCP 127 87*b2adf788SChiYuan Huang 88*b2adf788SChiYuan Huang enum { 89*b2adf788SChiYuan Huang MT6370_USBC_I2C = 0, 90*b2adf788SChiYuan Huang MT6370_PMU_I2C, 91*b2adf788SChiYuan Huang MT6370_MAX_I2C 92*b2adf788SChiYuan Huang }; 93*b2adf788SChiYuan Huang 94*b2adf788SChiYuan Huang struct mt6370_info { 95*b2adf788SChiYuan Huang struct i2c_client *i2c[MT6370_MAX_I2C]; 96*b2adf788SChiYuan Huang struct regmap_irq_chip_data *irq_data; 97*b2adf788SChiYuan Huang }; 98*b2adf788SChiYuan Huang 99*b2adf788SChiYuan Huang #endif /* __MFD_MT6375_H__ */ 100