xref: /openbmc/linux/drivers/mfd/mt6370.h (revision b2adf788)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2022 Richtek Technology Corp.
4  *
5  * Author: ChiYuan Huang <cy_huang@richtek.com>
6  */
7 
8 #ifndef __MFD_MT6370_H__
9 #define __MFD_MT6370_H__
10 
11 /* IRQ definitions */
12 #define MT6370_IRQ_DIRCHGON		0
13 #define MT6370_IRQ_CHG_TREG		4
14 #define MT6370_IRQ_CHG_AICR		5
15 #define MT6370_IRQ_CHG_MIVR		6
16 #define MT6370_IRQ_PWR_RDY		7
17 #define MT6370_IRQ_FL_CHG_VINOVP	11
18 #define MT6370_IRQ_CHG_VSYSUV		12
19 #define MT6370_IRQ_CHG_VSYSOV		13
20 #define MT6370_IRQ_CHG_VBATOV		14
21 #define MT6370_IRQ_CHG_VINOVPCHG	15
22 #define MT6370_IRQ_TS_BAT_COLD		20
23 #define MT6370_IRQ_TS_BAT_COOL		21
24 #define MT6370_IRQ_TS_BAT_WARM		22
25 #define MT6370_IRQ_TS_BAT_HOT		23
26 #define MT6370_IRQ_TS_STATC		24
27 #define MT6370_IRQ_CHG_FAULT		25
28 #define MT6370_IRQ_CHG_STATC		26
29 #define MT6370_IRQ_CHG_TMR		27
30 #define MT6370_IRQ_CHG_BATABS		28
31 #define MT6370_IRQ_CHG_ADPBAD		29
32 #define MT6370_IRQ_CHG_RVP		30
33 #define MT6370_IRQ_TSHUTDOWN		31
34 #define MT6370_IRQ_CHG_IINMEAS		32
35 #define MT6370_IRQ_CHG_ICCMEAS		33
36 #define MT6370_IRQ_CHGDET_DONE		34
37 #define MT6370_IRQ_WDTMR		35
38 #define MT6370_IRQ_SSFINISH		36
39 #define MT6370_IRQ_CHG_RECHG		37
40 #define MT6370_IRQ_CHG_TERM		38
41 #define MT6370_IRQ_CHG_IEOC		39
42 #define MT6370_IRQ_ADC_DONE		40
43 #define MT6370_IRQ_PUMPX_DONE		41
44 #define MT6370_IRQ_BST_BATUV		45
45 #define MT6370_IRQ_BST_MIDOV		46
46 #define MT6370_IRQ_BST_OLP		47
47 #define MT6370_IRQ_ATTACH		48
48 #define MT6370_IRQ_DETACH		49
49 #define MT6370_IRQ_HVDCP_STPDONE	51
50 #define MT6370_IRQ_HVDCP_VBUSDET_DONE	52
51 #define MT6370_IRQ_HVDCP_DET		53
52 #define MT6370_IRQ_CHGDET		54
53 #define MT6370_IRQ_DCDT			55
54 #define MT6370_IRQ_DIRCHG_VGOK		59
55 #define MT6370_IRQ_DIRCHG_WDTMR		60
56 #define MT6370_IRQ_DIRCHG_UC		61
57 #define MT6370_IRQ_DIRCHG_OC		62
58 #define MT6370_IRQ_DIRCHG_OV		63
59 #define MT6370_IRQ_OVPCTRL_SWON		67
60 #define MT6370_IRQ_OVPCTRL_UVP_D	68
61 #define MT6370_IRQ_OVPCTRL_UVP		69
62 #define MT6370_IRQ_OVPCTRL_OVP_D	70
63 #define MT6370_IRQ_OVPCTRL_OVP		71
64 #define MT6370_IRQ_FLED_STRBPIN		72
65 #define MT6370_IRQ_FLED_TORPIN		73
66 #define MT6370_IRQ_FLED_TX		74
67 #define MT6370_IRQ_FLED_LVF		75
68 #define MT6370_IRQ_FLED2_SHORT		78
69 #define MT6370_IRQ_FLED1_SHORT		79
70 #define MT6370_IRQ_FLED2_STRB		80
71 #define MT6370_IRQ_FLED1_STRB		81
72 #define mT6370_IRQ_FLED2_STRB_TO	82
73 #define MT6370_IRQ_FLED1_STRB_TO	83
74 #define MT6370_IRQ_FLED2_TOR		84
75 #define MT6370_IRQ_FLED1_TOR		85
76 #define MT6370_IRQ_OTP			93
77 #define MT6370_IRQ_VDDA_OVP		94
78 #define MT6370_IRQ_VDDA_UV		95
79 #define MT6370_IRQ_LDO_OC		103
80 #define MT6370_IRQ_BLED_OCP		118
81 #define MT6370_IRQ_BLED_OVP		119
82 #define MT6370_IRQ_DSV_VNEG_OCP		123
83 #define MT6370_IRQ_DSV_VPOS_OCP		124
84 #define MT6370_IRQ_DSV_BST_OCP		125
85 #define MT6370_IRQ_DSV_VNEG_SCP		126
86 #define MT6370_IRQ_DSV_VPOS_SCP		127
87 
88 enum {
89 	MT6370_USBC_I2C = 0,
90 	MT6370_PMU_I2C,
91 	MT6370_MAX_I2C
92 };
93 
94 struct mt6370_info {
95 	struct i2c_client *i2c[MT6370_MAX_I2C];
96 	struct regmap_irq_chip_data *irq_data;
97 };
98 
99 #endif /* __MFD_MT6375_H__ */
100