xref: /openbmc/linux/drivers/media/i2c/ov9734.c (revision 92d25e02)
1d3f863a6STianshu Qiu // SPDX-License-Identifier: GPL-2.0
2d3f863a6STianshu Qiu // Copyright (c) 2020 Intel Corporation.
3d3f863a6STianshu Qiu 
4d3f863a6STianshu Qiu #include <asm/unaligned.h>
5d3f863a6STianshu Qiu #include <linux/acpi.h>
6d3f863a6STianshu Qiu #include <linux/delay.h>
7d3f863a6STianshu Qiu #include <linux/i2c.h>
8d3f863a6STianshu Qiu #include <linux/module.h>
9d3f863a6STianshu Qiu #include <linux/pm_runtime.h>
10d3f863a6STianshu Qiu #include <media/v4l2-ctrls.h>
11d3f863a6STianshu Qiu #include <media/v4l2-device.h>
12d3f863a6STianshu Qiu #include <media/v4l2-fwnode.h>
13d3f863a6STianshu Qiu 
14d3f863a6STianshu Qiu #define OV9734_LINK_FREQ_180MHZ		180000000ULL
15d3f863a6STianshu Qiu #define OV9734_SCLK			36000000LL
16d3f863a6STianshu Qiu #define OV9734_MCLK			19200000
17d3f863a6STianshu Qiu /* ov9734 only support 1-lane mipi output */
18d3f863a6STianshu Qiu #define OV9734_DATA_LANES		1
19d3f863a6STianshu Qiu #define OV9734_RGB_DEPTH		10
20d3f863a6STianshu Qiu 
21d3f863a6STianshu Qiu #define OV9734_REG_CHIP_ID		0x300a
22d3f863a6STianshu Qiu #define OV9734_CHIP_ID			0x9734
23d3f863a6STianshu Qiu 
24d3f863a6STianshu Qiu #define OV9734_REG_MODE_SELECT		0x0100
25d3f863a6STianshu Qiu #define OV9734_MODE_STANDBY		0x00
26d3f863a6STianshu Qiu #define OV9734_MODE_STREAMING		0x01
27d3f863a6STianshu Qiu 
28d3f863a6STianshu Qiu /* vertical-timings from sensor */
29d3f863a6STianshu Qiu #define OV9734_REG_VTS			0x380e
30d3f863a6STianshu Qiu #define OV9734_VTS_30FPS		0x0322
31d3f863a6STianshu Qiu #define OV9734_VTS_30FPS_MIN		0x0322
32d3f863a6STianshu Qiu #define OV9734_VTS_MAX			0x7fff
33d3f863a6STianshu Qiu 
34d3f863a6STianshu Qiu /* horizontal-timings from sensor */
35d3f863a6STianshu Qiu #define OV9734_REG_HTS			0x380c
36d3f863a6STianshu Qiu 
37d3f863a6STianshu Qiu /* Exposure controls from sensor */
38d3f863a6STianshu Qiu #define OV9734_REG_EXPOSURE		0x3500
39d3f863a6STianshu Qiu #define OV9734_EXPOSURE_MIN		4
40d3f863a6STianshu Qiu #define OV9734_EXPOSURE_MAX_MARGIN	4
41d3f863a6STianshu Qiu #define	OV9734_EXPOSURE_STEP		1
42d3f863a6STianshu Qiu 
43d3f863a6STianshu Qiu /* Analog gain controls from sensor */
44d3f863a6STianshu Qiu #define OV9734_REG_ANALOG_GAIN		0x350a
45d3f863a6STianshu Qiu #define OV9734_ANAL_GAIN_MIN		16
46d3f863a6STianshu Qiu #define OV9734_ANAL_GAIN_MAX		248
47d3f863a6STianshu Qiu #define OV9734_ANAL_GAIN_STEP		1
48d3f863a6STianshu Qiu 
49d3f863a6STianshu Qiu /* Digital gain controls from sensor */
50d3f863a6STianshu Qiu #define OV9734_REG_MWB_R_GAIN		0x5180
51d3f863a6STianshu Qiu #define OV9734_REG_MWB_G_GAIN		0x5182
52d3f863a6STianshu Qiu #define OV9734_REG_MWB_B_GAIN		0x5184
53d3f863a6STianshu Qiu #define OV9734_DGTL_GAIN_MIN		256
54d3f863a6STianshu Qiu #define OV9734_DGTL_GAIN_MAX		1023
55d3f863a6STianshu Qiu #define OV9734_DGTL_GAIN_STEP		1
56d3f863a6STianshu Qiu #define OV9734_DGTL_GAIN_DEFAULT	256
57d3f863a6STianshu Qiu 
58d3f863a6STianshu Qiu /* Test Pattern Control */
59d3f863a6STianshu Qiu #define OV9734_REG_TEST_PATTERN		0x5080
60d3f863a6STianshu Qiu #define OV9734_TEST_PATTERN_ENABLE	BIT(7)
61d3f863a6STianshu Qiu #define OV9734_TEST_PATTERN_BAR_SHIFT	2
62d3f863a6STianshu Qiu 
630e2b8552SBingbu Cao /* Group Access */
640e2b8552SBingbu Cao #define OV9734_REG_GROUP_ACCESS		0x3208
650e2b8552SBingbu Cao #define OV9734_GROUP_HOLD_START		0x0
660e2b8552SBingbu Cao #define OV9734_GROUP_HOLD_END		0x10
670e2b8552SBingbu Cao #define OV9734_GROUP_HOLD_LAUNCH	0xa0
680e2b8552SBingbu Cao 
69d3f863a6STianshu Qiu enum {
70d3f863a6STianshu Qiu 	OV9734_LINK_FREQ_180MHZ_INDEX,
71d3f863a6STianshu Qiu };
72d3f863a6STianshu Qiu 
73d3f863a6STianshu Qiu struct ov9734_reg {
74d3f863a6STianshu Qiu 	u16 address;
75d3f863a6STianshu Qiu 	u8 val;
76d3f863a6STianshu Qiu };
77d3f863a6STianshu Qiu 
78d3f863a6STianshu Qiu struct ov9734_reg_list {
79d3f863a6STianshu Qiu 	u32 num_of_regs;
80d3f863a6STianshu Qiu 	const struct ov9734_reg *regs;
81d3f863a6STianshu Qiu };
82d3f863a6STianshu Qiu 
83d3f863a6STianshu Qiu struct ov9734_link_freq_config {
84d3f863a6STianshu Qiu 	const struct ov9734_reg_list reg_list;
85d3f863a6STianshu Qiu };
86d3f863a6STianshu Qiu 
87d3f863a6STianshu Qiu struct ov9734_mode {
88d3f863a6STianshu Qiu 	/* Frame width in pixels */
89d3f863a6STianshu Qiu 	u32 width;
90d3f863a6STianshu Qiu 
91d3f863a6STianshu Qiu 	/* Frame height in pixels */
92d3f863a6STianshu Qiu 	u32 height;
93d3f863a6STianshu Qiu 
94d3f863a6STianshu Qiu 	/* Horizontal timining size */
95d3f863a6STianshu Qiu 	u32 hts;
96d3f863a6STianshu Qiu 
97d3f863a6STianshu Qiu 	/* Default vertical timining size */
98d3f863a6STianshu Qiu 	u32 vts_def;
99d3f863a6STianshu Qiu 
100d3f863a6STianshu Qiu 	/* Min vertical timining size */
101d3f863a6STianshu Qiu 	u32 vts_min;
102d3f863a6STianshu Qiu 
103d3f863a6STianshu Qiu 	/* Link frequency needed for this resolution */
104d3f863a6STianshu Qiu 	u32 link_freq_index;
105d3f863a6STianshu Qiu 
106d3f863a6STianshu Qiu 	/* Sensor register settings for this resolution */
107d3f863a6STianshu Qiu 	const struct ov9734_reg_list reg_list;
108d3f863a6STianshu Qiu };
109d3f863a6STianshu Qiu 
110d3f863a6STianshu Qiu static const struct ov9734_reg mipi_data_rate_360mbps[] = {
111d3f863a6STianshu Qiu 	{0x3030, 0x19},
112d3f863a6STianshu Qiu 	{0x3080, 0x02},
113d3f863a6STianshu Qiu 	{0x3081, 0x4b},
114d3f863a6STianshu Qiu 	{0x3082, 0x04},
115d3f863a6STianshu Qiu 	{0x3083, 0x00},
116d3f863a6STianshu Qiu 	{0x3084, 0x02},
117d3f863a6STianshu Qiu 	{0x3085, 0x01},
118d3f863a6STianshu Qiu 	{0x3086, 0x01},
119d3f863a6STianshu Qiu 	{0x3089, 0x01},
120d3f863a6STianshu Qiu 	{0x308a, 0x00},
121d3f863a6STianshu Qiu 	{0x301e, 0x15},
122d3f863a6STianshu Qiu 	{0x3103, 0x01},
123d3f863a6STianshu Qiu };
124d3f863a6STianshu Qiu 
125d3f863a6STianshu Qiu static const struct ov9734_reg mode_1296x734_regs[] = {
126d3f863a6STianshu Qiu 	{0x3001, 0x00},
127d3f863a6STianshu Qiu 	{0x3002, 0x00},
128d3f863a6STianshu Qiu 	{0x3007, 0x00},
129d3f863a6STianshu Qiu 	{0x3010, 0x00},
130d3f863a6STianshu Qiu 	{0x3011, 0x08},
131d3f863a6STianshu Qiu 	{0x3014, 0x22},
132d3f863a6STianshu Qiu 	{0x3600, 0x55},
133d3f863a6STianshu Qiu 	{0x3601, 0x02},
134d3f863a6STianshu Qiu 	{0x3605, 0x22},
135d3f863a6STianshu Qiu 	{0x3611, 0xe7},
136d3f863a6STianshu Qiu 	{0x3654, 0x10},
137d3f863a6STianshu Qiu 	{0x3655, 0x77},
138d3f863a6STianshu Qiu 	{0x3656, 0x77},
139d3f863a6STianshu Qiu 	{0x3657, 0x07},
140d3f863a6STianshu Qiu 	{0x3658, 0x22},
141d3f863a6STianshu Qiu 	{0x3659, 0x22},
142d3f863a6STianshu Qiu 	{0x365a, 0x02},
143d3f863a6STianshu Qiu 	{0x3784, 0x05},
144d3f863a6STianshu Qiu 	{0x3785, 0x55},
145d3f863a6STianshu Qiu 	{0x37c0, 0x07},
146d3f863a6STianshu Qiu 	{0x3800, 0x00},
147d3f863a6STianshu Qiu 	{0x3801, 0x04},
148d3f863a6STianshu Qiu 	{0x3802, 0x00},
149d3f863a6STianshu Qiu 	{0x3803, 0x04},
150d3f863a6STianshu Qiu 	{0x3804, 0x05},
151d3f863a6STianshu Qiu 	{0x3805, 0x0b},
152d3f863a6STianshu Qiu 	{0x3806, 0x02},
153d3f863a6STianshu Qiu 	{0x3807, 0xdb},
154d3f863a6STianshu Qiu 	{0x3808, 0x05},
155d3f863a6STianshu Qiu 	{0x3809, 0x00},
156d3f863a6STianshu Qiu 	{0x380a, 0x02},
157d3f863a6STianshu Qiu 	{0x380b, 0xd0},
158d3f863a6STianshu Qiu 	{0x380c, 0x05},
159d3f863a6STianshu Qiu 	{0x380d, 0xc6},
160d3f863a6STianshu Qiu 	{0x380e, 0x03},
161d3f863a6STianshu Qiu 	{0x380f, 0x22},
162d3f863a6STianshu Qiu 	{0x3810, 0x00},
163d3f863a6STianshu Qiu 	{0x3811, 0x04},
164d3f863a6STianshu Qiu 	{0x3812, 0x00},
165d3f863a6STianshu Qiu 	{0x3813, 0x04},
166d3f863a6STianshu Qiu 	{0x3816, 0x00},
167d3f863a6STianshu Qiu 	{0x3817, 0x00},
168d3f863a6STianshu Qiu 	{0x3818, 0x00},
169d3f863a6STianshu Qiu 	{0x3819, 0x04},
170d3f863a6STianshu Qiu 	{0x3820, 0x18},
171d3f863a6STianshu Qiu 	{0x3821, 0x00},
172d3f863a6STianshu Qiu 	{0x382c, 0x06},
173d3f863a6STianshu Qiu 	{0x3500, 0x00},
174d3f863a6STianshu Qiu 	{0x3501, 0x31},
175d3f863a6STianshu Qiu 	{0x3502, 0x00},
176d3f863a6STianshu Qiu 	{0x3503, 0x03},
177d3f863a6STianshu Qiu 	{0x3504, 0x00},
178d3f863a6STianshu Qiu 	{0x3505, 0x00},
179d3f863a6STianshu Qiu 	{0x3509, 0x10},
180d3f863a6STianshu Qiu 	{0x350a, 0x00},
181d3f863a6STianshu Qiu 	{0x350b, 0x40},
182d3f863a6STianshu Qiu 	{0x3d00, 0x00},
183d3f863a6STianshu Qiu 	{0x3d01, 0x00},
184d3f863a6STianshu Qiu 	{0x3d02, 0x00},
185d3f863a6STianshu Qiu 	{0x3d03, 0x00},
186d3f863a6STianshu Qiu 	{0x3d04, 0x00},
187d3f863a6STianshu Qiu 	{0x3d05, 0x00},
188d3f863a6STianshu Qiu 	{0x3d06, 0x00},
189d3f863a6STianshu Qiu 	{0x3d07, 0x00},
190d3f863a6STianshu Qiu 	{0x3d08, 0x00},
191d3f863a6STianshu Qiu 	{0x3d09, 0x00},
192d3f863a6STianshu Qiu 	{0x3d0a, 0x00},
193d3f863a6STianshu Qiu 	{0x3d0b, 0x00},
194d3f863a6STianshu Qiu 	{0x3d0c, 0x00},
195d3f863a6STianshu Qiu 	{0x3d0d, 0x00},
196d3f863a6STianshu Qiu 	{0x3d0e, 0x00},
197d3f863a6STianshu Qiu 	{0x3d0f, 0x00},
198d3f863a6STianshu Qiu 	{0x3d80, 0x00},
199d3f863a6STianshu Qiu 	{0x3d81, 0x00},
200d3f863a6STianshu Qiu 	{0x3d82, 0x38},
201d3f863a6STianshu Qiu 	{0x3d83, 0xa4},
202d3f863a6STianshu Qiu 	{0x3d84, 0x00},
203d3f863a6STianshu Qiu 	{0x3d85, 0x00},
204d3f863a6STianshu Qiu 	{0x3d86, 0x1f},
205d3f863a6STianshu Qiu 	{0x3d87, 0x03},
206d3f863a6STianshu Qiu 	{0x3d8b, 0x00},
207d3f863a6STianshu Qiu 	{0x3d8f, 0x00},
208d3f863a6STianshu Qiu 	{0x4001, 0xe0},
209d3f863a6STianshu Qiu 	{0x4009, 0x0b},
210d3f863a6STianshu Qiu 	{0x4300, 0x03},
211d3f863a6STianshu Qiu 	{0x4301, 0xff},
212d3f863a6STianshu Qiu 	{0x4304, 0x00},
213d3f863a6STianshu Qiu 	{0x4305, 0x00},
214d3f863a6STianshu Qiu 	{0x4309, 0x00},
215d3f863a6STianshu Qiu 	{0x4600, 0x00},
216d3f863a6STianshu Qiu 	{0x4601, 0x80},
217d3f863a6STianshu Qiu 	{0x4800, 0x00},
218d3f863a6STianshu Qiu 	{0x4805, 0x00},
219d3f863a6STianshu Qiu 	{0x4821, 0x50},
220d3f863a6STianshu Qiu 	{0x4823, 0x50},
221d3f863a6STianshu Qiu 	{0x4837, 0x2d},
222d3f863a6STianshu Qiu 	{0x4a00, 0x00},
223d3f863a6STianshu Qiu 	{0x4f00, 0x80},
224d3f863a6STianshu Qiu 	{0x4f01, 0x10},
225d3f863a6STianshu Qiu 	{0x4f02, 0x00},
226d3f863a6STianshu Qiu 	{0x4f03, 0x00},
227d3f863a6STianshu Qiu 	{0x4f04, 0x00},
228d3f863a6STianshu Qiu 	{0x4f05, 0x00},
229d3f863a6STianshu Qiu 	{0x4f06, 0x00},
230d3f863a6STianshu Qiu 	{0x4f07, 0x00},
231d3f863a6STianshu Qiu 	{0x4f08, 0x00},
232d3f863a6STianshu Qiu 	{0x4f09, 0x00},
233d3f863a6STianshu Qiu 	{0x5000, 0x2f},
234d3f863a6STianshu Qiu 	{0x500c, 0x00},
235d3f863a6STianshu Qiu 	{0x500d, 0x00},
236d3f863a6STianshu Qiu 	{0x500e, 0x00},
237d3f863a6STianshu Qiu 	{0x500f, 0x00},
238d3f863a6STianshu Qiu 	{0x5010, 0x00},
239d3f863a6STianshu Qiu 	{0x5011, 0x00},
240d3f863a6STianshu Qiu 	{0x5012, 0x00},
241d3f863a6STianshu Qiu 	{0x5013, 0x00},
242d3f863a6STianshu Qiu 	{0x5014, 0x00},
243d3f863a6STianshu Qiu 	{0x5015, 0x00},
244d3f863a6STianshu Qiu 	{0x5016, 0x00},
245d3f863a6STianshu Qiu 	{0x5017, 0x00},
246d3f863a6STianshu Qiu 	{0x5080, 0x00},
247d3f863a6STianshu Qiu 	{0x5180, 0x01},
248d3f863a6STianshu Qiu 	{0x5181, 0x00},
249d3f863a6STianshu Qiu 	{0x5182, 0x01},
250d3f863a6STianshu Qiu 	{0x5183, 0x00},
251d3f863a6STianshu Qiu 	{0x5184, 0x01},
252d3f863a6STianshu Qiu 	{0x5185, 0x00},
253d3f863a6STianshu Qiu 	{0x5708, 0x06},
254d3f863a6STianshu Qiu 	{0x380f, 0x2a},
255d3f863a6STianshu Qiu 	{0x5780, 0x3e},
256d3f863a6STianshu Qiu 	{0x5781, 0x0f},
257d3f863a6STianshu Qiu 	{0x5782, 0x44},
258d3f863a6STianshu Qiu 	{0x5783, 0x02},
259d3f863a6STianshu Qiu 	{0x5784, 0x01},
260d3f863a6STianshu Qiu 	{0x5785, 0x01},
261d3f863a6STianshu Qiu 	{0x5786, 0x00},
262d3f863a6STianshu Qiu 	{0x5787, 0x04},
263d3f863a6STianshu Qiu 	{0x5788, 0x02},
264d3f863a6STianshu Qiu 	{0x5789, 0x0f},
265d3f863a6STianshu Qiu 	{0x578a, 0xfd},
266d3f863a6STianshu Qiu 	{0x578b, 0xf5},
267d3f863a6STianshu Qiu 	{0x578c, 0xf5},
268d3f863a6STianshu Qiu 	{0x578d, 0x03},
269d3f863a6STianshu Qiu 	{0x578e, 0x08},
270d3f863a6STianshu Qiu 	{0x578f, 0x0c},
271d3f863a6STianshu Qiu 	{0x5790, 0x08},
272d3f863a6STianshu Qiu 	{0x5791, 0x04},
273d3f863a6STianshu Qiu 	{0x5792, 0x00},
274d3f863a6STianshu Qiu 	{0x5793, 0x52},
275d3f863a6STianshu Qiu 	{0x5794, 0xa3},
276d3f863a6STianshu Qiu 	{0x5000, 0x3f},
277d3f863a6STianshu Qiu 	{0x3801, 0x00},
278d3f863a6STianshu Qiu 	{0x3803, 0x00},
279d3f863a6STianshu Qiu 	{0x3805, 0x0f},
280d3f863a6STianshu Qiu 	{0x3807, 0xdf},
281d3f863a6STianshu Qiu 	{0x3809, 0x10},
282d3f863a6STianshu Qiu 	{0x380b, 0xde},
283d3f863a6STianshu Qiu 	{0x3811, 0x00},
284d3f863a6STianshu Qiu 	{0x3813, 0x01},
285d3f863a6STianshu Qiu };
286d3f863a6STianshu Qiu 
287d3f863a6STianshu Qiu static const char * const ov9734_test_pattern_menu[] = {
288d3f863a6STianshu Qiu 	"Disabled",
289d3f863a6STianshu Qiu 	"Standard Color Bar",
290d3f863a6STianshu Qiu 	"Top-Bottom Darker Color Bar",
291d3f863a6STianshu Qiu 	"Right-Left Darker Color Bar",
292d3f863a6STianshu Qiu 	"Bottom-Top Darker Color Bar",
293d3f863a6STianshu Qiu };
294d3f863a6STianshu Qiu 
295d3f863a6STianshu Qiu static const s64 link_freq_menu_items[] = {
296d3f863a6STianshu Qiu 	OV9734_LINK_FREQ_180MHZ,
297d3f863a6STianshu Qiu };
298d3f863a6STianshu Qiu 
299d3f863a6STianshu Qiu static const struct ov9734_link_freq_config link_freq_configs[] = {
300d3f863a6STianshu Qiu 	[OV9734_LINK_FREQ_180MHZ_INDEX] = {
301d3f863a6STianshu Qiu 		.reg_list = {
302d3f863a6STianshu Qiu 			.num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),
303d3f863a6STianshu Qiu 			.regs = mipi_data_rate_360mbps,
304d3f863a6STianshu Qiu 		}
305d3f863a6STianshu Qiu 	},
306d3f863a6STianshu Qiu };
307d3f863a6STianshu Qiu 
308d3f863a6STianshu Qiu static const struct ov9734_mode supported_modes[] = {
309d3f863a6STianshu Qiu 	{
310d3f863a6STianshu Qiu 		.width = 1296,
311d3f863a6STianshu Qiu 		.height = 734,
312d3f863a6STianshu Qiu 		.hts = 0x5c6,
313d3f863a6STianshu Qiu 		.vts_def = OV9734_VTS_30FPS,
314d3f863a6STianshu Qiu 		.vts_min = OV9734_VTS_30FPS_MIN,
315d3f863a6STianshu Qiu 		.reg_list = {
316d3f863a6STianshu Qiu 			.num_of_regs = ARRAY_SIZE(mode_1296x734_regs),
317d3f863a6STianshu Qiu 			.regs = mode_1296x734_regs,
318d3f863a6STianshu Qiu 		},
319d3f863a6STianshu Qiu 		.link_freq_index = OV9734_LINK_FREQ_180MHZ_INDEX,
320d3f863a6STianshu Qiu 	},
321d3f863a6STianshu Qiu };
322d3f863a6STianshu Qiu 
323d3f863a6STianshu Qiu struct ov9734 {
324d3f863a6STianshu Qiu 	struct v4l2_subdev sd;
325d3f863a6STianshu Qiu 	struct media_pad pad;
326d3f863a6STianshu Qiu 	struct v4l2_ctrl_handler ctrl_handler;
327d3f863a6STianshu Qiu 
328d3f863a6STianshu Qiu 	/* V4L2 Controls */
329d3f863a6STianshu Qiu 	struct v4l2_ctrl *link_freq;
330d3f863a6STianshu Qiu 	struct v4l2_ctrl *pixel_rate;
331d3f863a6STianshu Qiu 	struct v4l2_ctrl *vblank;
332d3f863a6STianshu Qiu 	struct v4l2_ctrl *hblank;
333d3f863a6STianshu Qiu 	struct v4l2_ctrl *exposure;
334d3f863a6STianshu Qiu 
335d3f863a6STianshu Qiu 	/* Current mode */
336d3f863a6STianshu Qiu 	const struct ov9734_mode *cur_mode;
337d3f863a6STianshu Qiu 
338d3f863a6STianshu Qiu 	/* To serialize asynchronus callbacks */
339d3f863a6STianshu Qiu 	struct mutex mutex;
340d3f863a6STianshu Qiu 
341d3f863a6STianshu Qiu 	/* Streaming on/off */
342d3f863a6STianshu Qiu 	bool streaming;
343d3f863a6STianshu Qiu };
344d3f863a6STianshu Qiu 
to_ov9734(struct v4l2_subdev * subdev)345d3f863a6STianshu Qiu static inline struct ov9734 *to_ov9734(struct v4l2_subdev *subdev)
346d3f863a6STianshu Qiu {
347d3f863a6STianshu Qiu 	return container_of(subdev, struct ov9734, sd);
348d3f863a6STianshu Qiu }
349d3f863a6STianshu Qiu 
to_pixel_rate(u32 f_index)350d3f863a6STianshu Qiu static u64 to_pixel_rate(u32 f_index)
351d3f863a6STianshu Qiu {
352d3f863a6STianshu Qiu 	u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV9734_DATA_LANES;
353d3f863a6STianshu Qiu 
354d3f863a6STianshu Qiu 	do_div(pixel_rate, OV9734_RGB_DEPTH);
355d3f863a6STianshu Qiu 
356d3f863a6STianshu Qiu 	return pixel_rate;
357d3f863a6STianshu Qiu }
358d3f863a6STianshu Qiu 
to_pixels_per_line(u32 hts,u32 f_index)359d3f863a6STianshu Qiu static u64 to_pixels_per_line(u32 hts, u32 f_index)
360d3f863a6STianshu Qiu {
361d3f863a6STianshu Qiu 	u64 ppl = hts * to_pixel_rate(f_index);
362d3f863a6STianshu Qiu 
363d3f863a6STianshu Qiu 	do_div(ppl, OV9734_SCLK);
364d3f863a6STianshu Qiu 
365d3f863a6STianshu Qiu 	return ppl;
366d3f863a6STianshu Qiu }
367d3f863a6STianshu Qiu 
ov9734_read_reg(struct ov9734 * ov9734,u16 reg,u16 len,u32 * val)368d3f863a6STianshu Qiu static int ov9734_read_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 *val)
369d3f863a6STianshu Qiu {
370d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
371d3f863a6STianshu Qiu 	struct i2c_msg msgs[2];
372d3f863a6STianshu Qiu 	u8 addr_buf[2];
373d3f863a6STianshu Qiu 	u8 data_buf[4] = {0};
374d3f863a6STianshu Qiu 	int ret;
375d3f863a6STianshu Qiu 
376d3f863a6STianshu Qiu 	if (len > sizeof(data_buf))
377d3f863a6STianshu Qiu 		return -EINVAL;
378d3f863a6STianshu Qiu 
379d3f863a6STianshu Qiu 	put_unaligned_be16(reg, addr_buf);
380d3f863a6STianshu Qiu 	msgs[0].addr = client->addr;
381d3f863a6STianshu Qiu 	msgs[0].flags = 0;
382d3f863a6STianshu Qiu 	msgs[0].len = sizeof(addr_buf);
383d3f863a6STianshu Qiu 	msgs[0].buf = addr_buf;
384d3f863a6STianshu Qiu 	msgs[1].addr = client->addr;
385d3f863a6STianshu Qiu 	msgs[1].flags = I2C_M_RD;
386d3f863a6STianshu Qiu 	msgs[1].len = len;
387d3f863a6STianshu Qiu 	msgs[1].buf = &data_buf[sizeof(data_buf) - len];
388d3f863a6STianshu Qiu 
389d3f863a6STianshu Qiu 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
390d3f863a6STianshu Qiu 	if (ret != ARRAY_SIZE(msgs))
391d3f863a6STianshu Qiu 		return ret < 0 ? ret : -EIO;
392d3f863a6STianshu Qiu 
393d3f863a6STianshu Qiu 	*val = get_unaligned_be32(data_buf);
394d3f863a6STianshu Qiu 
395d3f863a6STianshu Qiu 	return 0;
396d3f863a6STianshu Qiu }
397d3f863a6STianshu Qiu 
ov9734_write_reg(struct ov9734 * ov9734,u16 reg,u16 len,u32 val)398d3f863a6STianshu Qiu static int ov9734_write_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 val)
399d3f863a6STianshu Qiu {
400d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
401d3f863a6STianshu Qiu 	u8 buf[6];
402d3f863a6STianshu Qiu 	int ret = 0;
403d3f863a6STianshu Qiu 
404d3f863a6STianshu Qiu 	if (len > 4)
405d3f863a6STianshu Qiu 		return -EINVAL;
406d3f863a6STianshu Qiu 
407d3f863a6STianshu Qiu 	put_unaligned_be16(reg, buf);
408d3f863a6STianshu Qiu 	put_unaligned_be32(val << 8 * (4 - len), buf + 2);
409d3f863a6STianshu Qiu 
410d3f863a6STianshu Qiu 	ret = i2c_master_send(client, buf, len + 2);
411d3f863a6STianshu Qiu 	if (ret != len + 2)
412d3f863a6STianshu Qiu 		return ret < 0 ? ret : -EIO;
413d3f863a6STianshu Qiu 
414d3f863a6STianshu Qiu 	return 0;
415d3f863a6STianshu Qiu }
416d3f863a6STianshu Qiu 
ov9734_write_reg_list(struct ov9734 * ov9734,const struct ov9734_reg_list * r_list)417d3f863a6STianshu Qiu static int ov9734_write_reg_list(struct ov9734 *ov9734,
418d3f863a6STianshu Qiu 				 const struct ov9734_reg_list *r_list)
419d3f863a6STianshu Qiu {
420d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
421d3f863a6STianshu Qiu 	unsigned int i;
422d3f863a6STianshu Qiu 	int ret;
423d3f863a6STianshu Qiu 
424d3f863a6STianshu Qiu 	for (i = 0; i < r_list->num_of_regs; i++) {
425d3f863a6STianshu Qiu 		ret = ov9734_write_reg(ov9734, r_list->regs[i].address, 1,
426d3f863a6STianshu Qiu 				       r_list->regs[i].val);
427d3f863a6STianshu Qiu 		if (ret) {
428d3f863a6STianshu Qiu 			dev_err_ratelimited(&client->dev,
429d3f863a6STianshu Qiu 					    "write reg 0x%4.4x return err = %d",
430d3f863a6STianshu Qiu 					    r_list->regs[i].address, ret);
431d3f863a6STianshu Qiu 			return ret;
432d3f863a6STianshu Qiu 		}
433d3f863a6STianshu Qiu 	}
434d3f863a6STianshu Qiu 
435d3f863a6STianshu Qiu 	return 0;
436d3f863a6STianshu Qiu }
437d3f863a6STianshu Qiu 
ov9734_update_digital_gain(struct ov9734 * ov9734,u32 d_gain)438d3f863a6STianshu Qiu static int ov9734_update_digital_gain(struct ov9734 *ov9734, u32 d_gain)
439d3f863a6STianshu Qiu {
440d3f863a6STianshu Qiu 	int ret;
441d3f863a6STianshu Qiu 
4420e2b8552SBingbu Cao 	ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1,
4430e2b8552SBingbu Cao 			       OV9734_GROUP_HOLD_START);
4440e2b8552SBingbu Cao 	if (ret)
4450e2b8552SBingbu Cao 		return ret;
4460e2b8552SBingbu Cao 
447d3f863a6STianshu Qiu 	ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_R_GAIN, 2, d_gain);
448d3f863a6STianshu Qiu 	if (ret)
449d3f863a6STianshu Qiu 		return ret;
450d3f863a6STianshu Qiu 
451d3f863a6STianshu Qiu 	ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_G_GAIN, 2, d_gain);
452d3f863a6STianshu Qiu 	if (ret)
453d3f863a6STianshu Qiu 		return ret;
454d3f863a6STianshu Qiu 
4550e2b8552SBingbu Cao 	ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_B_GAIN, 2, d_gain);
4560e2b8552SBingbu Cao 	if (ret)
4570e2b8552SBingbu Cao 		return ret;
4580e2b8552SBingbu Cao 
4590e2b8552SBingbu Cao 	ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1,
4600e2b8552SBingbu Cao 			       OV9734_GROUP_HOLD_END);
4610e2b8552SBingbu Cao 	if (ret)
4620e2b8552SBingbu Cao 		return ret;
4630e2b8552SBingbu Cao 
4640e2b8552SBingbu Cao 	ret = ov9734_write_reg(ov9734, OV9734_REG_GROUP_ACCESS, 1,
4650e2b8552SBingbu Cao 			       OV9734_GROUP_HOLD_LAUNCH);
4660e2b8552SBingbu Cao 	return ret;
467d3f863a6STianshu Qiu }
468d3f863a6STianshu Qiu 
ov9734_test_pattern(struct ov9734 * ov9734,u32 pattern)469d3f863a6STianshu Qiu static int ov9734_test_pattern(struct ov9734 *ov9734, u32 pattern)
470d3f863a6STianshu Qiu {
471d3f863a6STianshu Qiu 	if (pattern)
472d3f863a6STianshu Qiu 		pattern = (pattern - 1) << OV9734_TEST_PATTERN_BAR_SHIFT |
473d3f863a6STianshu Qiu 			OV9734_TEST_PATTERN_ENABLE;
474d3f863a6STianshu Qiu 
475d3f863a6STianshu Qiu 	return ov9734_write_reg(ov9734, OV9734_REG_TEST_PATTERN, 1, pattern);
476d3f863a6STianshu Qiu }
477d3f863a6STianshu Qiu 
ov9734_set_ctrl(struct v4l2_ctrl * ctrl)478d3f863a6STianshu Qiu static int ov9734_set_ctrl(struct v4l2_ctrl *ctrl)
479d3f863a6STianshu Qiu {
480d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = container_of(ctrl->handler,
481d3f863a6STianshu Qiu 					     struct ov9734, ctrl_handler);
482d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
483d3f863a6STianshu Qiu 	s64 exposure_max;
484d3f863a6STianshu Qiu 	int ret = 0;
485d3f863a6STianshu Qiu 
486d3f863a6STianshu Qiu 	/* Propagate change of current control to all related controls */
487d3f863a6STianshu Qiu 	if (ctrl->id == V4L2_CID_VBLANK) {
488d3f863a6STianshu Qiu 		/* Update max exposure while meeting expected vblanking */
489d3f863a6STianshu Qiu 		exposure_max = ov9734->cur_mode->height + ctrl->val -
490d3f863a6STianshu Qiu 			OV9734_EXPOSURE_MAX_MARGIN;
491d3f863a6STianshu Qiu 		__v4l2_ctrl_modify_range(ov9734->exposure,
492d3f863a6STianshu Qiu 					 ov9734->exposure->minimum,
493d3f863a6STianshu Qiu 					 exposure_max, ov9734->exposure->step,
494d3f863a6STianshu Qiu 					 exposure_max);
495d3f863a6STianshu Qiu 	}
496d3f863a6STianshu Qiu 
497d3f863a6STianshu Qiu 	/* V4L2 controls values will be applied only when power is already up */
498d3f863a6STianshu Qiu 	if (!pm_runtime_get_if_in_use(&client->dev))
499d3f863a6STianshu Qiu 		return 0;
500d3f863a6STianshu Qiu 
501d3f863a6STianshu Qiu 	switch (ctrl->id) {
502d3f863a6STianshu Qiu 	case V4L2_CID_ANALOGUE_GAIN:
503d3f863a6STianshu Qiu 		ret = ov9734_write_reg(ov9734, OV9734_REG_ANALOG_GAIN,
504d3f863a6STianshu Qiu 				       2, ctrl->val);
505d3f863a6STianshu Qiu 		break;
506d3f863a6STianshu Qiu 
507d3f863a6STianshu Qiu 	case V4L2_CID_DIGITAL_GAIN:
508d3f863a6STianshu Qiu 		ret = ov9734_update_digital_gain(ov9734, ctrl->val);
509d3f863a6STianshu Qiu 		break;
510d3f863a6STianshu Qiu 
511d3f863a6STianshu Qiu 	case V4L2_CID_EXPOSURE:
512d3f863a6STianshu Qiu 		/* 4 least significant bits of expsoure are fractional part */
513d3f863a6STianshu Qiu 		ret = ov9734_write_reg(ov9734, OV9734_REG_EXPOSURE,
514d3f863a6STianshu Qiu 				       3, ctrl->val << 4);
515d3f863a6STianshu Qiu 		break;
516d3f863a6STianshu Qiu 
517d3f863a6STianshu Qiu 	case V4L2_CID_VBLANK:
518d3f863a6STianshu Qiu 		ret = ov9734_write_reg(ov9734, OV9734_REG_VTS, 2,
519d3f863a6STianshu Qiu 				       ov9734->cur_mode->height + ctrl->val);
520d3f863a6STianshu Qiu 		break;
521d3f863a6STianshu Qiu 
522d3f863a6STianshu Qiu 	case V4L2_CID_TEST_PATTERN:
523d3f863a6STianshu Qiu 		ret = ov9734_test_pattern(ov9734, ctrl->val);
524d3f863a6STianshu Qiu 		break;
525d3f863a6STianshu Qiu 
526d3f863a6STianshu Qiu 	default:
527d3f863a6STianshu Qiu 		ret = -EINVAL;
528d3f863a6STianshu Qiu 		break;
529d3f863a6STianshu Qiu 	}
530d3f863a6STianshu Qiu 
531d3f863a6STianshu Qiu 	pm_runtime_put(&client->dev);
532d3f863a6STianshu Qiu 
533d3f863a6STianshu Qiu 	return ret;
534d3f863a6STianshu Qiu }
535d3f863a6STianshu Qiu 
536d3f863a6STianshu Qiu static const struct v4l2_ctrl_ops ov9734_ctrl_ops = {
537d3f863a6STianshu Qiu 	.s_ctrl = ov9734_set_ctrl,
538d3f863a6STianshu Qiu };
539d3f863a6STianshu Qiu 
ov9734_init_controls(struct ov9734 * ov9734)540d3f863a6STianshu Qiu static int ov9734_init_controls(struct ov9734 *ov9734)
541d3f863a6STianshu Qiu {
542d3f863a6STianshu Qiu 	struct v4l2_ctrl_handler *ctrl_hdlr;
543d3f863a6STianshu Qiu 	const struct ov9734_mode *cur_mode;
544d3f863a6STianshu Qiu 	s64 exposure_max, h_blank, pixel_rate;
545d3f863a6STianshu Qiu 	u32 vblank_min, vblank_max, vblank_default;
546d3f863a6STianshu Qiu 	int ret, size;
547d3f863a6STianshu Qiu 
548d3f863a6STianshu Qiu 	ctrl_hdlr = &ov9734->ctrl_handler;
549d3f863a6STianshu Qiu 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
550d3f863a6STianshu Qiu 	if (ret)
551d3f863a6STianshu Qiu 		return ret;
552d3f863a6STianshu Qiu 
553d3f863a6STianshu Qiu 	ctrl_hdlr->lock = &ov9734->mutex;
554d3f863a6STianshu Qiu 	cur_mode = ov9734->cur_mode;
555d3f863a6STianshu Qiu 	size = ARRAY_SIZE(link_freq_menu_items);
556d3f863a6STianshu Qiu 	ov9734->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov9734_ctrl_ops,
557d3f863a6STianshu Qiu 						   V4L2_CID_LINK_FREQ,
558d3f863a6STianshu Qiu 						   size - 1, 0,
559d3f863a6STianshu Qiu 						   link_freq_menu_items);
560d3f863a6STianshu Qiu 	if (ov9734->link_freq)
561d3f863a6STianshu Qiu 		ov9734->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
562d3f863a6STianshu Qiu 
563d3f863a6STianshu Qiu 	pixel_rate = to_pixel_rate(OV9734_LINK_FREQ_180MHZ_INDEX);
564d3f863a6STianshu Qiu 	ov9734->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
565d3f863a6STianshu Qiu 					       V4L2_CID_PIXEL_RATE, 0,
566d3f863a6STianshu Qiu 					       pixel_rate, 1, pixel_rate);
567d3f863a6STianshu Qiu 	vblank_min = cur_mode->vts_min - cur_mode->height;
568d3f863a6STianshu Qiu 	vblank_max = OV9734_VTS_MAX - cur_mode->height;
569d3f863a6STianshu Qiu 	vblank_default = cur_mode->vts_def - cur_mode->height;
570d3f863a6STianshu Qiu 	ov9734->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
571d3f863a6STianshu Qiu 					   V4L2_CID_VBLANK, vblank_min,
572d3f863a6STianshu Qiu 					   vblank_max, 1, vblank_default);
573d3f863a6STianshu Qiu 	h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
574d3f863a6STianshu Qiu 	h_blank -= cur_mode->width;
575d3f863a6STianshu Qiu 	ov9734->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
576d3f863a6STianshu Qiu 					   V4L2_CID_HBLANK, h_blank, h_blank, 1,
577d3f863a6STianshu Qiu 					   h_blank);
578d3f863a6STianshu Qiu 	if (ov9734->hblank)
579d3f863a6STianshu Qiu 		ov9734->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
580d3f863a6STianshu Qiu 
581d3f863a6STianshu Qiu 	v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
582d3f863a6STianshu Qiu 			  OV9734_ANAL_GAIN_MIN, OV9734_ANAL_GAIN_MAX,
583d3f863a6STianshu Qiu 			  OV9734_ANAL_GAIN_STEP, OV9734_ANAL_GAIN_MIN);
584d3f863a6STianshu Qiu 	v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
585d3f863a6STianshu Qiu 			  OV9734_DGTL_GAIN_MIN, OV9734_DGTL_GAIN_MAX,
586d3f863a6STianshu Qiu 			  OV9734_DGTL_GAIN_STEP, OV9734_DGTL_GAIN_DEFAULT);
587d3f863a6STianshu Qiu 	exposure_max = ov9734->cur_mode->vts_def - OV9734_EXPOSURE_MAX_MARGIN;
588d3f863a6STianshu Qiu 	ov9734->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
589d3f863a6STianshu Qiu 					     V4L2_CID_EXPOSURE,
590d3f863a6STianshu Qiu 					     OV9734_EXPOSURE_MIN, exposure_max,
591d3f863a6STianshu Qiu 					     OV9734_EXPOSURE_STEP,
592d3f863a6STianshu Qiu 					     exposure_max);
593d3f863a6STianshu Qiu 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov9734_ctrl_ops,
594d3f863a6STianshu Qiu 				     V4L2_CID_TEST_PATTERN,
595d3f863a6STianshu Qiu 				     ARRAY_SIZE(ov9734_test_pattern_menu) - 1,
596d3f863a6STianshu Qiu 				     0, 0, ov9734_test_pattern_menu);
597d3f863a6STianshu Qiu 	if (ctrl_hdlr->error)
598d3f863a6STianshu Qiu 		return ctrl_hdlr->error;
599d3f863a6STianshu Qiu 
600d3f863a6STianshu Qiu 	ov9734->sd.ctrl_handler = ctrl_hdlr;
601d3f863a6STianshu Qiu 
602d3f863a6STianshu Qiu 	return 0;
603d3f863a6STianshu Qiu }
604d3f863a6STianshu Qiu 
ov9734_update_pad_format(const struct ov9734_mode * mode,struct v4l2_mbus_framefmt * fmt)605d3f863a6STianshu Qiu static void ov9734_update_pad_format(const struct ov9734_mode *mode,
606d3f863a6STianshu Qiu 				     struct v4l2_mbus_framefmt *fmt)
607d3f863a6STianshu Qiu {
608d3f863a6STianshu Qiu 	fmt->width = mode->width;
609d3f863a6STianshu Qiu 	fmt->height = mode->height;
610d3f863a6STianshu Qiu 	fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
611d3f863a6STianshu Qiu 	fmt->field = V4L2_FIELD_NONE;
612d3f863a6STianshu Qiu }
613d3f863a6STianshu Qiu 
ov9734_start_streaming(struct ov9734 * ov9734)614d3f863a6STianshu Qiu static int ov9734_start_streaming(struct ov9734 *ov9734)
615d3f863a6STianshu Qiu {
616d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
617d3f863a6STianshu Qiu 	const struct ov9734_reg_list *reg_list;
618d3f863a6STianshu Qiu 	int link_freq_index, ret;
619d3f863a6STianshu Qiu 
620d3f863a6STianshu Qiu 	link_freq_index = ov9734->cur_mode->link_freq_index;
621d3f863a6STianshu Qiu 	reg_list = &link_freq_configs[link_freq_index].reg_list;
622d3f863a6STianshu Qiu 	ret = ov9734_write_reg_list(ov9734, reg_list);
623d3f863a6STianshu Qiu 	if (ret) {
624d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to set plls");
625d3f863a6STianshu Qiu 		return ret;
626d3f863a6STianshu Qiu 	}
627d3f863a6STianshu Qiu 
628d3f863a6STianshu Qiu 	reg_list = &ov9734->cur_mode->reg_list;
629d3f863a6STianshu Qiu 	ret = ov9734_write_reg_list(ov9734, reg_list);
630d3f863a6STianshu Qiu 	if (ret) {
631d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to set mode");
632d3f863a6STianshu Qiu 		return ret;
633d3f863a6STianshu Qiu 	}
634d3f863a6STianshu Qiu 
635d3f863a6STianshu Qiu 	ret = __v4l2_ctrl_handler_setup(ov9734->sd.ctrl_handler);
636d3f863a6STianshu Qiu 	if (ret)
637d3f863a6STianshu Qiu 		return ret;
638d3f863a6STianshu Qiu 
639d3f863a6STianshu Qiu 	ret = ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT,
640d3f863a6STianshu Qiu 			       1, OV9734_MODE_STREAMING);
641d3f863a6STianshu Qiu 	if (ret)
642d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to start stream");
643d3f863a6STianshu Qiu 
644d3f863a6STianshu Qiu 	return ret;
645d3f863a6STianshu Qiu }
646d3f863a6STianshu Qiu 
ov9734_stop_streaming(struct ov9734 * ov9734)647d3f863a6STianshu Qiu static void ov9734_stop_streaming(struct ov9734 *ov9734)
648d3f863a6STianshu Qiu {
649d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
650d3f863a6STianshu Qiu 
651d3f863a6STianshu Qiu 	if (ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT,
652d3f863a6STianshu Qiu 			     1, OV9734_MODE_STANDBY))
653d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to stop stream");
654d3f863a6STianshu Qiu }
655d3f863a6STianshu Qiu 
ov9734_set_stream(struct v4l2_subdev * sd,int enable)656d3f863a6STianshu Qiu static int ov9734_set_stream(struct v4l2_subdev *sd, int enable)
657d3f863a6STianshu Qiu {
658d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
659d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(sd);
660d3f863a6STianshu Qiu 	int ret = 0;
661d3f863a6STianshu Qiu 
662d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
6639677958dSBingbu Cao 	if (ov9734->streaming == enable) {
6649677958dSBingbu Cao 		mutex_unlock(&ov9734->mutex);
6659677958dSBingbu Cao 		return 0;
6669677958dSBingbu Cao 	}
6679677958dSBingbu Cao 
668d3f863a6STianshu Qiu 	if (enable) {
669279a085dSMauro Carvalho Chehab 		ret = pm_runtime_resume_and_get(&client->dev);
670d3f863a6STianshu Qiu 		if (ret < 0) {
671d3f863a6STianshu Qiu 			mutex_unlock(&ov9734->mutex);
672d3f863a6STianshu Qiu 			return ret;
673d3f863a6STianshu Qiu 		}
674d3f863a6STianshu Qiu 
675d3f863a6STianshu Qiu 		ret = ov9734_start_streaming(ov9734);
676d3f863a6STianshu Qiu 		if (ret) {
677d3f863a6STianshu Qiu 			enable = 0;
678d3f863a6STianshu Qiu 			ov9734_stop_streaming(ov9734);
679d3f863a6STianshu Qiu 			pm_runtime_put(&client->dev);
680d3f863a6STianshu Qiu 		}
681d3f863a6STianshu Qiu 	} else {
682d3f863a6STianshu Qiu 		ov9734_stop_streaming(ov9734);
683d3f863a6STianshu Qiu 		pm_runtime_put(&client->dev);
684d3f863a6STianshu Qiu 	}
685d3f863a6STianshu Qiu 
686d3f863a6STianshu Qiu 	ov9734->streaming = enable;
687d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
688d3f863a6STianshu Qiu 
689d3f863a6STianshu Qiu 	return ret;
690d3f863a6STianshu Qiu }
691d3f863a6STianshu Qiu 
ov9734_suspend(struct device * dev)692d3f863a6STianshu Qiu static int __maybe_unused ov9734_suspend(struct device *dev)
693d3f863a6STianshu Qiu {
694d3f863a6STianshu Qiu 	struct i2c_client *client = to_i2c_client(dev);
695d3f863a6STianshu Qiu 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
696d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
697d3f863a6STianshu Qiu 
698d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
699d3f863a6STianshu Qiu 	if (ov9734->streaming)
700d3f863a6STianshu Qiu 		ov9734_stop_streaming(ov9734);
701d3f863a6STianshu Qiu 
702d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
703d3f863a6STianshu Qiu 
704d3f863a6STianshu Qiu 	return 0;
705d3f863a6STianshu Qiu }
706d3f863a6STianshu Qiu 
ov9734_resume(struct device * dev)707d3f863a6STianshu Qiu static int __maybe_unused ov9734_resume(struct device *dev)
708d3f863a6STianshu Qiu {
709d3f863a6STianshu Qiu 	struct i2c_client *client = to_i2c_client(dev);
710d3f863a6STianshu Qiu 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
711d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
712d3f863a6STianshu Qiu 	int ret = 0;
713d3f863a6STianshu Qiu 
714d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
715d3f863a6STianshu Qiu 	if (!ov9734->streaming)
716d3f863a6STianshu Qiu 		goto exit;
717d3f863a6STianshu Qiu 
718d3f863a6STianshu Qiu 	ret = ov9734_start_streaming(ov9734);
719d3f863a6STianshu Qiu 	if (ret) {
720d3f863a6STianshu Qiu 		ov9734->streaming = false;
721d3f863a6STianshu Qiu 		ov9734_stop_streaming(ov9734);
722d3f863a6STianshu Qiu 	}
723d3f863a6STianshu Qiu 
724d3f863a6STianshu Qiu exit:
725d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
726d3f863a6STianshu Qiu 	return ret;
727d3f863a6STianshu Qiu }
728d3f863a6STianshu Qiu 
ov9734_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)729d3f863a6STianshu Qiu static int ov9734_set_format(struct v4l2_subdev *sd,
7300d346d2aSTomi Valkeinen 			     struct v4l2_subdev_state *sd_state,
731d3f863a6STianshu Qiu 			     struct v4l2_subdev_format *fmt)
732d3f863a6STianshu Qiu {
733d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
734d3f863a6STianshu Qiu 	const struct ov9734_mode *mode;
735d3f863a6STianshu Qiu 	s32 vblank_def, h_blank;
736d3f863a6STianshu Qiu 
737d3f863a6STianshu Qiu 	mode = v4l2_find_nearest_size(supported_modes,
738d3f863a6STianshu Qiu 				      ARRAY_SIZE(supported_modes), width,
739d3f863a6STianshu Qiu 				      height, fmt->format.width,
740d3f863a6STianshu Qiu 				      fmt->format.height);
741d3f863a6STianshu Qiu 
742d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
743d3f863a6STianshu Qiu 	ov9734_update_pad_format(mode, &fmt->format);
744d3f863a6STianshu Qiu 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
7450d346d2aSTomi Valkeinen 		*v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
746d3f863a6STianshu Qiu 	} else {
747d3f863a6STianshu Qiu 		ov9734->cur_mode = mode;
748d3f863a6STianshu Qiu 		__v4l2_ctrl_s_ctrl(ov9734->link_freq, mode->link_freq_index);
749d3f863a6STianshu Qiu 		__v4l2_ctrl_s_ctrl_int64(ov9734->pixel_rate,
750d3f863a6STianshu Qiu 					 to_pixel_rate(mode->link_freq_index));
751d3f863a6STianshu Qiu 
752d3f863a6STianshu Qiu 		/* Update limits and set FPS to default */
753d3f863a6STianshu Qiu 		vblank_def = mode->vts_def - mode->height;
754d3f863a6STianshu Qiu 		__v4l2_ctrl_modify_range(ov9734->vblank,
755d3f863a6STianshu Qiu 					 mode->vts_min - mode->height,
756d3f863a6STianshu Qiu 					 OV9734_VTS_MAX - mode->height, 1,
757d3f863a6STianshu Qiu 					 vblank_def);
758d3f863a6STianshu Qiu 		__v4l2_ctrl_s_ctrl(ov9734->vblank, vblank_def);
759d3f863a6STianshu Qiu 		h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
760d3f863a6STianshu Qiu 			mode->width;
761d3f863a6STianshu Qiu 		__v4l2_ctrl_modify_range(ov9734->hblank, h_blank, h_blank, 1,
762d3f863a6STianshu Qiu 					 h_blank);
763d3f863a6STianshu Qiu 	}
764d3f863a6STianshu Qiu 
765d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
766d3f863a6STianshu Qiu 
767d3f863a6STianshu Qiu 	return 0;
768d3f863a6STianshu Qiu }
769d3f863a6STianshu Qiu 
ov9734_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)770d3f863a6STianshu Qiu static int ov9734_get_format(struct v4l2_subdev *sd,
7710d346d2aSTomi Valkeinen 			     struct v4l2_subdev_state *sd_state,
772d3f863a6STianshu Qiu 			     struct v4l2_subdev_format *fmt)
773d3f863a6STianshu Qiu {
774d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
775d3f863a6STianshu Qiu 
776d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
777d3f863a6STianshu Qiu 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
7780d346d2aSTomi Valkeinen 		fmt->format = *v4l2_subdev_get_try_format(&ov9734->sd,
7790d346d2aSTomi Valkeinen 							  sd_state,
780d3f863a6STianshu Qiu 							  fmt->pad);
781d3f863a6STianshu Qiu 	else
782d3f863a6STianshu Qiu 		ov9734_update_pad_format(ov9734->cur_mode, &fmt->format);
783d3f863a6STianshu Qiu 
784d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
785d3f863a6STianshu Qiu 
786d3f863a6STianshu Qiu 	return 0;
787d3f863a6STianshu Qiu }
788d3f863a6STianshu Qiu 
ov9734_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)789d3f863a6STianshu Qiu static int ov9734_enum_mbus_code(struct v4l2_subdev *sd,
7900d346d2aSTomi Valkeinen 				 struct v4l2_subdev_state *sd_state,
791d3f863a6STianshu Qiu 				 struct v4l2_subdev_mbus_code_enum *code)
792d3f863a6STianshu Qiu {
793d3f863a6STianshu Qiu 	if (code->index > 0)
794d3f863a6STianshu Qiu 		return -EINVAL;
795d3f863a6STianshu Qiu 
796d3f863a6STianshu Qiu 	code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
797d3f863a6STianshu Qiu 
798d3f863a6STianshu Qiu 	return 0;
799d3f863a6STianshu Qiu }
800d3f863a6STianshu Qiu 
ov9734_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)801d3f863a6STianshu Qiu static int ov9734_enum_frame_size(struct v4l2_subdev *sd,
8020d346d2aSTomi Valkeinen 				  struct v4l2_subdev_state *sd_state,
803d3f863a6STianshu Qiu 				  struct v4l2_subdev_frame_size_enum *fse)
804d3f863a6STianshu Qiu {
805d3f863a6STianshu Qiu 	if (fse->index >= ARRAY_SIZE(supported_modes))
806d3f863a6STianshu Qiu 		return -EINVAL;
807d3f863a6STianshu Qiu 
808d3f863a6STianshu Qiu 	if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
809d3f863a6STianshu Qiu 		return -EINVAL;
810d3f863a6STianshu Qiu 
811d3f863a6STianshu Qiu 	fse->min_width = supported_modes[fse->index].width;
812d3f863a6STianshu Qiu 	fse->max_width = fse->min_width;
813d3f863a6STianshu Qiu 	fse->min_height = supported_modes[fse->index].height;
814d3f863a6STianshu Qiu 	fse->max_height = fse->min_height;
815d3f863a6STianshu Qiu 
816d3f863a6STianshu Qiu 	return 0;
817d3f863a6STianshu Qiu }
818d3f863a6STianshu Qiu 
ov9734_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)819d3f863a6STianshu Qiu static int ov9734_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
820d3f863a6STianshu Qiu {
821d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
822d3f863a6STianshu Qiu 
823d3f863a6STianshu Qiu 	mutex_lock(&ov9734->mutex);
824d3f863a6STianshu Qiu 	ov9734_update_pad_format(&supported_modes[0],
8250d346d2aSTomi Valkeinen 				 v4l2_subdev_get_try_format(sd, fh->state, 0));
826d3f863a6STianshu Qiu 	mutex_unlock(&ov9734->mutex);
827d3f863a6STianshu Qiu 
828d3f863a6STianshu Qiu 	return 0;
829d3f863a6STianshu Qiu }
830d3f863a6STianshu Qiu 
831d3f863a6STianshu Qiu static const struct v4l2_subdev_video_ops ov9734_video_ops = {
832d3f863a6STianshu Qiu 	.s_stream = ov9734_set_stream,
833d3f863a6STianshu Qiu };
834d3f863a6STianshu Qiu 
835d3f863a6STianshu Qiu static const struct v4l2_subdev_pad_ops ov9734_pad_ops = {
836d3f863a6STianshu Qiu 	.set_fmt = ov9734_set_format,
837d3f863a6STianshu Qiu 	.get_fmt = ov9734_get_format,
838d3f863a6STianshu Qiu 	.enum_mbus_code = ov9734_enum_mbus_code,
839d3f863a6STianshu Qiu 	.enum_frame_size = ov9734_enum_frame_size,
840d3f863a6STianshu Qiu };
841d3f863a6STianshu Qiu 
842d3f863a6STianshu Qiu static const struct v4l2_subdev_ops ov9734_subdev_ops = {
843d3f863a6STianshu Qiu 	.video = &ov9734_video_ops,
844d3f863a6STianshu Qiu 	.pad = &ov9734_pad_ops,
845d3f863a6STianshu Qiu };
846d3f863a6STianshu Qiu 
847d3f863a6STianshu Qiu static const struct media_entity_operations ov9734_subdev_entity_ops = {
848d3f863a6STianshu Qiu 	.link_validate = v4l2_subdev_link_validate,
849d3f863a6STianshu Qiu };
850d3f863a6STianshu Qiu 
851d3f863a6STianshu Qiu static const struct v4l2_subdev_internal_ops ov9734_internal_ops = {
852d3f863a6STianshu Qiu 	.open = ov9734_open,
853d3f863a6STianshu Qiu };
854d3f863a6STianshu Qiu 
ov9734_identify_module(struct ov9734 * ov9734)855d3f863a6STianshu Qiu static int ov9734_identify_module(struct ov9734 *ov9734)
856d3f863a6STianshu Qiu {
857d3f863a6STianshu Qiu 	struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
858d3f863a6STianshu Qiu 	int ret;
859d3f863a6STianshu Qiu 	u32 val;
860d3f863a6STianshu Qiu 
861d3f863a6STianshu Qiu 	ret = ov9734_read_reg(ov9734, OV9734_REG_CHIP_ID, 2, &val);
862d3f863a6STianshu Qiu 	if (ret)
863d3f863a6STianshu Qiu 		return ret;
864d3f863a6STianshu Qiu 
865d3f863a6STianshu Qiu 	if (val != OV9734_CHIP_ID) {
866d3f863a6STianshu Qiu 		dev_err(&client->dev, "chip id mismatch: %x!=%x",
867d3f863a6STianshu Qiu 			OV9734_CHIP_ID, val);
868d3f863a6STianshu Qiu 		return -ENXIO;
869d3f863a6STianshu Qiu 	}
870d3f863a6STianshu Qiu 
871d3f863a6STianshu Qiu 	return 0;
872d3f863a6STianshu Qiu }
873d3f863a6STianshu Qiu 
ov9734_check_hwcfg(struct device * dev)874d3f863a6STianshu Qiu static int ov9734_check_hwcfg(struct device *dev)
875d3f863a6STianshu Qiu {
876d3f863a6STianshu Qiu 	struct fwnode_handle *ep;
877d3f863a6STianshu Qiu 	struct fwnode_handle *fwnode = dev_fwnode(dev);
878d3f863a6STianshu Qiu 	struct v4l2_fwnode_endpoint bus_cfg = {
879d3f863a6STianshu Qiu 		.bus_type = V4L2_MBUS_CSI2_DPHY
880d3f863a6STianshu Qiu 	};
881d3f863a6STianshu Qiu 	u32 mclk;
882d3f863a6STianshu Qiu 	int ret;
883d3f863a6STianshu Qiu 	unsigned int i, j;
884d3f863a6STianshu Qiu 
885d3f863a6STianshu Qiu 	if (!fwnode)
886d3f863a6STianshu Qiu 		return -ENXIO;
887d3f863a6STianshu Qiu 
888d3f863a6STianshu Qiu 	ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
889d3f863a6STianshu Qiu 	if (ret)
890d3f863a6STianshu Qiu 		return ret;
891d3f863a6STianshu Qiu 
892d3f863a6STianshu Qiu 	if (mclk != OV9734_MCLK) {
893d3f863a6STianshu Qiu 		dev_err(dev, "external clock %d is not supported", mclk);
894d3f863a6STianshu Qiu 		return -EINVAL;
895d3f863a6STianshu Qiu 	}
896d3f863a6STianshu Qiu 
897d3f863a6STianshu Qiu 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
898d3f863a6STianshu Qiu 	if (!ep)
899d3f863a6STianshu Qiu 		return -ENXIO;
900d3f863a6STianshu Qiu 
901d3f863a6STianshu Qiu 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
902d3f863a6STianshu Qiu 	fwnode_handle_put(ep);
903d3f863a6STianshu Qiu 	if (ret)
904d3f863a6STianshu Qiu 		return ret;
905d3f863a6STianshu Qiu 
906d3f863a6STianshu Qiu 	if (!bus_cfg.nr_of_link_frequencies) {
907d3f863a6STianshu Qiu 		dev_err(dev, "no link frequencies defined");
908d3f863a6STianshu Qiu 		ret = -EINVAL;
909d3f863a6STianshu Qiu 		goto check_hwcfg_error;
910d3f863a6STianshu Qiu 	}
911d3f863a6STianshu Qiu 
912d3f863a6STianshu Qiu 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
913d3f863a6STianshu Qiu 		for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
914d3f863a6STianshu Qiu 			if (link_freq_menu_items[i] ==
915d3f863a6STianshu Qiu 			    bus_cfg.link_frequencies[j])
916d3f863a6STianshu Qiu 				break;
917d3f863a6STianshu Qiu 		}
918d3f863a6STianshu Qiu 
919d3f863a6STianshu Qiu 		if (j == bus_cfg.nr_of_link_frequencies) {
920d3f863a6STianshu Qiu 			dev_err(dev, "no link frequency %lld supported",
921d3f863a6STianshu Qiu 				link_freq_menu_items[i]);
922d3f863a6STianshu Qiu 			ret = -EINVAL;
923d3f863a6STianshu Qiu 			goto check_hwcfg_error;
924d3f863a6STianshu Qiu 		}
925d3f863a6STianshu Qiu 	}
926d3f863a6STianshu Qiu 
927d3f863a6STianshu Qiu check_hwcfg_error:
928d3f863a6STianshu Qiu 	v4l2_fwnode_endpoint_free(&bus_cfg);
929d3f863a6STianshu Qiu 
930d3f863a6STianshu Qiu 	return ret;
931d3f863a6STianshu Qiu }
932d3f863a6STianshu Qiu 
ov9734_remove(struct i2c_client * client)933ed5c2f5fSUwe Kleine-König static void ov9734_remove(struct i2c_client *client)
934d3f863a6STianshu Qiu {
935d3f863a6STianshu Qiu 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
936d3f863a6STianshu Qiu 	struct ov9734 *ov9734 = to_ov9734(sd);
937d3f863a6STianshu Qiu 
938d3f863a6STianshu Qiu 	v4l2_async_unregister_subdev(sd);
939d3f863a6STianshu Qiu 	media_entity_cleanup(&sd->entity);
940d3f863a6STianshu Qiu 	v4l2_ctrl_handler_free(sd->ctrl_handler);
941d3f863a6STianshu Qiu 	pm_runtime_disable(&client->dev);
942*92d25e02SBingbu Cao 	pm_runtime_set_suspended(&client->dev);
943d3f863a6STianshu Qiu 	mutex_destroy(&ov9734->mutex);
944d3f863a6STianshu Qiu }
945d3f863a6STianshu Qiu 
ov9734_probe(struct i2c_client * client)946d3f863a6STianshu Qiu static int ov9734_probe(struct i2c_client *client)
947d3f863a6STianshu Qiu {
948d3f863a6STianshu Qiu 	struct ov9734 *ov9734;
949d3f863a6STianshu Qiu 	int ret;
950d3f863a6STianshu Qiu 
951d3f863a6STianshu Qiu 	ret = ov9734_check_hwcfg(&client->dev);
952d3f863a6STianshu Qiu 	if (ret) {
953d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to check HW configuration: %d",
954d3f863a6STianshu Qiu 			ret);
955d3f863a6STianshu Qiu 		return ret;
956d3f863a6STianshu Qiu 	}
957d3f863a6STianshu Qiu 
958d3f863a6STianshu Qiu 	ov9734 = devm_kzalloc(&client->dev, sizeof(*ov9734), GFP_KERNEL);
959d3f863a6STianshu Qiu 	if (!ov9734)
960d3f863a6STianshu Qiu 		return -ENOMEM;
961d3f863a6STianshu Qiu 
962d3f863a6STianshu Qiu 	v4l2_i2c_subdev_init(&ov9734->sd, client, &ov9734_subdev_ops);
963d3f863a6STianshu Qiu 	ret = ov9734_identify_module(ov9734);
964d3f863a6STianshu Qiu 	if (ret) {
965d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to find sensor: %d", ret);
966d3f863a6STianshu Qiu 		return ret;
967d3f863a6STianshu Qiu 	}
968d3f863a6STianshu Qiu 
969d3f863a6STianshu Qiu 	mutex_init(&ov9734->mutex);
970d3f863a6STianshu Qiu 	ov9734->cur_mode = &supported_modes[0];
971d3f863a6STianshu Qiu 	ret = ov9734_init_controls(ov9734);
972d3f863a6STianshu Qiu 	if (ret) {
973d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to init controls: %d", ret);
974d3f863a6STianshu Qiu 		goto probe_error_v4l2_ctrl_handler_free;
975d3f863a6STianshu Qiu 	}
976d3f863a6STianshu Qiu 
977d3f863a6STianshu Qiu 	ov9734->sd.internal_ops = &ov9734_internal_ops;
978d3f863a6STianshu Qiu 	ov9734->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
979d3f863a6STianshu Qiu 	ov9734->sd.entity.ops = &ov9734_subdev_entity_ops;
980d3f863a6STianshu Qiu 	ov9734->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
981d3f863a6STianshu Qiu 	ov9734->pad.flags = MEDIA_PAD_FL_SOURCE;
982d3f863a6STianshu Qiu 	ret = media_entity_pads_init(&ov9734->sd.entity, 1, &ov9734->pad);
983d3f863a6STianshu Qiu 	if (ret) {
984d3f863a6STianshu Qiu 		dev_err(&client->dev, "failed to init entity pads: %d", ret);
985d3f863a6STianshu Qiu 		goto probe_error_v4l2_ctrl_handler_free;
986d3f863a6STianshu Qiu 	}
987d3f863a6STianshu Qiu 
988d3f863a6STianshu Qiu 	/*
989d3f863a6STianshu Qiu 	 * Device is already turned on by i2c-core with ACPI domain PM.
990d3f863a6STianshu Qiu 	 * Enable runtime PM and turn off the device.
991d3f863a6STianshu Qiu 	 */
992d3f863a6STianshu Qiu 	pm_runtime_set_active(&client->dev);
993d3f863a6STianshu Qiu 	pm_runtime_enable(&client->dev);
994d3f863a6STianshu Qiu 	pm_runtime_idle(&client->dev);
995d3f863a6STianshu Qiu 
996*92d25e02SBingbu Cao 	ret = v4l2_async_register_subdev_sensor(&ov9734->sd);
997*92d25e02SBingbu Cao 	if (ret < 0) {
998*92d25e02SBingbu Cao 		dev_err(&client->dev, "failed to register V4L2 subdev: %d",
999*92d25e02SBingbu Cao 			ret);
1000*92d25e02SBingbu Cao 		goto probe_error_media_entity_cleanup_pm;
1001*92d25e02SBingbu Cao 	}
1002*92d25e02SBingbu Cao 
1003d3f863a6STianshu Qiu 	return 0;
1004d3f863a6STianshu Qiu 
1005*92d25e02SBingbu Cao probe_error_media_entity_cleanup_pm:
1006*92d25e02SBingbu Cao 	pm_runtime_disable(&client->dev);
1007*92d25e02SBingbu Cao 	pm_runtime_set_suspended(&client->dev);
1008d3f863a6STianshu Qiu 	media_entity_cleanup(&ov9734->sd.entity);
1009d3f863a6STianshu Qiu 
1010d3f863a6STianshu Qiu probe_error_v4l2_ctrl_handler_free:
1011d3f863a6STianshu Qiu 	v4l2_ctrl_handler_free(ov9734->sd.ctrl_handler);
1012d3f863a6STianshu Qiu 	mutex_destroy(&ov9734->mutex);
1013d3f863a6STianshu Qiu 
1014d3f863a6STianshu Qiu 	return ret;
1015d3f863a6STianshu Qiu }
1016d3f863a6STianshu Qiu 
1017d3f863a6STianshu Qiu static const struct dev_pm_ops ov9734_pm_ops = {
1018d3f863a6STianshu Qiu 	SET_SYSTEM_SLEEP_PM_OPS(ov9734_suspend, ov9734_resume)
1019d3f863a6STianshu Qiu };
1020d3f863a6STianshu Qiu 
1021d3f863a6STianshu Qiu static const struct acpi_device_id ov9734_acpi_ids[] = {
1022d3f863a6STianshu Qiu 	{ "OVTI9734", },
1023d3f863a6STianshu Qiu 	{}
1024d3f863a6STianshu Qiu };
1025d3f863a6STianshu Qiu 
1026d3f863a6STianshu Qiu MODULE_DEVICE_TABLE(acpi, ov9734_acpi_ids);
1027d3f863a6STianshu Qiu 
1028d3f863a6STianshu Qiu static struct i2c_driver ov9734_i2c_driver = {
1029d3f863a6STianshu Qiu 	.driver = {
1030d3f863a6STianshu Qiu 		.name = "ov9734",
1031d3f863a6STianshu Qiu 		.pm = &ov9734_pm_ops,
1032d3f863a6STianshu Qiu 		.acpi_match_table = ov9734_acpi_ids,
1033d3f863a6STianshu Qiu 	},
1034aaeb31c0SUwe Kleine-König 	.probe = ov9734_probe,
1035d3f863a6STianshu Qiu 	.remove = ov9734_remove,
1036d3f863a6STianshu Qiu };
1037d3f863a6STianshu Qiu 
1038d3f863a6STianshu Qiu module_i2c_driver(ov9734_i2c_driver);
1039d3f863a6STianshu Qiu 
1040d3f863a6STianshu Qiu MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1041d3f863a6STianshu Qiu MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1042d3f863a6STianshu Qiu MODULE_DESCRIPTION("OmniVision OV9734 sensor driver");
1043d3f863a6STianshu Qiu MODULE_LICENSE("GPL v2");
1044