1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <media/media-entity.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-subdev.h> 24 25 #define IMX290_REG_SIZE_SHIFT 16 26 #define IMX290_REG_ADDR_MASK 0xffff 27 #define IMX290_REG_8BIT(n) ((1U << IMX290_REG_SIZE_SHIFT) | (n)) 28 #define IMX290_REG_16BIT(n) ((2U << IMX290_REG_SIZE_SHIFT) | (n)) 29 #define IMX290_REG_24BIT(n) ((3U << IMX290_REG_SIZE_SHIFT) | (n)) 30 31 #define IMX290_STANDBY IMX290_REG_8BIT(0x3000) 32 #define IMX290_REGHOLD IMX290_REG_8BIT(0x3001) 33 #define IMX290_XMSTA IMX290_REG_8BIT(0x3002) 34 #define IMX290_ADBIT IMX290_REG_8BIT(0x3005) 35 #define IMX290_ADBIT_10BIT (0 << 0) 36 #define IMX290_ADBIT_12BIT (1 << 0) 37 #define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007) 38 #define IMX290_VREVERSE BIT(0) 39 #define IMX290_HREVERSE BIT(1) 40 #define IMX290_WINMODE_1080P (0 << 4) 41 #define IMX290_WINMODE_720P (1 << 4) 42 #define IMX290_WINMODE_CROP (4 << 4) 43 #define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009) 44 #define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a) 45 #define IMX290_GAIN IMX290_REG_8BIT(0x3014) 46 #define IMX290_VMAX IMX290_REG_24BIT(0x3018) 47 #define IMX290_HMAX IMX290_REG_16BIT(0x301c) 48 #define IMX290_SHS1 IMX290_REG_24BIT(0x3020) 49 #define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a) 50 #define IMX290_WINPV IMX290_REG_16BIT(0x303c) 51 #define IMX290_WINWV IMX290_REG_16BIT(0x303e) 52 #define IMX290_WINPH IMX290_REG_16BIT(0x3040) 53 #define IMX290_WINWH IMX290_REG_16BIT(0x3042) 54 #define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046) 55 #define IMX290_ODBIT_10BIT (0 << 0) 56 #define IMX290_ODBIT_12BIT (1 << 0) 57 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 58 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 59 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 60 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 61 #define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b) 62 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 63 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 64 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 65 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 66 #define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c) 67 #define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d) 68 #define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e) 69 #define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f) 70 #define IMX290_PGCTRL IMX290_REG_8BIT(0x308c) 71 #define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129) 72 #define IMX290_ADBIT1_10BIT 0x1d 73 #define IMX290_ADBIT1_12BIT 0x00 74 #define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e) 75 #define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164) 76 #define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c) 77 #define IMX290_ADBIT2_10BIT 0x12 78 #define IMX290_ADBIT2_12BIT 0x00 79 #define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a) 80 #define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec) 81 #define IMX290_ADBIT3_10BIT 0x37 82 #define IMX290_ADBIT3_12BIT 0x0e 83 #define IMX290_REPETITION IMX290_REG_8BIT(0x3405) 84 #define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407) 85 #define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414) 86 #define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418) 87 #define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441) 88 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 89 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 90 #define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443) 91 #define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444) 92 #define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446) 93 #define IMX290_THSZERO IMX290_REG_16BIT(0x3448) 94 #define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a) 95 #define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c) 96 #define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e) 97 #define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450) 98 #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452) 99 #define IMX290_TLPX IMX290_REG_16BIT(0x3454) 100 #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472) 101 102 #define IMX290_PGCTRL_REGEN BIT(0) 103 #define IMX290_PGCTRL_THRU BIT(1) 104 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 105 106 #define IMX290_VMAX_DEFAULT 1125 107 108 109 /* 110 * The IMX290 pixel array is organized as follows: 111 * 112 * +------------------------------------+ 113 * | Optical Black | } Vertical effective optical black (10) 114 * +---+------------------------------------+---+ 115 * | | | | } Effective top margin (8) 116 * | | +----------------------------+ | | \ 117 * | | | | | | | 118 * | | | | | | | 119 * | | | | | | | 120 * | | | Recording Pixel Area | | | | Recommended height (1080) 121 * | | | | | | | 122 * | | | | | | | 123 * | | | | | | | 124 * | | +----------------------------+ | | / 125 * | | | | } Effective bottom margin (9) 126 * +---+------------------------------------+---+ 127 * <-> <-> <--------------------------> <-> <-> 128 * \---- Ignored right margin (4) 129 * \-------- Effective right margin (9) 130 * \------------------------- Recommended width (1920) 131 * \----------------------------------------- Effective left margin (8) 132 * \--------------------------------------------- Ignored left margin (4) 133 * 134 * The optical black lines are output over CSI-2 with a separate data type. 135 * 136 * The pixel array is meant to have 1920x1080 usable pixels after image 137 * processing in an ISP. It has 8 (9) extra active pixels usable for color 138 * processing in the ISP on the top and left (bottom and right) sides of the 139 * image. In addition, 4 additional pixels are present on the left and right 140 * sides of the image, documented as "ignored area". 141 * 142 * As far as is understood, all pixels of the pixel array (ignored area, color 143 * processing margins and recording area) can be output by the sensor. 144 */ 145 146 #define IMX290_PIXEL_ARRAY_WIDTH 1945 147 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 148 #define IMX920_PIXEL_ARRAY_MARGIN_LEFT 12 149 #define IMX920_PIXEL_ARRAY_MARGIN_RIGHT 13 150 #define IMX920_PIXEL_ARRAY_MARGIN_TOP 8 151 #define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM 9 152 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 153 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 154 155 static const char * const imx290_supply_name[] = { 156 "vdda", 157 "vddd", 158 "vdddo", 159 }; 160 161 #define IMX290_NUM_SUPPLIES ARRAY_SIZE(imx290_supply_name) 162 163 struct imx290_regval { 164 u32 reg; 165 u32 val; 166 }; 167 168 struct imx290_mode { 169 u32 width; 170 u32 height; 171 u32 hmax; 172 u8 link_freq_index; 173 174 const struct imx290_regval *data; 175 u32 data_size; 176 }; 177 178 struct imx290 { 179 struct device *dev; 180 struct clk *xclk; 181 struct regmap *regmap; 182 u8 nlanes; 183 u8 bpp; 184 185 struct v4l2_subdev sd; 186 struct media_pad pad; 187 struct v4l2_mbus_framefmt current_format; 188 const struct imx290_mode *current_mode; 189 190 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 191 struct gpio_desc *rst_gpio; 192 193 struct v4l2_ctrl_handler ctrls; 194 struct v4l2_ctrl *link_freq; 195 struct v4l2_ctrl *pixel_rate; 196 struct v4l2_ctrl *hblank; 197 struct v4l2_ctrl *vblank; 198 199 struct mutex lock; 200 }; 201 202 struct imx290_pixfmt { 203 u32 code; 204 u8 bpp; 205 }; 206 207 static const struct imx290_pixfmt imx290_formats[] = { 208 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 209 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 210 }; 211 212 static const struct regmap_config imx290_regmap_config = { 213 .reg_bits = 16, 214 .val_bits = 8, 215 }; 216 217 static const char * const imx290_test_pattern_menu[] = { 218 "Disabled", 219 "Sequence Pattern 1", 220 "Horizontal Color-bar Chart", 221 "Vertical Color-bar Chart", 222 "Sequence Pattern 2", 223 "Gradation Pattern 1", 224 "Gradation Pattern 2", 225 "000/555h Toggle Pattern", 226 }; 227 228 static const struct imx290_regval imx290_global_init_settings[] = { 229 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 230 { IMX290_VMAX, IMX290_VMAX_DEFAULT }, 231 { IMX290_EXTCK_FREQ, 0x2520 }, 232 { IMX290_WINWV_OB, 12 }, 233 { IMX290_WINPH, 0 }, 234 { IMX290_WINPV, 0 }, 235 { IMX290_WINWH, 1948 }, 236 { IMX290_WINWV, 1097 }, 237 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 238 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 239 { IMX290_REG_8BIT(0x300f), 0x00 }, 240 { IMX290_REG_8BIT(0x3010), 0x21 }, 241 { IMX290_REG_8BIT(0x3012), 0x64 }, 242 { IMX290_REG_8BIT(0x3013), 0x00 }, 243 { IMX290_REG_8BIT(0x3016), 0x09 }, 244 { IMX290_REG_8BIT(0x3070), 0x02 }, 245 { IMX290_REG_8BIT(0x3071), 0x11 }, 246 { IMX290_REG_8BIT(0x309b), 0x10 }, 247 { IMX290_REG_8BIT(0x309c), 0x22 }, 248 { IMX290_REG_8BIT(0x30a2), 0x02 }, 249 { IMX290_REG_8BIT(0x30a6), 0x20 }, 250 { IMX290_REG_8BIT(0x30a8), 0x20 }, 251 { IMX290_REG_8BIT(0x30aa), 0x20 }, 252 { IMX290_REG_8BIT(0x30ac), 0x20 }, 253 { IMX290_REG_8BIT(0x30b0), 0x43 }, 254 { IMX290_REG_8BIT(0x3119), 0x9e }, 255 { IMX290_REG_8BIT(0x311c), 0x1e }, 256 { IMX290_REG_8BIT(0x311e), 0x08 }, 257 { IMX290_REG_8BIT(0x3128), 0x05 }, 258 { IMX290_REG_8BIT(0x313d), 0x83 }, 259 { IMX290_REG_8BIT(0x3150), 0x03 }, 260 { IMX290_REG_8BIT(0x317e), 0x00 }, 261 { IMX290_REG_8BIT(0x32b8), 0x50 }, 262 { IMX290_REG_8BIT(0x32b9), 0x10 }, 263 { IMX290_REG_8BIT(0x32ba), 0x00 }, 264 { IMX290_REG_8BIT(0x32bb), 0x04 }, 265 { IMX290_REG_8BIT(0x32c8), 0x50 }, 266 { IMX290_REG_8BIT(0x32c9), 0x10 }, 267 { IMX290_REG_8BIT(0x32ca), 0x00 }, 268 { IMX290_REG_8BIT(0x32cb), 0x04 }, 269 { IMX290_REG_8BIT(0x332c), 0xd3 }, 270 { IMX290_REG_8BIT(0x332d), 0x10 }, 271 { IMX290_REG_8BIT(0x332e), 0x0d }, 272 { IMX290_REG_8BIT(0x3358), 0x06 }, 273 { IMX290_REG_8BIT(0x3359), 0xe1 }, 274 { IMX290_REG_8BIT(0x335a), 0x11 }, 275 { IMX290_REG_8BIT(0x3360), 0x1e }, 276 { IMX290_REG_8BIT(0x3361), 0x61 }, 277 { IMX290_REG_8BIT(0x3362), 0x10 }, 278 { IMX290_REG_8BIT(0x33b0), 0x50 }, 279 { IMX290_REG_8BIT(0x33b2), 0x1a }, 280 { IMX290_REG_8BIT(0x33b3), 0x04 }, 281 { IMX290_REG_8BIT(0x3480), 0x49 }, 282 }; 283 284 static const struct imx290_regval imx290_1080p_settings[] = { 285 /* mode settings */ 286 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 287 { IMX290_WINWV_OB, 12 }, 288 { IMX290_OPB_SIZE_V, 10 }, 289 { IMX290_X_OUT_SIZE, 1920 }, 290 { IMX290_Y_OUT_SIZE, 1080 }, 291 { IMX290_INCKSEL1, 0x18 }, 292 { IMX290_INCKSEL2, 0x03 }, 293 { IMX290_INCKSEL3, 0x20 }, 294 { IMX290_INCKSEL4, 0x01 }, 295 { IMX290_INCKSEL5, 0x1a }, 296 { IMX290_INCKSEL6, 0x1a }, 297 /* data rate settings */ 298 { IMX290_REPETITION, 0x10 }, 299 { IMX290_TCLKPOST, 87 }, 300 { IMX290_THSZERO, 55 }, 301 { IMX290_THSPREPARE, 31 }, 302 { IMX290_TCLKTRAIL, 31 }, 303 { IMX290_THSTRAIL, 31 }, 304 { IMX290_TCLKZERO, 119 }, 305 { IMX290_TCLKPREPARE, 31 }, 306 { IMX290_TLPX, 23 }, 307 }; 308 309 static const struct imx290_regval imx290_720p_settings[] = { 310 /* mode settings */ 311 { IMX290_CTRL_07, IMX290_WINMODE_720P }, 312 { IMX290_WINWV_OB, 6 }, 313 { IMX290_OPB_SIZE_V, 4 }, 314 { IMX290_X_OUT_SIZE, 1280 }, 315 { IMX290_Y_OUT_SIZE, 720 }, 316 { IMX290_INCKSEL1, 0x20 }, 317 { IMX290_INCKSEL2, 0x00 }, 318 { IMX290_INCKSEL3, 0x20 }, 319 { IMX290_INCKSEL4, 0x01 }, 320 { IMX290_INCKSEL5, 0x1a }, 321 { IMX290_INCKSEL6, 0x1a }, 322 /* data rate settings */ 323 { IMX290_REPETITION, 0x10 }, 324 { IMX290_TCLKPOST, 79 }, 325 { IMX290_THSZERO, 47 }, 326 { IMX290_THSPREPARE, 23 }, 327 { IMX290_TCLKTRAIL, 23 }, 328 { IMX290_THSTRAIL, 23 }, 329 { IMX290_TCLKZERO, 87 }, 330 { IMX290_TCLKPREPARE, 23 }, 331 { IMX290_TLPX, 23 }, 332 }; 333 334 static const struct imx290_regval imx290_10bit_settings[] = { 335 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 336 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 337 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 338 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 339 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 340 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 341 { IMX290_BLKLEVEL, 60 }, 342 }; 343 344 static const struct imx290_regval imx290_12bit_settings[] = { 345 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 346 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 347 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 348 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 349 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 350 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 351 { IMX290_BLKLEVEL, 240 }, 352 }; 353 354 /* supported link frequencies */ 355 #define FREQ_INDEX_1080P 0 356 #define FREQ_INDEX_720P 1 357 static const s64 imx290_link_freq_2lanes[] = { 358 [FREQ_INDEX_1080P] = 445500000, 359 [FREQ_INDEX_720P] = 297000000, 360 }; 361 static const s64 imx290_link_freq_4lanes[] = { 362 [FREQ_INDEX_1080P] = 222750000, 363 [FREQ_INDEX_720P] = 148500000, 364 }; 365 366 /* 367 * In this function and in the similar ones below We rely on imx290_probe() 368 * to ensure that nlanes is either 2 or 4. 369 */ 370 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 371 { 372 if (imx290->nlanes == 2) 373 return imx290_link_freq_2lanes; 374 else 375 return imx290_link_freq_4lanes; 376 } 377 378 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 379 { 380 if (imx290->nlanes == 2) 381 return ARRAY_SIZE(imx290_link_freq_2lanes); 382 else 383 return ARRAY_SIZE(imx290_link_freq_4lanes); 384 } 385 386 /* Mode configs */ 387 static const struct imx290_mode imx290_modes_2lanes[] = { 388 { 389 .width = 1920, 390 .height = 1080, 391 .hmax = 4400, 392 .link_freq_index = FREQ_INDEX_1080P, 393 .data = imx290_1080p_settings, 394 .data_size = ARRAY_SIZE(imx290_1080p_settings), 395 }, 396 { 397 .width = 1280, 398 .height = 720, 399 .hmax = 6600, 400 .link_freq_index = FREQ_INDEX_720P, 401 .data = imx290_720p_settings, 402 .data_size = ARRAY_SIZE(imx290_720p_settings), 403 }, 404 }; 405 406 static const struct imx290_mode imx290_modes_4lanes[] = { 407 { 408 .width = 1920, 409 .height = 1080, 410 .hmax = 2200, 411 .link_freq_index = FREQ_INDEX_1080P, 412 .data = imx290_1080p_settings, 413 .data_size = ARRAY_SIZE(imx290_1080p_settings), 414 }, 415 { 416 .width = 1280, 417 .height = 720, 418 .hmax = 3300, 419 .link_freq_index = FREQ_INDEX_720P, 420 .data = imx290_720p_settings, 421 .data_size = ARRAY_SIZE(imx290_720p_settings), 422 }, 423 }; 424 425 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 426 { 427 if (imx290->nlanes == 2) 428 return imx290_modes_2lanes; 429 else 430 return imx290_modes_4lanes; 431 } 432 433 static inline int imx290_modes_num(const struct imx290 *imx290) 434 { 435 if (imx290->nlanes == 2) 436 return ARRAY_SIZE(imx290_modes_2lanes); 437 else 438 return ARRAY_SIZE(imx290_modes_4lanes); 439 } 440 441 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 442 { 443 return container_of(_sd, struct imx290, sd); 444 } 445 446 static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value) 447 { 448 u8 data[3] = { 0, 0, 0 }; 449 int ret; 450 451 ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 452 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 453 if (ret < 0) { 454 dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n", 455 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 456 addr & IMX290_REG_ADDR_MASK, ret); 457 return ret; 458 } 459 460 *value = (data[2] << 16) | (data[1] << 8) | data[0]; 461 return 0; 462 } 463 464 static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err) 465 { 466 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 }; 467 int ret; 468 469 if (err && *err) 470 return *err; 471 472 ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 473 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 474 if (ret < 0) { 475 dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n", 476 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 477 addr & IMX290_REG_ADDR_MASK, ret); 478 if (err) 479 *err = ret; 480 } 481 482 return ret; 483 } 484 485 static int imx290_set_register_array(struct imx290 *imx290, 486 const struct imx290_regval *settings, 487 unsigned int num_settings) 488 { 489 unsigned int i; 490 int ret; 491 492 for (i = 0; i < num_settings; ++i, ++settings) { 493 ret = imx290_write(imx290, settings->reg, settings->val, NULL); 494 if (ret < 0) 495 return ret; 496 } 497 498 /* Provide 10ms settle time */ 499 usleep_range(10000, 11000); 500 501 return 0; 502 } 503 504 /* Stop streaming */ 505 static int imx290_stop_streaming(struct imx290 *imx290) 506 { 507 int ret = 0; 508 509 imx290_write(imx290, IMX290_STANDBY, 0x01, &ret); 510 511 msleep(30); 512 513 return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret); 514 } 515 516 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 517 { 518 struct imx290 *imx290 = container_of(ctrl->handler, 519 struct imx290, ctrls); 520 int ret = 0; 521 522 /* V4L2 controls values will be applied only when power is already up */ 523 if (!pm_runtime_get_if_in_use(imx290->dev)) 524 return 0; 525 526 switch (ctrl->id) { 527 case V4L2_CID_ANALOGUE_GAIN: 528 ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL); 529 break; 530 531 case V4L2_CID_EXPOSURE: 532 ret = imx290_write(imx290, IMX290_SHS1, 533 IMX290_VMAX_DEFAULT - ctrl->val - 1, NULL); 534 break; 535 536 case V4L2_CID_TEST_PATTERN: 537 if (ctrl->val) { 538 imx290_write(imx290, IMX290_BLKLEVEL, 0, &ret); 539 usleep_range(10000, 11000); 540 imx290_write(imx290, IMX290_PGCTRL, 541 (u8)(IMX290_PGCTRL_REGEN | 542 IMX290_PGCTRL_THRU | 543 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 544 } else { 545 imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret); 546 usleep_range(10000, 11000); 547 if (imx290->bpp == 10) 548 imx290_write(imx290, IMX290_BLKLEVEL, 0x3c, 549 &ret); 550 else /* 12 bits per pixel */ 551 imx290_write(imx290, IMX290_BLKLEVEL, 0xf0, 552 &ret); 553 } 554 break; 555 default: 556 ret = -EINVAL; 557 break; 558 } 559 560 pm_runtime_put(imx290->dev); 561 562 return ret; 563 } 564 565 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 566 .s_ctrl = imx290_set_ctrl, 567 }; 568 569 static struct v4l2_mbus_framefmt * 570 imx290_get_pad_format(struct imx290 *imx290, struct v4l2_subdev_state *state, 571 u32 which) 572 { 573 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 574 return &imx290->current_format; 575 else 576 return v4l2_subdev_get_try_format(&imx290->sd, state, 0); 577 } 578 579 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 580 struct v4l2_subdev_state *sd_state, 581 struct v4l2_subdev_mbus_code_enum *code) 582 { 583 if (code->index >= ARRAY_SIZE(imx290_formats)) 584 return -EINVAL; 585 586 code->code = imx290_formats[code->index].code; 587 588 return 0; 589 } 590 591 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 592 struct v4l2_subdev_state *sd_state, 593 struct v4l2_subdev_frame_size_enum *fse) 594 { 595 const struct imx290 *imx290 = to_imx290(sd); 596 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 597 598 if ((fse->code != imx290_formats[0].code) && 599 (fse->code != imx290_formats[1].code)) 600 return -EINVAL; 601 602 if (fse->index >= imx290_modes_num(imx290)) 603 return -EINVAL; 604 605 fse->min_width = imx290_modes[fse->index].width; 606 fse->max_width = imx290_modes[fse->index].width; 607 fse->min_height = imx290_modes[fse->index].height; 608 fse->max_height = imx290_modes[fse->index].height; 609 610 return 0; 611 } 612 613 static int imx290_get_fmt(struct v4l2_subdev *sd, 614 struct v4l2_subdev_state *sd_state, 615 struct v4l2_subdev_format *fmt) 616 { 617 struct imx290 *imx290 = to_imx290(sd); 618 struct v4l2_mbus_framefmt *framefmt; 619 620 mutex_lock(&imx290->lock); 621 622 framefmt = imx290_get_pad_format(imx290, sd_state, fmt->which); 623 fmt->format = *framefmt; 624 625 mutex_unlock(&imx290->lock); 626 627 return 0; 628 } 629 630 static inline u8 imx290_get_link_freq_index(struct imx290 *imx290) 631 { 632 return imx290->current_mode->link_freq_index; 633 } 634 635 static s64 imx290_get_link_freq(struct imx290 *imx290) 636 { 637 u8 index = imx290_get_link_freq_index(imx290); 638 639 return *(imx290_link_freqs_ptr(imx290) + index); 640 } 641 642 static u64 imx290_calc_pixel_rate(struct imx290 *imx290) 643 { 644 s64 link_freq = imx290_get_link_freq(imx290); 645 u8 nlanes = imx290->nlanes; 646 u64 pixel_rate; 647 648 /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 649 pixel_rate = link_freq * 2 * nlanes; 650 do_div(pixel_rate, imx290->bpp); 651 return pixel_rate; 652 } 653 654 static int imx290_set_fmt(struct v4l2_subdev *sd, 655 struct v4l2_subdev_state *sd_state, 656 struct v4l2_subdev_format *fmt) 657 { 658 struct imx290 *imx290 = to_imx290(sd); 659 const struct imx290_mode *mode; 660 struct v4l2_mbus_framefmt *format; 661 unsigned int i; 662 663 mutex_lock(&imx290->lock); 664 665 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 666 imx290_modes_num(imx290), width, height, 667 fmt->format.width, fmt->format.height); 668 669 fmt->format.width = mode->width; 670 fmt->format.height = mode->height; 671 672 for (i = 0; i < ARRAY_SIZE(imx290_formats); i++) 673 if (imx290_formats[i].code == fmt->format.code) 674 break; 675 676 if (i >= ARRAY_SIZE(imx290_formats)) 677 i = 0; 678 679 fmt->format.code = imx290_formats[i].code; 680 fmt->format.field = V4L2_FIELD_NONE; 681 682 format = imx290_get_pad_format(imx290, sd_state, fmt->which); 683 684 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 685 imx290->current_mode = mode; 686 imx290->bpp = imx290_formats[i].bpp; 687 688 if (imx290->link_freq) 689 __v4l2_ctrl_s_ctrl(imx290->link_freq, 690 imx290_get_link_freq_index(imx290)); 691 if (imx290->pixel_rate) 692 __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate, 693 imx290_calc_pixel_rate(imx290)); 694 695 if (imx290->hblank) { 696 unsigned int hblank = mode->hmax - mode->width; 697 698 __v4l2_ctrl_modify_range(imx290->hblank, hblank, hblank, 699 1, hblank); 700 } 701 702 if (imx290->vblank) { 703 unsigned int vblank = IMX290_VMAX_DEFAULT - mode->height; 704 705 __v4l2_ctrl_modify_range(imx290->vblank, vblank, vblank, 706 1, vblank); 707 } 708 } 709 710 *format = fmt->format; 711 712 mutex_unlock(&imx290->lock); 713 714 return 0; 715 } 716 717 static int imx290_get_selection(struct v4l2_subdev *sd, 718 struct v4l2_subdev_state *sd_state, 719 struct v4l2_subdev_selection *sel) 720 { 721 struct imx290 *imx290 = to_imx290(sd); 722 struct v4l2_mbus_framefmt *format; 723 724 switch (sel->target) { 725 case V4L2_SEL_TGT_CROP: { 726 format = imx290_get_pad_format(imx290, sd_state, sel->which); 727 728 mutex_lock(&imx290->lock); 729 730 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP 731 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2; 732 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT 733 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2; 734 sel->r.width = format->width; 735 sel->r.height = format->height; 736 737 mutex_unlock(&imx290->lock); 738 return 0; 739 } 740 741 case V4L2_SEL_TGT_NATIVE_SIZE: 742 case V4L2_SEL_TGT_CROP_BOUNDS: 743 sel->r.top = 0; 744 sel->r.left = 0; 745 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 746 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 747 748 return 0; 749 750 case V4L2_SEL_TGT_CROP_DEFAULT: 751 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP; 752 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT; 753 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 754 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 755 756 return 0; 757 758 default: 759 return -EINVAL; 760 } 761 } 762 763 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 764 struct v4l2_subdev_state *sd_state) 765 { 766 struct v4l2_subdev_format fmt = { 0 }; 767 768 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 769 fmt.format.width = 1920; 770 fmt.format.height = 1080; 771 772 imx290_set_fmt(subdev, sd_state, &fmt); 773 774 return 0; 775 } 776 777 static int imx290_write_current_format(struct imx290 *imx290) 778 { 779 int ret; 780 781 switch (imx290->current_format.code) { 782 case MEDIA_BUS_FMT_SRGGB10_1X10: 783 ret = imx290_set_register_array(imx290, imx290_10bit_settings, 784 ARRAY_SIZE( 785 imx290_10bit_settings)); 786 if (ret < 0) { 787 dev_err(imx290->dev, "Could not set format registers\n"); 788 return ret; 789 } 790 break; 791 case MEDIA_BUS_FMT_SRGGB12_1X12: 792 ret = imx290_set_register_array(imx290, imx290_12bit_settings, 793 ARRAY_SIZE( 794 imx290_12bit_settings)); 795 if (ret < 0) { 796 dev_err(imx290->dev, "Could not set format registers\n"); 797 return ret; 798 } 799 break; 800 default: 801 dev_err(imx290->dev, "Unknown pixel format\n"); 802 return -EINVAL; 803 } 804 805 return 0; 806 } 807 808 /* Start streaming */ 809 static int imx290_start_streaming(struct imx290 *imx290) 810 { 811 int ret; 812 813 /* Set init register settings */ 814 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 815 ARRAY_SIZE( 816 imx290_global_init_settings)); 817 if (ret < 0) { 818 dev_err(imx290->dev, "Could not set init registers\n"); 819 return ret; 820 } 821 822 /* Apply the register values related to current frame format */ 823 ret = imx290_write_current_format(imx290); 824 if (ret < 0) { 825 dev_err(imx290->dev, "Could not set frame format\n"); 826 return ret; 827 } 828 829 /* Apply default values of current mode */ 830 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 831 imx290->current_mode->data_size); 832 if (ret < 0) { 833 dev_err(imx290->dev, "Could not set current mode\n"); 834 return ret; 835 } 836 837 ret = imx290_write(imx290, IMX290_HMAX, imx290->current_mode->hmax, 838 NULL); 839 if (ret) 840 return ret; 841 842 /* Apply customized values from user */ 843 ret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 844 if (ret) { 845 dev_err(imx290->dev, "Could not sync v4l2 controls\n"); 846 return ret; 847 } 848 849 imx290_write(imx290, IMX290_STANDBY, 0x00, &ret); 850 851 msleep(30); 852 853 /* Start streaming */ 854 return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret); 855 } 856 857 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 858 { 859 struct imx290 *imx290 = to_imx290(sd); 860 int ret = 0; 861 862 if (enable) { 863 ret = pm_runtime_resume_and_get(imx290->dev); 864 if (ret < 0) 865 goto unlock_and_return; 866 867 ret = imx290_start_streaming(imx290); 868 if (ret) { 869 dev_err(imx290->dev, "Start stream failed\n"); 870 pm_runtime_put(imx290->dev); 871 goto unlock_and_return; 872 } 873 } else { 874 imx290_stop_streaming(imx290); 875 pm_runtime_put(imx290->dev); 876 } 877 878 unlock_and_return: 879 880 return ret; 881 } 882 883 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 884 { 885 unsigned int i; 886 887 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 888 imx290->supplies[i].supply = imx290_supply_name[i]; 889 890 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 891 imx290->supplies); 892 } 893 894 static int imx290_set_data_lanes(struct imx290 *imx290) 895 { 896 int ret = 0, laneval, frsel; 897 898 switch (imx290->nlanes) { 899 case 2: 900 laneval = 0x01; 901 frsel = 0x02; 902 break; 903 case 4: 904 laneval = 0x03; 905 frsel = 0x01; 906 break; 907 default: 908 /* 909 * We should never hit this since the data lane count is 910 * validated in probe itself 911 */ 912 dev_err(imx290->dev, "Lane configuration not supported\n"); 913 return -EINVAL; 914 } 915 916 imx290_write(imx290, IMX290_PHY_LANE_NUM, laneval, &ret); 917 imx290_write(imx290, IMX290_CSI_LANE_MODE, laneval, &ret); 918 imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret); 919 920 return ret; 921 } 922 923 static int imx290_power_on(struct device *dev) 924 { 925 struct v4l2_subdev *sd = dev_get_drvdata(dev); 926 struct imx290 *imx290 = to_imx290(sd); 927 int ret; 928 929 ret = clk_prepare_enable(imx290->xclk); 930 if (ret) { 931 dev_err(dev, "Failed to enable clock\n"); 932 return ret; 933 } 934 935 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 936 imx290->supplies); 937 if (ret) { 938 dev_err(dev, "Failed to enable regulators\n"); 939 clk_disable_unprepare(imx290->xclk); 940 return ret; 941 } 942 943 usleep_range(1, 2); 944 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 945 usleep_range(30000, 31000); 946 947 /* Set data lane count */ 948 imx290_set_data_lanes(imx290); 949 950 return 0; 951 } 952 953 static int imx290_power_off(struct device *dev) 954 { 955 struct v4l2_subdev *sd = dev_get_drvdata(dev); 956 struct imx290 *imx290 = to_imx290(sd); 957 958 clk_disable_unprepare(imx290->xclk); 959 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 960 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 961 962 return 0; 963 } 964 965 static const struct dev_pm_ops imx290_pm_ops = { 966 SET_RUNTIME_PM_OPS(imx290_power_off, imx290_power_on, NULL) 967 }; 968 969 static const struct v4l2_subdev_video_ops imx290_video_ops = { 970 .s_stream = imx290_set_stream, 971 }; 972 973 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 974 .init_cfg = imx290_entity_init_cfg, 975 .enum_mbus_code = imx290_enum_mbus_code, 976 .enum_frame_size = imx290_enum_frame_size, 977 .get_fmt = imx290_get_fmt, 978 .set_fmt = imx290_set_fmt, 979 .get_selection = imx290_get_selection, 980 }; 981 982 static const struct v4l2_subdev_ops imx290_subdev_ops = { 983 .video = &imx290_video_ops, 984 .pad = &imx290_pad_ops, 985 }; 986 987 static const struct media_entity_operations imx290_subdev_entity_ops = { 988 .link_validate = v4l2_subdev_link_validate, 989 }; 990 991 static int imx290_ctrl_init(struct imx290 *imx290) 992 { 993 struct v4l2_fwnode_device_properties props; 994 unsigned int blank; 995 int ret; 996 997 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 998 if (ret < 0) 999 return ret; 1000 1001 v4l2_ctrl_handler_init(&imx290->ctrls, 9); 1002 imx290->ctrls.lock = &imx290->lock; 1003 1004 /* 1005 * The sensor has an analog gain and a digital gain, both controlled 1006 * through a single gain value, expressed in 0.3dB increments. Values 1007 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 1008 * up to 72.0dB (240) add further digital gain. Limit the range to 1009 * analog gain only, support for digital gain can be added separately 1010 * if needed. 1011 * 1012 * The IMX327 and IMX462 are largely compatible with the IMX290, but 1013 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 1014 * gain. When support for those sensors gets added to the driver, the 1015 * gain control should be adjusted accordingly. 1016 */ 1017 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 1018 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 1019 1020 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 1021 V4L2_CID_EXPOSURE, 1, IMX290_VMAX_DEFAULT - 2, 1, 1022 IMX290_VMAX_DEFAULT - 2); 1023 1024 imx290->link_freq = 1025 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 1026 V4L2_CID_LINK_FREQ, 1027 imx290_link_freqs_num(imx290) - 1, 0, 1028 imx290_link_freqs_ptr(imx290)); 1029 if (imx290->link_freq) 1030 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1031 1032 imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 1033 V4L2_CID_PIXEL_RATE, 1034 1, INT_MAX, 1, 1035 imx290_calc_pixel_rate(imx290)); 1036 1037 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 1038 V4L2_CID_TEST_PATTERN, 1039 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 1040 0, 0, imx290_test_pattern_menu); 1041 1042 blank = imx290->current_mode->hmax - imx290->current_mode->width; 1043 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 1044 V4L2_CID_HBLANK, blank, blank, 1, 1045 blank); 1046 if (imx290->hblank) 1047 imx290->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1048 1049 blank = IMX290_VMAX_DEFAULT - imx290->current_mode->height; 1050 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 1051 V4L2_CID_VBLANK, blank, blank, 1, 1052 blank); 1053 if (imx290->vblank) 1054 imx290->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 1055 1056 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 1057 &props); 1058 1059 imx290->sd.ctrl_handler = &imx290->ctrls; 1060 1061 if (imx290->ctrls.error) { 1062 ret = imx290->ctrls.error; 1063 v4l2_ctrl_handler_free(&imx290->ctrls); 1064 return ret; 1065 } 1066 1067 return 0; 1068 } 1069 1070 /* 1071 * Returns 0 if all link frequencies used by the driver for the given number 1072 * of MIPI data lanes are mentioned in the device tree, or the value of the 1073 * first missing frequency otherwise. 1074 */ 1075 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1076 const struct v4l2_fwnode_endpoint *ep) 1077 { 1078 int i, j; 1079 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1080 int freqs_count = imx290_link_freqs_num(imx290); 1081 1082 for (i = 0; i < freqs_count; i++) { 1083 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1084 if (freqs[i] == ep->link_frequencies[j]) 1085 break; 1086 if (j == ep->nr_of_link_frequencies) 1087 return freqs[i]; 1088 } 1089 return 0; 1090 } 1091 1092 static int imx290_probe(struct i2c_client *client) 1093 { 1094 struct device *dev = &client->dev; 1095 struct fwnode_handle *endpoint; 1096 /* Only CSI2 is supported for now: */ 1097 struct v4l2_fwnode_endpoint ep = { 1098 .bus_type = V4L2_MBUS_CSI2_DPHY 1099 }; 1100 struct imx290 *imx290; 1101 u32 xclk_freq; 1102 s64 fq; 1103 int ret; 1104 1105 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1106 if (!imx290) 1107 return -ENOMEM; 1108 1109 imx290->dev = dev; 1110 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config); 1111 if (IS_ERR(imx290->regmap)) { 1112 dev_err(dev, "Unable to initialize I2C\n"); 1113 return -ENODEV; 1114 } 1115 1116 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); 1117 if (!endpoint) { 1118 dev_err(dev, "Endpoint node not found\n"); 1119 return -EINVAL; 1120 } 1121 1122 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1123 fwnode_handle_put(endpoint); 1124 if (ret == -ENXIO) { 1125 dev_err(dev, "Unsupported bus type, should be CSI2\n"); 1126 goto free_err; 1127 } else if (ret) { 1128 dev_err(dev, "Parsing endpoint node failed\n"); 1129 goto free_err; 1130 } 1131 1132 /* Get number of data lanes */ 1133 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1134 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1135 dev_err(dev, "Invalid data lanes: %d\n", imx290->nlanes); 1136 ret = -EINVAL; 1137 goto free_err; 1138 } 1139 1140 dev_dbg(dev, "Using %u data lanes\n", imx290->nlanes); 1141 1142 if (!ep.nr_of_link_frequencies) { 1143 dev_err(dev, "link-frequency property not found in DT\n"); 1144 ret = -EINVAL; 1145 goto free_err; 1146 } 1147 1148 /* Check that link frequences for all the modes are in device tree */ 1149 fq = imx290_check_link_freqs(imx290, &ep); 1150 if (fq) { 1151 dev_err(dev, "Link frequency of %lld is not supported\n", fq); 1152 ret = -EINVAL; 1153 goto free_err; 1154 } 1155 1156 /* get system clock (xclk) */ 1157 imx290->xclk = devm_clk_get(dev, "xclk"); 1158 if (IS_ERR(imx290->xclk)) { 1159 dev_err(dev, "Could not get xclk"); 1160 ret = PTR_ERR(imx290->xclk); 1161 goto free_err; 1162 } 1163 1164 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency", 1165 &xclk_freq); 1166 if (ret) { 1167 dev_err(dev, "Could not get xclk frequency\n"); 1168 goto free_err; 1169 } 1170 1171 /* external clock must be 37.125 MHz */ 1172 if (xclk_freq != 37125000) { 1173 dev_err(dev, "External clock frequency %u is not supported\n", 1174 xclk_freq); 1175 ret = -EINVAL; 1176 goto free_err; 1177 } 1178 1179 ret = clk_set_rate(imx290->xclk, xclk_freq); 1180 if (ret) { 1181 dev_err(dev, "Could not set xclk frequency\n"); 1182 goto free_err; 1183 } 1184 1185 ret = imx290_get_regulators(dev, imx290); 1186 if (ret < 0) { 1187 dev_err(dev, "Cannot get regulators\n"); 1188 goto free_err; 1189 } 1190 1191 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1192 GPIOD_OUT_HIGH); 1193 if (IS_ERR(imx290->rst_gpio)) { 1194 dev_err(dev, "Cannot get reset gpio\n"); 1195 ret = PTR_ERR(imx290->rst_gpio); 1196 goto free_err; 1197 } 1198 1199 mutex_init(&imx290->lock); 1200 1201 /* 1202 * Initialize the frame format. In particular, imx290->current_mode 1203 * and imx290->bpp are set to defaults: imx290_calc_pixel_rate() call 1204 * below relies on these fields. 1205 */ 1206 imx290_entity_init_cfg(&imx290->sd, NULL); 1207 1208 ret = imx290_ctrl_init(imx290); 1209 if (ret < 0) { 1210 dev_err(dev, "Control initialization error %d\n", ret); 1211 goto free_mutex; 1212 } 1213 1214 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1215 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1216 imx290->sd.dev = &client->dev; 1217 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1218 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1219 1220 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1221 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1222 if (ret < 0) { 1223 dev_err(dev, "Could not register media entity\n"); 1224 goto free_ctrl; 1225 } 1226 1227 ret = v4l2_async_register_subdev(&imx290->sd); 1228 if (ret < 0) { 1229 dev_err(dev, "Could not register v4l2 device\n"); 1230 goto free_entity; 1231 } 1232 1233 /* Power on the device to match runtime PM state below */ 1234 ret = imx290_power_on(dev); 1235 if (ret < 0) { 1236 dev_err(dev, "Could not power on the device\n"); 1237 goto free_entity; 1238 } 1239 1240 pm_runtime_set_active(dev); 1241 pm_runtime_enable(dev); 1242 pm_runtime_idle(dev); 1243 1244 v4l2_fwnode_endpoint_free(&ep); 1245 1246 return 0; 1247 1248 free_entity: 1249 media_entity_cleanup(&imx290->sd.entity); 1250 free_ctrl: 1251 v4l2_ctrl_handler_free(&imx290->ctrls); 1252 free_mutex: 1253 mutex_destroy(&imx290->lock); 1254 free_err: 1255 v4l2_fwnode_endpoint_free(&ep); 1256 1257 return ret; 1258 } 1259 1260 static void imx290_remove(struct i2c_client *client) 1261 { 1262 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1263 struct imx290 *imx290 = to_imx290(sd); 1264 1265 v4l2_async_unregister_subdev(sd); 1266 media_entity_cleanup(&sd->entity); 1267 v4l2_ctrl_handler_free(sd->ctrl_handler); 1268 1269 mutex_destroy(&imx290->lock); 1270 1271 pm_runtime_disable(imx290->dev); 1272 if (!pm_runtime_status_suspended(imx290->dev)) 1273 imx290_power_off(imx290->dev); 1274 pm_runtime_set_suspended(imx290->dev); 1275 } 1276 1277 static const struct of_device_id imx290_of_match[] = { 1278 { .compatible = "sony,imx290" }, 1279 { /* sentinel */ } 1280 }; 1281 MODULE_DEVICE_TABLE(of, imx290_of_match); 1282 1283 static struct i2c_driver imx290_i2c_driver = { 1284 .probe_new = imx290_probe, 1285 .remove = imx290_remove, 1286 .driver = { 1287 .name = "imx290", 1288 .pm = &imx290_pm_ops, 1289 .of_match_table = of_match_ptr(imx290_of_match), 1290 }, 1291 }; 1292 1293 module_i2c_driver(imx290_i2c_driver); 1294 1295 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1296 MODULE_AUTHOR("FRAMOS GmbH"); 1297 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1298 MODULE_LICENSE("GPL v2"); 1299