1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <media/media-entity.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-subdev.h> 24 25 #define IMX290_REG_SIZE_SHIFT 16 26 #define IMX290_REG_ADDR_MASK 0xffff 27 #define IMX290_REG_8BIT(n) ((1U << IMX290_REG_SIZE_SHIFT) | (n)) 28 #define IMX290_REG_16BIT(n) ((2U << IMX290_REG_SIZE_SHIFT) | (n)) 29 #define IMX290_REG_24BIT(n) ((3U << IMX290_REG_SIZE_SHIFT) | (n)) 30 31 #define IMX290_STANDBY IMX290_REG_8BIT(0x3000) 32 #define IMX290_REGHOLD IMX290_REG_8BIT(0x3001) 33 #define IMX290_XMSTA IMX290_REG_8BIT(0x3002) 34 #define IMX290_ADBIT IMX290_REG_8BIT(0x3005) 35 #define IMX290_ADBIT_10BIT (0 << 0) 36 #define IMX290_ADBIT_12BIT (1 << 0) 37 #define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007) 38 #define IMX290_VREVERSE BIT(0) 39 #define IMX290_HREVERSE BIT(1) 40 #define IMX290_WINMODE_1080P (0 << 4) 41 #define IMX290_WINMODE_720P (1 << 4) 42 #define IMX290_WINMODE_CROP (4 << 4) 43 #define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009) 44 #define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a) 45 #define IMX290_GAIN IMX290_REG_8BIT(0x3014) 46 #define IMX290_VMAX IMX290_REG_24BIT(0x3018) 47 #define IMX290_HMAX IMX290_REG_16BIT(0x301c) 48 #define IMX290_SHS1 IMX290_REG_24BIT(0x3020) 49 #define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a) 50 #define IMX290_WINPV IMX290_REG_16BIT(0x303c) 51 #define IMX290_WINWV IMX290_REG_16BIT(0x303e) 52 #define IMX290_WINPH IMX290_REG_16BIT(0x3040) 53 #define IMX290_WINWH IMX290_REG_16BIT(0x3042) 54 #define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046) 55 #define IMX290_ODBIT_10BIT (0 << 0) 56 #define IMX290_ODBIT_12BIT (1 << 0) 57 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 58 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 59 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 60 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 61 #define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b) 62 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 63 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 64 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 65 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 66 #define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c) 67 #define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d) 68 #define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e) 69 #define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f) 70 #define IMX290_PGCTRL IMX290_REG_8BIT(0x308c) 71 #define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129) 72 #define IMX290_ADBIT1_10BIT 0x1d 73 #define IMX290_ADBIT1_12BIT 0x00 74 #define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e) 75 #define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164) 76 #define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c) 77 #define IMX290_ADBIT2_10BIT 0x12 78 #define IMX290_ADBIT2_12BIT 0x00 79 #define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a) 80 #define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec) 81 #define IMX290_ADBIT3_10BIT 0x37 82 #define IMX290_ADBIT3_12BIT 0x0e 83 #define IMX290_REPETITION IMX290_REG_8BIT(0x3405) 84 #define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407) 85 #define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414) 86 #define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418) 87 #define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441) 88 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 89 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 90 #define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443) 91 #define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444) 92 #define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446) 93 #define IMX290_THSZERO IMX290_REG_16BIT(0x3448) 94 #define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a) 95 #define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c) 96 #define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e) 97 #define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450) 98 #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452) 99 #define IMX290_TLPX IMX290_REG_16BIT(0x3454) 100 #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472) 101 102 #define IMX290_PGCTRL_REGEN BIT(0) 103 #define IMX290_PGCTRL_THRU BIT(1) 104 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 105 106 #define IMX290_VMAX_DEFAULT 1125 107 108 109 /* 110 * The IMX290 pixel array is organized as follows: 111 * 112 * +------------------------------------+ 113 * | Optical Black | } Vertical effective optical black (10) 114 * +---+------------------------------------+---+ 115 * | | | | } Effective top margin (8) 116 * | | +----------------------------+ | | \ 117 * | | | | | | | 118 * | | | | | | | 119 * | | | | | | | 120 * | | | Recording Pixel Area | | | | Recommended height (1080) 121 * | | | | | | | 122 * | | | | | | | 123 * | | | | | | | 124 * | | +----------------------------+ | | / 125 * | | | | } Effective bottom margin (9) 126 * +---+------------------------------------+---+ 127 * <-> <-> <--------------------------> <-> <-> 128 * \---- Ignored right margin (4) 129 * \-------- Effective right margin (9) 130 * \------------------------- Recommended width (1920) 131 * \----------------------------------------- Effective left margin (8) 132 * \--------------------------------------------- Ignored left margin (4) 133 * 134 * The optical black lines are output over CSI-2 with a separate data type. 135 * 136 * The pixel array is meant to have 1920x1080 usable pixels after image 137 * processing in an ISP. It has 8 (9) extra active pixels usable for color 138 * processing in the ISP on the top and left (bottom and right) sides of the 139 * image. In addition, 4 additional pixels are present on the left and right 140 * sides of the image, documented as "ignored area". 141 * 142 * As far as is understood, all pixels of the pixel array (ignored area, color 143 * processing margins and recording area) can be output by the sensor. 144 */ 145 146 #define IMX290_PIXEL_ARRAY_WIDTH 1945 147 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 148 #define IMX920_PIXEL_ARRAY_MARGIN_LEFT 12 149 #define IMX920_PIXEL_ARRAY_MARGIN_RIGHT 13 150 #define IMX920_PIXEL_ARRAY_MARGIN_TOP 8 151 #define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM 9 152 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 153 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 154 155 /* Equivalent value for 16bpp */ 156 #define IMX290_BLACK_LEVEL_DEFAULT 3840 157 158 #define IMX290_NUM_SUPPLIES 3 159 160 struct imx290_regval { 161 u32 reg; 162 u32 val; 163 }; 164 165 struct imx290_mode { 166 u32 width; 167 u32 height; 168 u32 hmax; 169 u8 link_freq_index; 170 171 const struct imx290_regval *data; 172 u32 data_size; 173 }; 174 175 struct imx290 { 176 struct device *dev; 177 struct clk *xclk; 178 struct regmap *regmap; 179 u8 nlanes; 180 181 struct v4l2_subdev sd; 182 struct media_pad pad; 183 184 const struct imx290_mode *current_mode; 185 186 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 187 struct gpio_desc *rst_gpio; 188 189 struct v4l2_ctrl_handler ctrls; 190 struct v4l2_ctrl *link_freq; 191 struct v4l2_ctrl *pixel_rate; 192 struct v4l2_ctrl *hblank; 193 struct v4l2_ctrl *vblank; 194 }; 195 196 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 197 { 198 return container_of(_sd, struct imx290, sd); 199 } 200 201 /* ----------------------------------------------------------------------------- 202 * Modes and formats 203 */ 204 205 static const struct imx290_regval imx290_global_init_settings[] = { 206 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 207 { IMX290_VMAX, IMX290_VMAX_DEFAULT }, 208 { IMX290_EXTCK_FREQ, 0x2520 }, 209 { IMX290_WINWV_OB, 12 }, 210 { IMX290_WINPH, 0 }, 211 { IMX290_WINPV, 0 }, 212 { IMX290_WINWH, 1948 }, 213 { IMX290_WINWV, 1097 }, 214 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 215 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 216 { IMX290_REG_8BIT(0x300f), 0x00 }, 217 { IMX290_REG_8BIT(0x3010), 0x21 }, 218 { IMX290_REG_8BIT(0x3012), 0x64 }, 219 { IMX290_REG_8BIT(0x3013), 0x00 }, 220 { IMX290_REG_8BIT(0x3016), 0x09 }, 221 { IMX290_REG_8BIT(0x3070), 0x02 }, 222 { IMX290_REG_8BIT(0x3071), 0x11 }, 223 { IMX290_REG_8BIT(0x309b), 0x10 }, 224 { IMX290_REG_8BIT(0x309c), 0x22 }, 225 { IMX290_REG_8BIT(0x30a2), 0x02 }, 226 { IMX290_REG_8BIT(0x30a6), 0x20 }, 227 { IMX290_REG_8BIT(0x30a8), 0x20 }, 228 { IMX290_REG_8BIT(0x30aa), 0x20 }, 229 { IMX290_REG_8BIT(0x30ac), 0x20 }, 230 { IMX290_REG_8BIT(0x30b0), 0x43 }, 231 { IMX290_REG_8BIT(0x3119), 0x9e }, 232 { IMX290_REG_8BIT(0x311c), 0x1e }, 233 { IMX290_REG_8BIT(0x311e), 0x08 }, 234 { IMX290_REG_8BIT(0x3128), 0x05 }, 235 { IMX290_REG_8BIT(0x313d), 0x83 }, 236 { IMX290_REG_8BIT(0x3150), 0x03 }, 237 { IMX290_REG_8BIT(0x317e), 0x00 }, 238 { IMX290_REG_8BIT(0x32b8), 0x50 }, 239 { IMX290_REG_8BIT(0x32b9), 0x10 }, 240 { IMX290_REG_8BIT(0x32ba), 0x00 }, 241 { IMX290_REG_8BIT(0x32bb), 0x04 }, 242 { IMX290_REG_8BIT(0x32c8), 0x50 }, 243 { IMX290_REG_8BIT(0x32c9), 0x10 }, 244 { IMX290_REG_8BIT(0x32ca), 0x00 }, 245 { IMX290_REG_8BIT(0x32cb), 0x04 }, 246 { IMX290_REG_8BIT(0x332c), 0xd3 }, 247 { IMX290_REG_8BIT(0x332d), 0x10 }, 248 { IMX290_REG_8BIT(0x332e), 0x0d }, 249 { IMX290_REG_8BIT(0x3358), 0x06 }, 250 { IMX290_REG_8BIT(0x3359), 0xe1 }, 251 { IMX290_REG_8BIT(0x335a), 0x11 }, 252 { IMX290_REG_8BIT(0x3360), 0x1e }, 253 { IMX290_REG_8BIT(0x3361), 0x61 }, 254 { IMX290_REG_8BIT(0x3362), 0x10 }, 255 { IMX290_REG_8BIT(0x33b0), 0x50 }, 256 { IMX290_REG_8BIT(0x33b2), 0x1a }, 257 { IMX290_REG_8BIT(0x33b3), 0x04 }, 258 { IMX290_REG_8BIT(0x3480), 0x49 }, 259 }; 260 261 static const struct imx290_regval imx290_1080p_settings[] = { 262 /* mode settings */ 263 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 264 { IMX290_WINWV_OB, 12 }, 265 { IMX290_OPB_SIZE_V, 10 }, 266 { IMX290_X_OUT_SIZE, 1920 }, 267 { IMX290_Y_OUT_SIZE, 1080 }, 268 { IMX290_INCKSEL1, 0x18 }, 269 { IMX290_INCKSEL2, 0x03 }, 270 { IMX290_INCKSEL3, 0x20 }, 271 { IMX290_INCKSEL4, 0x01 }, 272 { IMX290_INCKSEL5, 0x1a }, 273 { IMX290_INCKSEL6, 0x1a }, 274 /* data rate settings */ 275 { IMX290_REPETITION, 0x10 }, 276 { IMX290_TCLKPOST, 87 }, 277 { IMX290_THSZERO, 55 }, 278 { IMX290_THSPREPARE, 31 }, 279 { IMX290_TCLKTRAIL, 31 }, 280 { IMX290_THSTRAIL, 31 }, 281 { IMX290_TCLKZERO, 119 }, 282 { IMX290_TCLKPREPARE, 31 }, 283 { IMX290_TLPX, 23 }, 284 }; 285 286 static const struct imx290_regval imx290_720p_settings[] = { 287 /* mode settings */ 288 { IMX290_CTRL_07, IMX290_WINMODE_720P }, 289 { IMX290_WINWV_OB, 6 }, 290 { IMX290_OPB_SIZE_V, 4 }, 291 { IMX290_X_OUT_SIZE, 1280 }, 292 { IMX290_Y_OUT_SIZE, 720 }, 293 { IMX290_INCKSEL1, 0x20 }, 294 { IMX290_INCKSEL2, 0x00 }, 295 { IMX290_INCKSEL3, 0x20 }, 296 { IMX290_INCKSEL4, 0x01 }, 297 { IMX290_INCKSEL5, 0x1a }, 298 { IMX290_INCKSEL6, 0x1a }, 299 /* data rate settings */ 300 { IMX290_REPETITION, 0x10 }, 301 { IMX290_TCLKPOST, 79 }, 302 { IMX290_THSZERO, 47 }, 303 { IMX290_THSPREPARE, 23 }, 304 { IMX290_TCLKTRAIL, 23 }, 305 { IMX290_THSTRAIL, 23 }, 306 { IMX290_TCLKZERO, 87 }, 307 { IMX290_TCLKPREPARE, 23 }, 308 { IMX290_TLPX, 23 }, 309 }; 310 311 static const struct imx290_regval imx290_10bit_settings[] = { 312 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 313 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 314 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 315 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 316 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 317 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 318 }; 319 320 static const struct imx290_regval imx290_12bit_settings[] = { 321 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 322 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 323 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 324 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 325 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 326 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 327 }; 328 329 /* supported link frequencies */ 330 #define FREQ_INDEX_1080P 0 331 #define FREQ_INDEX_720P 1 332 static const s64 imx290_link_freq_2lanes[] = { 333 [FREQ_INDEX_1080P] = 445500000, 334 [FREQ_INDEX_720P] = 297000000, 335 }; 336 static const s64 imx290_link_freq_4lanes[] = { 337 [FREQ_INDEX_1080P] = 222750000, 338 [FREQ_INDEX_720P] = 148500000, 339 }; 340 341 /* 342 * In this function and in the similar ones below We rely on imx290_probe() 343 * to ensure that nlanes is either 2 or 4. 344 */ 345 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 346 { 347 if (imx290->nlanes == 2) 348 return imx290_link_freq_2lanes; 349 else 350 return imx290_link_freq_4lanes; 351 } 352 353 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 354 { 355 if (imx290->nlanes == 2) 356 return ARRAY_SIZE(imx290_link_freq_2lanes); 357 else 358 return ARRAY_SIZE(imx290_link_freq_4lanes); 359 } 360 361 /* Mode configs */ 362 static const struct imx290_mode imx290_modes_2lanes[] = { 363 { 364 .width = 1920, 365 .height = 1080, 366 .hmax = 4400, 367 .link_freq_index = FREQ_INDEX_1080P, 368 .data = imx290_1080p_settings, 369 .data_size = ARRAY_SIZE(imx290_1080p_settings), 370 }, 371 { 372 .width = 1280, 373 .height = 720, 374 .hmax = 6600, 375 .link_freq_index = FREQ_INDEX_720P, 376 .data = imx290_720p_settings, 377 .data_size = ARRAY_SIZE(imx290_720p_settings), 378 }, 379 }; 380 381 static const struct imx290_mode imx290_modes_4lanes[] = { 382 { 383 .width = 1920, 384 .height = 1080, 385 .hmax = 2200, 386 .link_freq_index = FREQ_INDEX_1080P, 387 .data = imx290_1080p_settings, 388 .data_size = ARRAY_SIZE(imx290_1080p_settings), 389 }, 390 { 391 .width = 1280, 392 .height = 720, 393 .hmax = 3300, 394 .link_freq_index = FREQ_INDEX_720P, 395 .data = imx290_720p_settings, 396 .data_size = ARRAY_SIZE(imx290_720p_settings), 397 }, 398 }; 399 400 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 401 { 402 if (imx290->nlanes == 2) 403 return imx290_modes_2lanes; 404 else 405 return imx290_modes_4lanes; 406 } 407 408 static inline int imx290_modes_num(const struct imx290 *imx290) 409 { 410 if (imx290->nlanes == 2) 411 return ARRAY_SIZE(imx290_modes_2lanes); 412 else 413 return ARRAY_SIZE(imx290_modes_4lanes); 414 } 415 416 struct imx290_format_info { 417 u32 code; 418 u8 bpp; 419 const struct imx290_regval *regs; 420 unsigned int num_regs; 421 }; 422 423 static const struct imx290_format_info imx290_formats[] = { 424 { 425 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 426 .bpp = 10, 427 .regs = imx290_10bit_settings, 428 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 429 }, { 430 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 431 .bpp = 12, 432 .regs = imx290_12bit_settings, 433 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 434 } 435 }; 436 437 static const struct imx290_format_info *imx290_format_info(u32 code) 438 { 439 unsigned int i; 440 441 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 442 const struct imx290_format_info *info = &imx290_formats[i]; 443 444 if (info->code == code) 445 return info; 446 } 447 448 return NULL; 449 } 450 451 /* ----------------------------------------------------------------------------- 452 * Register access 453 */ 454 455 static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value) 456 { 457 u8 data[3] = { 0, 0, 0 }; 458 int ret; 459 460 ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 461 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 462 if (ret < 0) { 463 dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n", 464 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 465 addr & IMX290_REG_ADDR_MASK, ret); 466 return ret; 467 } 468 469 *value = (data[2] << 16) | (data[1] << 8) | data[0]; 470 return 0; 471 } 472 473 static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err) 474 { 475 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 }; 476 int ret; 477 478 if (err && *err) 479 return *err; 480 481 ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 482 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 483 if (ret < 0) { 484 dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n", 485 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 486 addr & IMX290_REG_ADDR_MASK, ret); 487 if (err) 488 *err = ret; 489 } 490 491 return ret; 492 } 493 494 static int imx290_set_register_array(struct imx290 *imx290, 495 const struct imx290_regval *settings, 496 unsigned int num_settings) 497 { 498 unsigned int i; 499 int ret; 500 501 for (i = 0; i < num_settings; ++i, ++settings) { 502 ret = imx290_write(imx290, settings->reg, settings->val, NULL); 503 if (ret < 0) 504 return ret; 505 } 506 507 /* Provide 10ms settle time */ 508 usleep_range(10000, 11000); 509 510 return 0; 511 } 512 513 static int imx290_set_data_lanes(struct imx290 *imx290) 514 { 515 int ret = 0; 516 u32 frsel; 517 518 switch (imx290->nlanes) { 519 case 2: 520 default: 521 frsel = 0x02; 522 break; 523 case 4: 524 frsel = 0x01; 525 break; 526 } 527 528 imx290_write(imx290, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, &ret); 529 imx290_write(imx290, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, &ret); 530 imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret); 531 532 return ret; 533 } 534 535 static int imx290_set_black_level(struct imx290 *imx290, 536 const struct v4l2_mbus_framefmt *format, 537 unsigned int black_level, int *err) 538 { 539 unsigned int bpp = imx290_format_info(format->code)->bpp; 540 541 return imx290_write(imx290, IMX290_BLKLEVEL, 542 black_level >> (16 - bpp), err); 543 } 544 545 static int imx290_setup_format(struct imx290 *imx290, 546 const struct v4l2_mbus_framefmt *format) 547 { 548 const struct imx290_format_info *info; 549 int ret; 550 551 info = imx290_format_info(format->code); 552 553 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 554 if (ret < 0) { 555 dev_err(imx290->dev, "Could not set format registers\n"); 556 return ret; 557 } 558 559 return imx290_set_black_level(imx290, format, 560 IMX290_BLACK_LEVEL_DEFAULT, &ret); 561 } 562 563 /* ---------------------------------------------------------------------------- 564 * Controls 565 */ 566 567 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 568 { 569 struct imx290 *imx290 = container_of(ctrl->handler, 570 struct imx290, ctrls); 571 const struct v4l2_mbus_framefmt *format; 572 struct v4l2_subdev_state *state; 573 int ret = 0; 574 575 /* 576 * Return immediately for controls that don't need to be applied to the 577 * device. 578 */ 579 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 580 return 0; 581 582 /* V4L2 controls values will be applied only when power is already up */ 583 if (!pm_runtime_get_if_in_use(imx290->dev)) 584 return 0; 585 586 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 587 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 588 589 switch (ctrl->id) { 590 case V4L2_CID_ANALOGUE_GAIN: 591 ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL); 592 break; 593 594 case V4L2_CID_EXPOSURE: 595 ret = imx290_write(imx290, IMX290_SHS1, 596 IMX290_VMAX_DEFAULT - ctrl->val - 1, NULL); 597 break; 598 599 case V4L2_CID_TEST_PATTERN: 600 if (ctrl->val) { 601 imx290_set_black_level(imx290, format, 0, &ret); 602 usleep_range(10000, 11000); 603 imx290_write(imx290, IMX290_PGCTRL, 604 (u8)(IMX290_PGCTRL_REGEN | 605 IMX290_PGCTRL_THRU | 606 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 607 } else { 608 imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret); 609 usleep_range(10000, 11000); 610 imx290_set_black_level(imx290, format, 611 IMX290_BLACK_LEVEL_DEFAULT, &ret); 612 } 613 break; 614 615 default: 616 ret = -EINVAL; 617 break; 618 } 619 620 pm_runtime_mark_last_busy(imx290->dev); 621 pm_runtime_put_autosuspend(imx290->dev); 622 623 return ret; 624 } 625 626 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 627 .s_ctrl = imx290_set_ctrl, 628 }; 629 630 static const char * const imx290_test_pattern_menu[] = { 631 "Disabled", 632 "Sequence Pattern 1", 633 "Horizontal Color-bar Chart", 634 "Vertical Color-bar Chart", 635 "Sequence Pattern 2", 636 "Gradation Pattern 1", 637 "Gradation Pattern 2", 638 "000/555h Toggle Pattern", 639 }; 640 641 static void imx290_ctrl_update(struct imx290 *imx290, 642 const struct v4l2_mbus_framefmt *format, 643 const struct imx290_mode *mode) 644 { 645 unsigned int hblank = mode->hmax - mode->width; 646 unsigned int vblank = IMX290_VMAX_DEFAULT - mode->height; 647 s64 link_freq = imx290_link_freqs_ptr(imx290)[mode->link_freq_index]; 648 u64 pixel_rate; 649 650 /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 651 pixel_rate = link_freq * 2 * imx290->nlanes; 652 do_div(pixel_rate, imx290_format_info(format->code)->bpp); 653 654 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 655 __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate, pixel_rate); 656 657 __v4l2_ctrl_modify_range(imx290->hblank, hblank, hblank, 1, hblank); 658 __v4l2_ctrl_modify_range(imx290->vblank, vblank, vblank, 1, vblank); 659 } 660 661 static int imx290_ctrl_init(struct imx290 *imx290) 662 { 663 struct v4l2_fwnode_device_properties props; 664 int ret; 665 666 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 667 if (ret < 0) 668 return ret; 669 670 v4l2_ctrl_handler_init(&imx290->ctrls, 9); 671 672 /* 673 * The sensor has an analog gain and a digital gain, both controlled 674 * through a single gain value, expressed in 0.3dB increments. Values 675 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 676 * up to 72.0dB (240) add further digital gain. Limit the range to 677 * analog gain only, support for digital gain can be added separately 678 * if needed. 679 * 680 * The IMX327 and IMX462 are largely compatible with the IMX290, but 681 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 682 * gain. When support for those sensors gets added to the driver, the 683 * gain control should be adjusted accordingly. 684 */ 685 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 686 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 687 688 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 689 V4L2_CID_EXPOSURE, 1, IMX290_VMAX_DEFAULT - 2, 1, 690 IMX290_VMAX_DEFAULT - 2); 691 692 /* 693 * Set the link frequency, pixel rate, horizontal blanking and vertical 694 * blanking to hardcoded values, they will be updated by 695 * imx290_ctrl_update(). 696 */ 697 imx290->link_freq = 698 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 699 V4L2_CID_LINK_FREQ, 700 imx290_link_freqs_num(imx290) - 1, 0, 701 imx290_link_freqs_ptr(imx290)); 702 if (imx290->link_freq) 703 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 704 705 imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 706 V4L2_CID_PIXEL_RATE, 707 1, INT_MAX, 1, 1); 708 709 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 710 V4L2_CID_TEST_PATTERN, 711 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 712 0, 0, imx290_test_pattern_menu); 713 714 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 715 V4L2_CID_HBLANK, 1, 1, 1, 1); 716 if (imx290->hblank) 717 imx290->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 718 719 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 720 V4L2_CID_VBLANK, 1, 1, 1, 1); 721 if (imx290->vblank) 722 imx290->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 723 724 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 725 &props); 726 727 imx290->sd.ctrl_handler = &imx290->ctrls; 728 729 if (imx290->ctrls.error) { 730 ret = imx290->ctrls.error; 731 v4l2_ctrl_handler_free(&imx290->ctrls); 732 return ret; 733 } 734 735 return 0; 736 } 737 738 /* ---------------------------------------------------------------------------- 739 * Subdev operations 740 */ 741 742 /* Start streaming */ 743 static int imx290_start_streaming(struct imx290 *imx290, 744 struct v4l2_subdev_state *state) 745 { 746 const struct v4l2_mbus_framefmt *format; 747 int ret; 748 749 /* Set init register settings */ 750 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 751 ARRAY_SIZE( 752 imx290_global_init_settings)); 753 if (ret < 0) { 754 dev_err(imx290->dev, "Could not set init registers\n"); 755 return ret; 756 } 757 758 /* Set data lane count */ 759 ret = imx290_set_data_lanes(imx290); 760 if (ret < 0) { 761 dev_err(imx290->dev, "Could not set data lanes\n"); 762 return ret; 763 } 764 765 /* Apply the register values related to current frame format */ 766 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 767 ret = imx290_setup_format(imx290, format); 768 if (ret < 0) { 769 dev_err(imx290->dev, "Could not set frame format\n"); 770 return ret; 771 } 772 773 /* Apply default values of current mode */ 774 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 775 imx290->current_mode->data_size); 776 if (ret < 0) { 777 dev_err(imx290->dev, "Could not set current mode\n"); 778 return ret; 779 } 780 781 ret = imx290_write(imx290, IMX290_HMAX, imx290->current_mode->hmax, 782 NULL); 783 if (ret) 784 return ret; 785 786 /* Apply customized values from user */ 787 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 788 if (ret) { 789 dev_err(imx290->dev, "Could not sync v4l2 controls\n"); 790 return ret; 791 } 792 793 imx290_write(imx290, IMX290_STANDBY, 0x00, &ret); 794 795 msleep(30); 796 797 /* Start streaming */ 798 return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret); 799 } 800 801 /* Stop streaming */ 802 static int imx290_stop_streaming(struct imx290 *imx290) 803 { 804 int ret = 0; 805 806 imx290_write(imx290, IMX290_STANDBY, 0x01, &ret); 807 808 msleep(30); 809 810 return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret); 811 } 812 813 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 814 { 815 struct imx290 *imx290 = to_imx290(sd); 816 struct v4l2_subdev_state *state; 817 int ret = 0; 818 819 state = v4l2_subdev_lock_and_get_active_state(sd); 820 821 if (enable) { 822 ret = pm_runtime_resume_and_get(imx290->dev); 823 if (ret < 0) 824 goto unlock; 825 826 ret = imx290_start_streaming(imx290, state); 827 if (ret) { 828 dev_err(imx290->dev, "Start stream failed\n"); 829 pm_runtime_put_sync(imx290->dev); 830 goto unlock; 831 } 832 } else { 833 imx290_stop_streaming(imx290); 834 pm_runtime_mark_last_busy(imx290->dev); 835 pm_runtime_put_autosuspend(imx290->dev); 836 } 837 838 unlock: 839 v4l2_subdev_unlock_state(state); 840 return ret; 841 } 842 843 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 844 struct v4l2_subdev_state *sd_state, 845 struct v4l2_subdev_mbus_code_enum *code) 846 { 847 if (code->index >= ARRAY_SIZE(imx290_formats)) 848 return -EINVAL; 849 850 code->code = imx290_formats[code->index].code; 851 852 return 0; 853 } 854 855 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 856 struct v4l2_subdev_state *sd_state, 857 struct v4l2_subdev_frame_size_enum *fse) 858 { 859 const struct imx290 *imx290 = to_imx290(sd); 860 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 861 862 if (!imx290_format_info(fse->code)) 863 return -EINVAL; 864 865 if (fse->index >= imx290_modes_num(imx290)) 866 return -EINVAL; 867 868 fse->min_width = imx290_modes[fse->index].width; 869 fse->max_width = imx290_modes[fse->index].width; 870 fse->min_height = imx290_modes[fse->index].height; 871 fse->max_height = imx290_modes[fse->index].height; 872 873 return 0; 874 } 875 876 static int imx290_set_fmt(struct v4l2_subdev *sd, 877 struct v4l2_subdev_state *sd_state, 878 struct v4l2_subdev_format *fmt) 879 { 880 struct imx290 *imx290 = to_imx290(sd); 881 const struct imx290_mode *mode; 882 struct v4l2_mbus_framefmt *format; 883 884 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 885 imx290_modes_num(imx290), width, height, 886 fmt->format.width, fmt->format.height); 887 888 fmt->format.width = mode->width; 889 fmt->format.height = mode->height; 890 891 if (!imx290_format_info(fmt->format.code)) 892 fmt->format.code = imx290_formats[0].code; 893 894 fmt->format.field = V4L2_FIELD_NONE; 895 896 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 897 898 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 899 imx290->current_mode = mode; 900 901 imx290_ctrl_update(imx290, &fmt->format, mode); 902 } 903 904 *format = fmt->format; 905 906 return 0; 907 } 908 909 static int imx290_get_selection(struct v4l2_subdev *sd, 910 struct v4l2_subdev_state *sd_state, 911 struct v4l2_subdev_selection *sel) 912 { 913 struct v4l2_mbus_framefmt *format; 914 915 switch (sel->target) { 916 case V4L2_SEL_TGT_CROP: { 917 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 918 919 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP 920 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2; 921 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT 922 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2; 923 sel->r.width = format->width; 924 sel->r.height = format->height; 925 926 return 0; 927 } 928 929 case V4L2_SEL_TGT_NATIVE_SIZE: 930 case V4L2_SEL_TGT_CROP_BOUNDS: 931 sel->r.top = 0; 932 sel->r.left = 0; 933 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 934 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 935 936 return 0; 937 938 case V4L2_SEL_TGT_CROP_DEFAULT: 939 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP; 940 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT; 941 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 942 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 943 944 return 0; 945 946 default: 947 return -EINVAL; 948 } 949 } 950 951 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 952 struct v4l2_subdev_state *sd_state) 953 { 954 struct v4l2_subdev_format fmt = { 955 .which = V4L2_SUBDEV_FORMAT_TRY, 956 .format = { 957 .width = 1920, 958 .height = 1080, 959 }, 960 }; 961 962 imx290_set_fmt(subdev, sd_state, &fmt); 963 964 return 0; 965 } 966 967 static const struct v4l2_subdev_video_ops imx290_video_ops = { 968 .s_stream = imx290_set_stream, 969 }; 970 971 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 972 .init_cfg = imx290_entity_init_cfg, 973 .enum_mbus_code = imx290_enum_mbus_code, 974 .enum_frame_size = imx290_enum_frame_size, 975 .get_fmt = v4l2_subdev_get_fmt, 976 .set_fmt = imx290_set_fmt, 977 .get_selection = imx290_get_selection, 978 }; 979 980 static const struct v4l2_subdev_ops imx290_subdev_ops = { 981 .video = &imx290_video_ops, 982 .pad = &imx290_pad_ops, 983 }; 984 985 static const struct media_entity_operations imx290_subdev_entity_ops = { 986 .link_validate = v4l2_subdev_link_validate, 987 }; 988 989 static int imx290_subdev_init(struct imx290 *imx290) 990 { 991 struct i2c_client *client = to_i2c_client(imx290->dev); 992 const struct v4l2_mbus_framefmt *format; 993 struct v4l2_subdev_state *state; 994 int ret; 995 996 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 997 998 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 999 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1000 imx290->sd.dev = imx290->dev; 1001 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1002 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1003 1004 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1005 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1006 if (ret < 0) { 1007 dev_err(imx290->dev, "Could not register media entity\n"); 1008 return ret; 1009 } 1010 1011 ret = imx290_ctrl_init(imx290); 1012 if (ret < 0) { 1013 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1014 goto err_media; 1015 } 1016 1017 imx290->sd.state_lock = imx290->ctrls.lock; 1018 1019 ret = v4l2_subdev_init_finalize(&imx290->sd); 1020 if (ret < 0) { 1021 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1022 goto err_ctrls; 1023 } 1024 1025 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1026 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 1027 imx290_ctrl_update(imx290, format, imx290->current_mode); 1028 v4l2_subdev_unlock_state(state); 1029 1030 return 0; 1031 1032 err_ctrls: 1033 v4l2_ctrl_handler_free(&imx290->ctrls); 1034 err_media: 1035 media_entity_cleanup(&imx290->sd.entity); 1036 return ret; 1037 } 1038 1039 static void imx290_subdev_cleanup(struct imx290 *imx290) 1040 { 1041 v4l2_subdev_cleanup(&imx290->sd); 1042 media_entity_cleanup(&imx290->sd.entity); 1043 v4l2_ctrl_handler_free(&imx290->ctrls); 1044 } 1045 1046 /* ---------------------------------------------------------------------------- 1047 * Power management 1048 */ 1049 1050 static int imx290_power_on(struct imx290 *imx290) 1051 { 1052 int ret; 1053 1054 ret = clk_prepare_enable(imx290->xclk); 1055 if (ret) { 1056 dev_err(imx290->dev, "Failed to enable clock\n"); 1057 return ret; 1058 } 1059 1060 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1061 imx290->supplies); 1062 if (ret) { 1063 dev_err(imx290->dev, "Failed to enable regulators\n"); 1064 clk_disable_unprepare(imx290->xclk); 1065 return ret; 1066 } 1067 1068 usleep_range(1, 2); 1069 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1070 usleep_range(30000, 31000); 1071 1072 return 0; 1073 } 1074 1075 static void imx290_power_off(struct imx290 *imx290) 1076 { 1077 clk_disable_unprepare(imx290->xclk); 1078 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1079 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1080 } 1081 1082 static int imx290_runtime_resume(struct device *dev) 1083 { 1084 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1085 struct imx290 *imx290 = to_imx290(sd); 1086 1087 return imx290_power_on(imx290); 1088 } 1089 1090 static int imx290_runtime_suspend(struct device *dev) 1091 { 1092 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1093 struct imx290 *imx290 = to_imx290(sd); 1094 1095 imx290_power_off(imx290); 1096 1097 return 0; 1098 } 1099 1100 static const struct dev_pm_ops imx290_pm_ops = { 1101 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1102 }; 1103 1104 /* ---------------------------------------------------------------------------- 1105 * Probe & remove 1106 */ 1107 1108 static const struct regmap_config imx290_regmap_config = { 1109 .reg_bits = 16, 1110 .val_bits = 8, 1111 }; 1112 1113 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1114 "vdda", 1115 "vddd", 1116 "vdddo", 1117 }; 1118 1119 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1120 { 1121 unsigned int i; 1122 1123 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1124 imx290->supplies[i].supply = imx290_supply_name[i]; 1125 1126 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1127 imx290->supplies); 1128 } 1129 1130 static int imx290_init_clk(struct imx290 *imx290) 1131 { 1132 u32 xclk_freq; 1133 int ret; 1134 1135 ret = fwnode_property_read_u32(dev_fwnode(imx290->dev), 1136 "clock-frequency", &xclk_freq); 1137 if (ret) { 1138 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1139 return ret; 1140 } 1141 1142 /* external clock must be 37.125 MHz */ 1143 if (xclk_freq != 37125000) { 1144 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1145 xclk_freq); 1146 return -EINVAL; 1147 } 1148 1149 ret = clk_set_rate(imx290->xclk, xclk_freq); 1150 if (ret) { 1151 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1152 return ret; 1153 } 1154 1155 return 0; 1156 } 1157 1158 /* 1159 * Returns 0 if all link frequencies used by the driver for the given number 1160 * of MIPI data lanes are mentioned in the device tree, or the value of the 1161 * first missing frequency otherwise. 1162 */ 1163 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1164 const struct v4l2_fwnode_endpoint *ep) 1165 { 1166 int i, j; 1167 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1168 int freqs_count = imx290_link_freqs_num(imx290); 1169 1170 for (i = 0; i < freqs_count; i++) { 1171 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1172 if (freqs[i] == ep->link_frequencies[j]) 1173 break; 1174 if (j == ep->nr_of_link_frequencies) 1175 return freqs[i]; 1176 } 1177 return 0; 1178 } 1179 1180 static int imx290_parse_dt(struct imx290 *imx290) 1181 { 1182 /* Only CSI2 is supported for now: */ 1183 struct v4l2_fwnode_endpoint ep = { 1184 .bus_type = V4L2_MBUS_CSI2_DPHY 1185 }; 1186 struct fwnode_handle *endpoint; 1187 int ret; 1188 s64 fq; 1189 1190 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1191 if (!endpoint) { 1192 dev_err(imx290->dev, "Endpoint node not found\n"); 1193 return -EINVAL; 1194 } 1195 1196 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1197 fwnode_handle_put(endpoint); 1198 if (ret == -ENXIO) { 1199 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1200 goto done; 1201 } else if (ret) { 1202 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1203 goto done; 1204 } 1205 1206 /* Get number of data lanes */ 1207 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1208 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1209 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1210 ret = -EINVAL; 1211 goto done; 1212 } 1213 1214 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1215 1216 if (!ep.nr_of_link_frequencies) { 1217 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1218 ret = -EINVAL; 1219 goto done; 1220 } 1221 1222 /* Check that link frequences for all the modes are in device tree */ 1223 fq = imx290_check_link_freqs(imx290, &ep); 1224 if (fq) { 1225 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1226 fq); 1227 ret = -EINVAL; 1228 goto done; 1229 } 1230 1231 ret = 0; 1232 1233 done: 1234 v4l2_fwnode_endpoint_free(&ep); 1235 return ret; 1236 } 1237 1238 static int imx290_probe(struct i2c_client *client) 1239 { 1240 struct device *dev = &client->dev; 1241 struct imx290 *imx290; 1242 int ret; 1243 1244 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1245 if (!imx290) 1246 return -ENOMEM; 1247 1248 imx290->dev = dev; 1249 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config); 1250 if (IS_ERR(imx290->regmap)) { 1251 dev_err(dev, "Unable to initialize I2C\n"); 1252 return -ENODEV; 1253 } 1254 1255 ret = imx290_parse_dt(imx290); 1256 if (ret) 1257 return ret; 1258 1259 /* Acquire resources. */ 1260 imx290->xclk = devm_clk_get(dev, "xclk"); 1261 if (IS_ERR(imx290->xclk)) 1262 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1263 "Could not get xclk"); 1264 1265 ret = imx290_get_regulators(dev, imx290); 1266 if (ret < 0) 1267 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1268 1269 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1270 GPIOD_OUT_HIGH); 1271 if (IS_ERR(imx290->rst_gpio)) 1272 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1273 "Cannot get reset gpio\n"); 1274 1275 /* Initialize external clock frequency. */ 1276 ret = imx290_init_clk(imx290); 1277 if (ret) 1278 return ret; 1279 1280 /* 1281 * Enable power management. The driver supports runtime PM, but needs to 1282 * work when runtime PM is disabled in the kernel. To that end, power 1283 * the sensor on manually here. 1284 */ 1285 ret = imx290_power_on(imx290); 1286 if (ret < 0) { 1287 dev_err(dev, "Could not power on the device\n"); 1288 return ret; 1289 } 1290 1291 /* 1292 * Enable runtime PM with autosuspend. As the device has been powered 1293 * manually, mark it as active, and increase the usage count without 1294 * resuming the device. 1295 */ 1296 pm_runtime_set_active(dev); 1297 pm_runtime_get_noresume(dev); 1298 pm_runtime_enable(dev); 1299 pm_runtime_set_autosuspend_delay(dev, 1000); 1300 pm_runtime_use_autosuspend(dev); 1301 1302 /* Initialize the V4L2 subdev. */ 1303 ret = imx290_subdev_init(imx290); 1304 if (ret) 1305 goto err_pm; 1306 1307 /* 1308 * Finally, register the V4L2 subdev. This must be done after 1309 * initializing everything as the subdev can be used immediately after 1310 * being registered. 1311 */ 1312 ret = v4l2_async_register_subdev(&imx290->sd); 1313 if (ret < 0) { 1314 dev_err(dev, "Could not register v4l2 device\n"); 1315 goto err_subdev; 1316 } 1317 1318 /* 1319 * Decrease the PM usage count. The device will get suspended after the 1320 * autosuspend delay, turning the power off. 1321 */ 1322 pm_runtime_mark_last_busy(dev); 1323 pm_runtime_put_autosuspend(dev); 1324 1325 return 0; 1326 1327 err_subdev: 1328 imx290_subdev_cleanup(imx290); 1329 err_pm: 1330 pm_runtime_disable(dev); 1331 pm_runtime_put_noidle(dev); 1332 imx290_power_off(imx290); 1333 return ret; 1334 } 1335 1336 static void imx290_remove(struct i2c_client *client) 1337 { 1338 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1339 struct imx290 *imx290 = to_imx290(sd); 1340 1341 v4l2_async_unregister_subdev(sd); 1342 imx290_subdev_cleanup(imx290); 1343 1344 /* 1345 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1346 * make sure to turn power off manually. 1347 */ 1348 pm_runtime_disable(imx290->dev); 1349 if (!pm_runtime_status_suspended(imx290->dev)) 1350 imx290_power_off(imx290); 1351 pm_runtime_set_suspended(imx290->dev); 1352 } 1353 1354 static const struct of_device_id imx290_of_match[] = { 1355 { .compatible = "sony,imx290" }, 1356 { /* sentinel */ } 1357 }; 1358 MODULE_DEVICE_TABLE(of, imx290_of_match); 1359 1360 static struct i2c_driver imx290_i2c_driver = { 1361 .probe_new = imx290_probe, 1362 .remove = imx290_remove, 1363 .driver = { 1364 .name = "imx290", 1365 .pm = pm_ptr(&imx290_pm_ops), 1366 .of_match_table = imx290_of_match, 1367 }, 1368 }; 1369 1370 module_i2c_driver(imx290_i2c_driver); 1371 1372 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1373 MODULE_AUTHOR("FRAMOS GmbH"); 1374 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1375 MODULE_LICENSE("GPL v2"); 1376