1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 20 #include <asm/unaligned.h> 21 22 #include <media/media-entity.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-fwnode.h> 26 #include <media/v4l2-subdev.h> 27 28 #define IMX290_REG_SIZE_SHIFT 16 29 #define IMX290_REG_ADDR_MASK 0xffff 30 #define IMX290_REG_8BIT(n) ((1U << IMX290_REG_SIZE_SHIFT) | (n)) 31 #define IMX290_REG_16BIT(n) ((2U << IMX290_REG_SIZE_SHIFT) | (n)) 32 #define IMX290_REG_24BIT(n) ((3U << IMX290_REG_SIZE_SHIFT) | (n)) 33 34 #define IMX290_STANDBY IMX290_REG_8BIT(0x3000) 35 #define IMX290_REGHOLD IMX290_REG_8BIT(0x3001) 36 #define IMX290_XMSTA IMX290_REG_8BIT(0x3002) 37 #define IMX290_ADBIT IMX290_REG_8BIT(0x3005) 38 #define IMX290_ADBIT_10BIT (0 << 0) 39 #define IMX290_ADBIT_12BIT (1 << 0) 40 #define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007) 41 #define IMX290_VREVERSE BIT(0) 42 #define IMX290_HREVERSE BIT(1) 43 #define IMX290_WINMODE_1080P (0 << 4) 44 #define IMX290_WINMODE_720P (1 << 4) 45 #define IMX290_WINMODE_CROP (4 << 4) 46 #define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009) 47 #define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a) 48 #define IMX290_GAIN IMX290_REG_8BIT(0x3014) 49 #define IMX290_VMAX IMX290_REG_24BIT(0x3018) 50 #define IMX290_HMAX IMX290_REG_16BIT(0x301c) 51 #define IMX290_SHS1 IMX290_REG_24BIT(0x3020) 52 #define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a) 53 #define IMX290_WINPV IMX290_REG_16BIT(0x303c) 54 #define IMX290_WINWV IMX290_REG_16BIT(0x303e) 55 #define IMX290_WINPH IMX290_REG_16BIT(0x3040) 56 #define IMX290_WINWH IMX290_REG_16BIT(0x3042) 57 #define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046) 58 #define IMX290_ODBIT_10BIT (0 << 0) 59 #define IMX290_ODBIT_12BIT (1 << 0) 60 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 61 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 62 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 63 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 64 #define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b) 65 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 66 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 67 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 68 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 69 #define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c) 70 #define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d) 71 #define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e) 72 #define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f) 73 #define IMX290_PGCTRL IMX290_REG_8BIT(0x308c) 74 #define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129) 75 #define IMX290_ADBIT1_10BIT 0x1d 76 #define IMX290_ADBIT1_12BIT 0x00 77 #define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e) 78 #define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164) 79 #define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c) 80 #define IMX290_ADBIT2_10BIT 0x12 81 #define IMX290_ADBIT2_12BIT 0x00 82 #define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a) 83 #define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec) 84 #define IMX290_ADBIT3_10BIT 0x37 85 #define IMX290_ADBIT3_12BIT 0x0e 86 #define IMX290_REPETITION IMX290_REG_8BIT(0x3405) 87 #define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407) 88 #define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414) 89 #define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418) 90 #define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441) 91 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 92 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 93 #define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443) 94 #define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444) 95 #define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446) 96 #define IMX290_THSZERO IMX290_REG_16BIT(0x3448) 97 #define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a) 98 #define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c) 99 #define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e) 100 #define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450) 101 #define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452) 102 #define IMX290_TLPX IMX290_REG_16BIT(0x3454) 103 #define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472) 104 105 #define IMX290_PGCTRL_REGEN BIT(0) 106 #define IMX290_PGCTRL_THRU BIT(1) 107 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 108 109 #define IMX290_VMAX_DEFAULT 1125 110 111 112 /* 113 * The IMX290 pixel array is organized as follows: 114 * 115 * +------------------------------------+ 116 * | Optical Black | } Vertical effective optical black (10) 117 * +---+------------------------------------+---+ 118 * | | | | } Effective top margin (8) 119 * | | +----------------------------+ | | \ 120 * | | | | | | | 121 * | | | | | | | 122 * | | | | | | | 123 * | | | Recording Pixel Area | | | | Recommended height (1080) 124 * | | | | | | | 125 * | | | | | | | 126 * | | | | | | | 127 * | | +----------------------------+ | | / 128 * | | | | } Effective bottom margin (9) 129 * +---+------------------------------------+---+ 130 * <-> <-> <--------------------------> <-> <-> 131 * \---- Ignored right margin (4) 132 * \-------- Effective right margin (9) 133 * \------------------------- Recommended width (1920) 134 * \----------------------------------------- Effective left margin (8) 135 * \--------------------------------------------- Ignored left margin (4) 136 * 137 * The optical black lines are output over CSI-2 with a separate data type. 138 * 139 * The pixel array is meant to have 1920x1080 usable pixels after image 140 * processing in an ISP. It has 8 (9) extra active pixels usable for color 141 * processing in the ISP on the top and left (bottom and right) sides of the 142 * image. In addition, 4 additional pixels are present on the left and right 143 * sides of the image, documented as "ignored area". 144 * 145 * As far as is understood, all pixels of the pixel array (ignored area, color 146 * processing margins and recording area) can be output by the sensor. 147 */ 148 149 #define IMX290_PIXEL_ARRAY_WIDTH 1945 150 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 151 #define IMX920_PIXEL_ARRAY_MARGIN_LEFT 12 152 #define IMX920_PIXEL_ARRAY_MARGIN_RIGHT 13 153 #define IMX920_PIXEL_ARRAY_MARGIN_TOP 8 154 #define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM 9 155 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 156 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 157 158 /* Equivalent value for 16bpp */ 159 #define IMX290_BLACK_LEVEL_DEFAULT 3840 160 161 #define IMX290_NUM_SUPPLIES 3 162 163 struct imx290_regval { 164 u32 reg; 165 u32 val; 166 }; 167 168 struct imx290_mode { 169 u32 width; 170 u32 height; 171 u32 hmax; 172 u8 link_freq_index; 173 174 const struct imx290_regval *data; 175 u32 data_size; 176 }; 177 178 struct imx290 { 179 struct device *dev; 180 struct clk *xclk; 181 struct regmap *regmap; 182 u8 nlanes; 183 184 struct v4l2_subdev sd; 185 struct media_pad pad; 186 187 const struct imx290_mode *current_mode; 188 189 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 190 struct gpio_desc *rst_gpio; 191 192 struct v4l2_ctrl_handler ctrls; 193 struct v4l2_ctrl *link_freq; 194 struct v4l2_ctrl *pixel_rate; 195 struct v4l2_ctrl *hblank; 196 struct v4l2_ctrl *vblank; 197 }; 198 199 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 200 { 201 return container_of(_sd, struct imx290, sd); 202 } 203 204 /* ----------------------------------------------------------------------------- 205 * Modes and formats 206 */ 207 208 static const struct imx290_regval imx290_global_init_settings[] = { 209 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 210 { IMX290_VMAX, IMX290_VMAX_DEFAULT }, 211 { IMX290_EXTCK_FREQ, 0x2520 }, 212 { IMX290_WINWV_OB, 12 }, 213 { IMX290_WINPH, 0 }, 214 { IMX290_WINPV, 0 }, 215 { IMX290_WINWH, 1948 }, 216 { IMX290_WINWV, 1097 }, 217 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 218 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 219 { IMX290_REG_8BIT(0x300f), 0x00 }, 220 { IMX290_REG_8BIT(0x3010), 0x21 }, 221 { IMX290_REG_8BIT(0x3012), 0x64 }, 222 { IMX290_REG_8BIT(0x3013), 0x00 }, 223 { IMX290_REG_8BIT(0x3016), 0x09 }, 224 { IMX290_REG_8BIT(0x3070), 0x02 }, 225 { IMX290_REG_8BIT(0x3071), 0x11 }, 226 { IMX290_REG_8BIT(0x309b), 0x10 }, 227 { IMX290_REG_8BIT(0x309c), 0x22 }, 228 { IMX290_REG_8BIT(0x30a2), 0x02 }, 229 { IMX290_REG_8BIT(0x30a6), 0x20 }, 230 { IMX290_REG_8BIT(0x30a8), 0x20 }, 231 { IMX290_REG_8BIT(0x30aa), 0x20 }, 232 { IMX290_REG_8BIT(0x30ac), 0x20 }, 233 { IMX290_REG_8BIT(0x30b0), 0x43 }, 234 { IMX290_REG_8BIT(0x3119), 0x9e }, 235 { IMX290_REG_8BIT(0x311c), 0x1e }, 236 { IMX290_REG_8BIT(0x311e), 0x08 }, 237 { IMX290_REG_8BIT(0x3128), 0x05 }, 238 { IMX290_REG_8BIT(0x313d), 0x83 }, 239 { IMX290_REG_8BIT(0x3150), 0x03 }, 240 { IMX290_REG_8BIT(0x317e), 0x00 }, 241 { IMX290_REG_8BIT(0x32b8), 0x50 }, 242 { IMX290_REG_8BIT(0x32b9), 0x10 }, 243 { IMX290_REG_8BIT(0x32ba), 0x00 }, 244 { IMX290_REG_8BIT(0x32bb), 0x04 }, 245 { IMX290_REG_8BIT(0x32c8), 0x50 }, 246 { IMX290_REG_8BIT(0x32c9), 0x10 }, 247 { IMX290_REG_8BIT(0x32ca), 0x00 }, 248 { IMX290_REG_8BIT(0x32cb), 0x04 }, 249 { IMX290_REG_8BIT(0x332c), 0xd3 }, 250 { IMX290_REG_8BIT(0x332d), 0x10 }, 251 { IMX290_REG_8BIT(0x332e), 0x0d }, 252 { IMX290_REG_8BIT(0x3358), 0x06 }, 253 { IMX290_REG_8BIT(0x3359), 0xe1 }, 254 { IMX290_REG_8BIT(0x335a), 0x11 }, 255 { IMX290_REG_8BIT(0x3360), 0x1e }, 256 { IMX290_REG_8BIT(0x3361), 0x61 }, 257 { IMX290_REG_8BIT(0x3362), 0x10 }, 258 { IMX290_REG_8BIT(0x33b0), 0x50 }, 259 { IMX290_REG_8BIT(0x33b2), 0x1a }, 260 { IMX290_REG_8BIT(0x33b3), 0x04 }, 261 { IMX290_REG_8BIT(0x3480), 0x49 }, 262 }; 263 264 static const struct imx290_regval imx290_1080p_settings[] = { 265 /* mode settings */ 266 { IMX290_CTRL_07, IMX290_WINMODE_1080P }, 267 { IMX290_WINWV_OB, 12 }, 268 { IMX290_OPB_SIZE_V, 10 }, 269 { IMX290_X_OUT_SIZE, 1920 }, 270 { IMX290_Y_OUT_SIZE, 1080 }, 271 { IMX290_INCKSEL1, 0x18 }, 272 { IMX290_INCKSEL2, 0x03 }, 273 { IMX290_INCKSEL3, 0x20 }, 274 { IMX290_INCKSEL4, 0x01 }, 275 { IMX290_INCKSEL5, 0x1a }, 276 { IMX290_INCKSEL6, 0x1a }, 277 /* data rate settings */ 278 { IMX290_REPETITION, 0x10 }, 279 { IMX290_TCLKPOST, 87 }, 280 { IMX290_THSZERO, 55 }, 281 { IMX290_THSPREPARE, 31 }, 282 { IMX290_TCLKTRAIL, 31 }, 283 { IMX290_THSTRAIL, 31 }, 284 { IMX290_TCLKZERO, 119 }, 285 { IMX290_TCLKPREPARE, 31 }, 286 { IMX290_TLPX, 23 }, 287 }; 288 289 static const struct imx290_regval imx290_720p_settings[] = { 290 /* mode settings */ 291 { IMX290_CTRL_07, IMX290_WINMODE_720P }, 292 { IMX290_WINWV_OB, 6 }, 293 { IMX290_OPB_SIZE_V, 4 }, 294 { IMX290_X_OUT_SIZE, 1280 }, 295 { IMX290_Y_OUT_SIZE, 720 }, 296 { IMX290_INCKSEL1, 0x20 }, 297 { IMX290_INCKSEL2, 0x00 }, 298 { IMX290_INCKSEL3, 0x20 }, 299 { IMX290_INCKSEL4, 0x01 }, 300 { IMX290_INCKSEL5, 0x1a }, 301 { IMX290_INCKSEL6, 0x1a }, 302 /* data rate settings */ 303 { IMX290_REPETITION, 0x10 }, 304 { IMX290_TCLKPOST, 79 }, 305 { IMX290_THSZERO, 47 }, 306 { IMX290_THSPREPARE, 23 }, 307 { IMX290_TCLKTRAIL, 23 }, 308 { IMX290_THSTRAIL, 23 }, 309 { IMX290_TCLKZERO, 87 }, 310 { IMX290_TCLKPREPARE, 23 }, 311 { IMX290_TLPX, 23 }, 312 }; 313 314 static const struct imx290_regval imx290_10bit_settings[] = { 315 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 316 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 317 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 318 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 319 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 320 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 321 }; 322 323 static const struct imx290_regval imx290_12bit_settings[] = { 324 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 325 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 326 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 327 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 328 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 329 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 330 }; 331 332 /* supported link frequencies */ 333 #define FREQ_INDEX_1080P 0 334 #define FREQ_INDEX_720P 1 335 static const s64 imx290_link_freq_2lanes[] = { 336 [FREQ_INDEX_1080P] = 445500000, 337 [FREQ_INDEX_720P] = 297000000, 338 }; 339 static const s64 imx290_link_freq_4lanes[] = { 340 [FREQ_INDEX_1080P] = 222750000, 341 [FREQ_INDEX_720P] = 148500000, 342 }; 343 344 /* 345 * In this function and in the similar ones below We rely on imx290_probe() 346 * to ensure that nlanes is either 2 or 4. 347 */ 348 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 349 { 350 if (imx290->nlanes == 2) 351 return imx290_link_freq_2lanes; 352 else 353 return imx290_link_freq_4lanes; 354 } 355 356 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 357 { 358 if (imx290->nlanes == 2) 359 return ARRAY_SIZE(imx290_link_freq_2lanes); 360 else 361 return ARRAY_SIZE(imx290_link_freq_4lanes); 362 } 363 364 /* Mode configs */ 365 static const struct imx290_mode imx290_modes_2lanes[] = { 366 { 367 .width = 1920, 368 .height = 1080, 369 .hmax = 4400, 370 .link_freq_index = FREQ_INDEX_1080P, 371 .data = imx290_1080p_settings, 372 .data_size = ARRAY_SIZE(imx290_1080p_settings), 373 }, 374 { 375 .width = 1280, 376 .height = 720, 377 .hmax = 6600, 378 .link_freq_index = FREQ_INDEX_720P, 379 .data = imx290_720p_settings, 380 .data_size = ARRAY_SIZE(imx290_720p_settings), 381 }, 382 }; 383 384 static const struct imx290_mode imx290_modes_4lanes[] = { 385 { 386 .width = 1920, 387 .height = 1080, 388 .hmax = 2200, 389 .link_freq_index = FREQ_INDEX_1080P, 390 .data = imx290_1080p_settings, 391 .data_size = ARRAY_SIZE(imx290_1080p_settings), 392 }, 393 { 394 .width = 1280, 395 .height = 720, 396 .hmax = 3300, 397 .link_freq_index = FREQ_INDEX_720P, 398 .data = imx290_720p_settings, 399 .data_size = ARRAY_SIZE(imx290_720p_settings), 400 }, 401 }; 402 403 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 404 { 405 if (imx290->nlanes == 2) 406 return imx290_modes_2lanes; 407 else 408 return imx290_modes_4lanes; 409 } 410 411 static inline int imx290_modes_num(const struct imx290 *imx290) 412 { 413 if (imx290->nlanes == 2) 414 return ARRAY_SIZE(imx290_modes_2lanes); 415 else 416 return ARRAY_SIZE(imx290_modes_4lanes); 417 } 418 419 struct imx290_format_info { 420 u32 code; 421 u8 bpp; 422 const struct imx290_regval *regs; 423 unsigned int num_regs; 424 }; 425 426 static const struct imx290_format_info imx290_formats[] = { 427 { 428 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 429 .bpp = 10, 430 .regs = imx290_10bit_settings, 431 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 432 }, { 433 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 434 .bpp = 12, 435 .regs = imx290_12bit_settings, 436 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 437 } 438 }; 439 440 static const struct imx290_format_info *imx290_format_info(u32 code) 441 { 442 unsigned int i; 443 444 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 445 const struct imx290_format_info *info = &imx290_formats[i]; 446 447 if (info->code == code) 448 return info; 449 } 450 451 return NULL; 452 } 453 454 /* ----------------------------------------------------------------------------- 455 * Register access 456 */ 457 458 static int __always_unused imx290_read(struct imx290 *imx290, u32 addr, u32 *value) 459 { 460 u8 data[3] = { 0, 0, 0 }; 461 int ret; 462 463 ret = regmap_raw_read(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 464 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 465 if (ret < 0) { 466 dev_err(imx290->dev, "%u-bit read from 0x%04x failed: %d\n", 467 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 468 addr & IMX290_REG_ADDR_MASK, ret); 469 return ret; 470 } 471 472 *value = get_unaligned_le24(data); 473 return 0; 474 } 475 476 static int imx290_write(struct imx290 *imx290, u32 addr, u32 value, int *err) 477 { 478 u8 data[3]; 479 int ret; 480 481 if (err && *err) 482 return *err; 483 484 put_unaligned_le24(value, data); 485 486 ret = regmap_raw_write(imx290->regmap, addr & IMX290_REG_ADDR_MASK, 487 data, (addr >> IMX290_REG_SIZE_SHIFT) & 3); 488 if (ret < 0) { 489 dev_err(imx290->dev, "%u-bit write to 0x%04x failed: %d\n", 490 ((addr >> IMX290_REG_SIZE_SHIFT) & 3) * 8, 491 addr & IMX290_REG_ADDR_MASK, ret); 492 if (err) 493 *err = ret; 494 } 495 496 return ret; 497 } 498 499 static int imx290_set_register_array(struct imx290 *imx290, 500 const struct imx290_regval *settings, 501 unsigned int num_settings) 502 { 503 unsigned int i; 504 int ret; 505 506 for (i = 0; i < num_settings; ++i, ++settings) { 507 ret = imx290_write(imx290, settings->reg, settings->val, NULL); 508 if (ret < 0) 509 return ret; 510 } 511 512 /* Provide 10ms settle time */ 513 usleep_range(10000, 11000); 514 515 return 0; 516 } 517 518 static int imx290_set_data_lanes(struct imx290 *imx290) 519 { 520 int ret = 0; 521 u32 frsel; 522 523 switch (imx290->nlanes) { 524 case 2: 525 default: 526 frsel = 0x02; 527 break; 528 case 4: 529 frsel = 0x01; 530 break; 531 } 532 533 imx290_write(imx290, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, &ret); 534 imx290_write(imx290, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, &ret); 535 imx290_write(imx290, IMX290_FR_FDG_SEL, frsel, &ret); 536 537 return ret; 538 } 539 540 static int imx290_set_black_level(struct imx290 *imx290, 541 const struct v4l2_mbus_framefmt *format, 542 unsigned int black_level, int *err) 543 { 544 unsigned int bpp = imx290_format_info(format->code)->bpp; 545 546 return imx290_write(imx290, IMX290_BLKLEVEL, 547 black_level >> (16 - bpp), err); 548 } 549 550 static int imx290_setup_format(struct imx290 *imx290, 551 const struct v4l2_mbus_framefmt *format) 552 { 553 const struct imx290_format_info *info; 554 int ret; 555 556 info = imx290_format_info(format->code); 557 558 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 559 if (ret < 0) { 560 dev_err(imx290->dev, "Could not set format registers\n"); 561 return ret; 562 } 563 564 return imx290_set_black_level(imx290, format, 565 IMX290_BLACK_LEVEL_DEFAULT, &ret); 566 } 567 568 /* ---------------------------------------------------------------------------- 569 * Controls 570 */ 571 572 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 573 { 574 struct imx290 *imx290 = container_of(ctrl->handler, 575 struct imx290, ctrls); 576 const struct v4l2_mbus_framefmt *format; 577 struct v4l2_subdev_state *state; 578 int ret = 0; 579 580 /* 581 * Return immediately for controls that don't need to be applied to the 582 * device. 583 */ 584 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 585 return 0; 586 587 /* V4L2 controls values will be applied only when power is already up */ 588 if (!pm_runtime_get_if_in_use(imx290->dev)) 589 return 0; 590 591 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 592 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 593 594 switch (ctrl->id) { 595 case V4L2_CID_ANALOGUE_GAIN: 596 ret = imx290_write(imx290, IMX290_GAIN, ctrl->val, NULL); 597 break; 598 599 case V4L2_CID_EXPOSURE: 600 ret = imx290_write(imx290, IMX290_SHS1, 601 IMX290_VMAX_DEFAULT - ctrl->val - 1, NULL); 602 break; 603 604 case V4L2_CID_TEST_PATTERN: 605 if (ctrl->val) { 606 imx290_set_black_level(imx290, format, 0, &ret); 607 usleep_range(10000, 11000); 608 imx290_write(imx290, IMX290_PGCTRL, 609 (u8)(IMX290_PGCTRL_REGEN | 610 IMX290_PGCTRL_THRU | 611 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 612 } else { 613 imx290_write(imx290, IMX290_PGCTRL, 0x00, &ret); 614 usleep_range(10000, 11000); 615 imx290_set_black_level(imx290, format, 616 IMX290_BLACK_LEVEL_DEFAULT, &ret); 617 } 618 break; 619 620 default: 621 ret = -EINVAL; 622 break; 623 } 624 625 pm_runtime_mark_last_busy(imx290->dev); 626 pm_runtime_put_autosuspend(imx290->dev); 627 628 return ret; 629 } 630 631 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 632 .s_ctrl = imx290_set_ctrl, 633 }; 634 635 static const char * const imx290_test_pattern_menu[] = { 636 "Disabled", 637 "Sequence Pattern 1", 638 "Horizontal Color-bar Chart", 639 "Vertical Color-bar Chart", 640 "Sequence Pattern 2", 641 "Gradation Pattern 1", 642 "Gradation Pattern 2", 643 "000/555h Toggle Pattern", 644 }; 645 646 static void imx290_ctrl_update(struct imx290 *imx290, 647 const struct v4l2_mbus_framefmt *format, 648 const struct imx290_mode *mode) 649 { 650 unsigned int hblank = mode->hmax - mode->width; 651 unsigned int vblank = IMX290_VMAX_DEFAULT - mode->height; 652 s64 link_freq = imx290_link_freqs_ptr(imx290)[mode->link_freq_index]; 653 u64 pixel_rate; 654 655 /* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */ 656 pixel_rate = link_freq * 2 * imx290->nlanes; 657 do_div(pixel_rate, imx290_format_info(format->code)->bpp); 658 659 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 660 __v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate, pixel_rate); 661 662 __v4l2_ctrl_modify_range(imx290->hblank, hblank, hblank, 1, hblank); 663 __v4l2_ctrl_modify_range(imx290->vblank, vblank, vblank, 1, vblank); 664 } 665 666 static int imx290_ctrl_init(struct imx290 *imx290) 667 { 668 struct v4l2_fwnode_device_properties props; 669 int ret; 670 671 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 672 if (ret < 0) 673 return ret; 674 675 v4l2_ctrl_handler_init(&imx290->ctrls, 9); 676 677 /* 678 * The sensor has an analog gain and a digital gain, both controlled 679 * through a single gain value, expressed in 0.3dB increments. Values 680 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 681 * up to 72.0dB (240) add further digital gain. Limit the range to 682 * analog gain only, support for digital gain can be added separately 683 * if needed. 684 * 685 * The IMX327 and IMX462 are largely compatible with the IMX290, but 686 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 687 * gain. When support for those sensors gets added to the driver, the 688 * gain control should be adjusted accordingly. 689 */ 690 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 691 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 692 693 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 694 V4L2_CID_EXPOSURE, 1, IMX290_VMAX_DEFAULT - 2, 1, 695 IMX290_VMAX_DEFAULT - 2); 696 697 /* 698 * Set the link frequency, pixel rate, horizontal blanking and vertical 699 * blanking to hardcoded values, they will be updated by 700 * imx290_ctrl_update(). 701 */ 702 imx290->link_freq = 703 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 704 V4L2_CID_LINK_FREQ, 705 imx290_link_freqs_num(imx290) - 1, 0, 706 imx290_link_freqs_ptr(imx290)); 707 if (imx290->link_freq) 708 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 709 710 imx290->pixel_rate = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 711 V4L2_CID_PIXEL_RATE, 712 1, INT_MAX, 1, 1); 713 714 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 715 V4L2_CID_TEST_PATTERN, 716 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 717 0, 0, imx290_test_pattern_menu); 718 719 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 720 V4L2_CID_HBLANK, 1, 1, 1, 1); 721 if (imx290->hblank) 722 imx290->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 723 724 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 725 V4L2_CID_VBLANK, 1, 1, 1, 1); 726 if (imx290->vblank) 727 imx290->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 728 729 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 730 &props); 731 732 imx290->sd.ctrl_handler = &imx290->ctrls; 733 734 if (imx290->ctrls.error) { 735 ret = imx290->ctrls.error; 736 v4l2_ctrl_handler_free(&imx290->ctrls); 737 return ret; 738 } 739 740 return 0; 741 } 742 743 /* ---------------------------------------------------------------------------- 744 * Subdev operations 745 */ 746 747 /* Start streaming */ 748 static int imx290_start_streaming(struct imx290 *imx290, 749 struct v4l2_subdev_state *state) 750 { 751 const struct v4l2_mbus_framefmt *format; 752 int ret; 753 754 /* Set init register settings */ 755 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 756 ARRAY_SIZE( 757 imx290_global_init_settings)); 758 if (ret < 0) { 759 dev_err(imx290->dev, "Could not set init registers\n"); 760 return ret; 761 } 762 763 /* Set data lane count */ 764 ret = imx290_set_data_lanes(imx290); 765 if (ret < 0) { 766 dev_err(imx290->dev, "Could not set data lanes\n"); 767 return ret; 768 } 769 770 /* Apply the register values related to current frame format */ 771 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 772 ret = imx290_setup_format(imx290, format); 773 if (ret < 0) { 774 dev_err(imx290->dev, "Could not set frame format\n"); 775 return ret; 776 } 777 778 /* Apply default values of current mode */ 779 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 780 imx290->current_mode->data_size); 781 if (ret < 0) { 782 dev_err(imx290->dev, "Could not set current mode\n"); 783 return ret; 784 } 785 786 ret = imx290_write(imx290, IMX290_HMAX, imx290->current_mode->hmax, 787 NULL); 788 if (ret) 789 return ret; 790 791 /* Apply customized values from user */ 792 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 793 if (ret) { 794 dev_err(imx290->dev, "Could not sync v4l2 controls\n"); 795 return ret; 796 } 797 798 imx290_write(imx290, IMX290_STANDBY, 0x00, &ret); 799 800 msleep(30); 801 802 /* Start streaming */ 803 return imx290_write(imx290, IMX290_XMSTA, 0x00, &ret); 804 } 805 806 /* Stop streaming */ 807 static int imx290_stop_streaming(struct imx290 *imx290) 808 { 809 int ret = 0; 810 811 imx290_write(imx290, IMX290_STANDBY, 0x01, &ret); 812 813 msleep(30); 814 815 return imx290_write(imx290, IMX290_XMSTA, 0x01, &ret); 816 } 817 818 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 819 { 820 struct imx290 *imx290 = to_imx290(sd); 821 struct v4l2_subdev_state *state; 822 int ret = 0; 823 824 state = v4l2_subdev_lock_and_get_active_state(sd); 825 826 if (enable) { 827 ret = pm_runtime_resume_and_get(imx290->dev); 828 if (ret < 0) 829 goto unlock; 830 831 ret = imx290_start_streaming(imx290, state); 832 if (ret) { 833 dev_err(imx290->dev, "Start stream failed\n"); 834 pm_runtime_put_sync(imx290->dev); 835 goto unlock; 836 } 837 } else { 838 imx290_stop_streaming(imx290); 839 pm_runtime_mark_last_busy(imx290->dev); 840 pm_runtime_put_autosuspend(imx290->dev); 841 } 842 843 unlock: 844 v4l2_subdev_unlock_state(state); 845 return ret; 846 } 847 848 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 849 struct v4l2_subdev_state *sd_state, 850 struct v4l2_subdev_mbus_code_enum *code) 851 { 852 if (code->index >= ARRAY_SIZE(imx290_formats)) 853 return -EINVAL; 854 855 code->code = imx290_formats[code->index].code; 856 857 return 0; 858 } 859 860 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 861 struct v4l2_subdev_state *sd_state, 862 struct v4l2_subdev_frame_size_enum *fse) 863 { 864 const struct imx290 *imx290 = to_imx290(sd); 865 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 866 867 if (!imx290_format_info(fse->code)) 868 return -EINVAL; 869 870 if (fse->index >= imx290_modes_num(imx290)) 871 return -EINVAL; 872 873 fse->min_width = imx290_modes[fse->index].width; 874 fse->max_width = imx290_modes[fse->index].width; 875 fse->min_height = imx290_modes[fse->index].height; 876 fse->max_height = imx290_modes[fse->index].height; 877 878 return 0; 879 } 880 881 static int imx290_set_fmt(struct v4l2_subdev *sd, 882 struct v4l2_subdev_state *sd_state, 883 struct v4l2_subdev_format *fmt) 884 { 885 struct imx290 *imx290 = to_imx290(sd); 886 const struct imx290_mode *mode; 887 struct v4l2_mbus_framefmt *format; 888 889 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 890 imx290_modes_num(imx290), width, height, 891 fmt->format.width, fmt->format.height); 892 893 fmt->format.width = mode->width; 894 fmt->format.height = mode->height; 895 896 if (!imx290_format_info(fmt->format.code)) 897 fmt->format.code = imx290_formats[0].code; 898 899 fmt->format.field = V4L2_FIELD_NONE; 900 901 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 902 903 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 904 imx290->current_mode = mode; 905 906 imx290_ctrl_update(imx290, &fmt->format, mode); 907 } 908 909 *format = fmt->format; 910 911 return 0; 912 } 913 914 static int imx290_get_selection(struct v4l2_subdev *sd, 915 struct v4l2_subdev_state *sd_state, 916 struct v4l2_subdev_selection *sel) 917 { 918 struct v4l2_mbus_framefmt *format; 919 920 switch (sel->target) { 921 case V4L2_SEL_TGT_CROP: { 922 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 923 924 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP 925 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2; 926 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT 927 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2; 928 sel->r.width = format->width; 929 sel->r.height = format->height; 930 931 return 0; 932 } 933 934 case V4L2_SEL_TGT_NATIVE_SIZE: 935 case V4L2_SEL_TGT_CROP_BOUNDS: 936 sel->r.top = 0; 937 sel->r.left = 0; 938 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 939 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 940 941 return 0; 942 943 case V4L2_SEL_TGT_CROP_DEFAULT: 944 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP; 945 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT; 946 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 947 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 948 949 return 0; 950 951 default: 952 return -EINVAL; 953 } 954 } 955 956 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 957 struct v4l2_subdev_state *sd_state) 958 { 959 struct v4l2_subdev_format fmt = { 960 .which = V4L2_SUBDEV_FORMAT_TRY, 961 .format = { 962 .width = 1920, 963 .height = 1080, 964 }, 965 }; 966 967 imx290_set_fmt(subdev, sd_state, &fmt); 968 969 return 0; 970 } 971 972 static const struct v4l2_subdev_video_ops imx290_video_ops = { 973 .s_stream = imx290_set_stream, 974 }; 975 976 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 977 .init_cfg = imx290_entity_init_cfg, 978 .enum_mbus_code = imx290_enum_mbus_code, 979 .enum_frame_size = imx290_enum_frame_size, 980 .get_fmt = v4l2_subdev_get_fmt, 981 .set_fmt = imx290_set_fmt, 982 .get_selection = imx290_get_selection, 983 }; 984 985 static const struct v4l2_subdev_ops imx290_subdev_ops = { 986 .video = &imx290_video_ops, 987 .pad = &imx290_pad_ops, 988 }; 989 990 static const struct media_entity_operations imx290_subdev_entity_ops = { 991 .link_validate = v4l2_subdev_link_validate, 992 }; 993 994 static int imx290_subdev_init(struct imx290 *imx290) 995 { 996 struct i2c_client *client = to_i2c_client(imx290->dev); 997 const struct v4l2_mbus_framefmt *format; 998 struct v4l2_subdev_state *state; 999 int ret; 1000 1001 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1002 1003 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1004 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1005 imx290->sd.dev = imx290->dev; 1006 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1007 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1008 1009 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1010 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1011 if (ret < 0) { 1012 dev_err(imx290->dev, "Could not register media entity\n"); 1013 return ret; 1014 } 1015 1016 ret = imx290_ctrl_init(imx290); 1017 if (ret < 0) { 1018 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1019 goto err_media; 1020 } 1021 1022 imx290->sd.state_lock = imx290->ctrls.lock; 1023 1024 ret = v4l2_subdev_init_finalize(&imx290->sd); 1025 if (ret < 0) { 1026 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1027 goto err_ctrls; 1028 } 1029 1030 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1031 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 1032 imx290_ctrl_update(imx290, format, imx290->current_mode); 1033 v4l2_subdev_unlock_state(state); 1034 1035 return 0; 1036 1037 err_ctrls: 1038 v4l2_ctrl_handler_free(&imx290->ctrls); 1039 err_media: 1040 media_entity_cleanup(&imx290->sd.entity); 1041 return ret; 1042 } 1043 1044 static void imx290_subdev_cleanup(struct imx290 *imx290) 1045 { 1046 v4l2_subdev_cleanup(&imx290->sd); 1047 media_entity_cleanup(&imx290->sd.entity); 1048 v4l2_ctrl_handler_free(&imx290->ctrls); 1049 } 1050 1051 /* ---------------------------------------------------------------------------- 1052 * Power management 1053 */ 1054 1055 static int imx290_power_on(struct imx290 *imx290) 1056 { 1057 int ret; 1058 1059 ret = clk_prepare_enable(imx290->xclk); 1060 if (ret) { 1061 dev_err(imx290->dev, "Failed to enable clock\n"); 1062 return ret; 1063 } 1064 1065 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1066 imx290->supplies); 1067 if (ret) { 1068 dev_err(imx290->dev, "Failed to enable regulators\n"); 1069 clk_disable_unprepare(imx290->xclk); 1070 return ret; 1071 } 1072 1073 usleep_range(1, 2); 1074 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1075 usleep_range(30000, 31000); 1076 1077 return 0; 1078 } 1079 1080 static void imx290_power_off(struct imx290 *imx290) 1081 { 1082 clk_disable_unprepare(imx290->xclk); 1083 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1084 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1085 } 1086 1087 static int imx290_runtime_resume(struct device *dev) 1088 { 1089 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1090 struct imx290 *imx290 = to_imx290(sd); 1091 1092 return imx290_power_on(imx290); 1093 } 1094 1095 static int imx290_runtime_suspend(struct device *dev) 1096 { 1097 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1098 struct imx290 *imx290 = to_imx290(sd); 1099 1100 imx290_power_off(imx290); 1101 1102 return 0; 1103 } 1104 1105 static const struct dev_pm_ops imx290_pm_ops = { 1106 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1107 }; 1108 1109 /* ---------------------------------------------------------------------------- 1110 * Probe & remove 1111 */ 1112 1113 static const struct regmap_config imx290_regmap_config = { 1114 .reg_bits = 16, 1115 .val_bits = 8, 1116 }; 1117 1118 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1119 "vdda", 1120 "vddd", 1121 "vdddo", 1122 }; 1123 1124 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1125 { 1126 unsigned int i; 1127 1128 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1129 imx290->supplies[i].supply = imx290_supply_name[i]; 1130 1131 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1132 imx290->supplies); 1133 } 1134 1135 static int imx290_init_clk(struct imx290 *imx290) 1136 { 1137 u32 xclk_freq; 1138 int ret; 1139 1140 ret = fwnode_property_read_u32(dev_fwnode(imx290->dev), 1141 "clock-frequency", &xclk_freq); 1142 if (ret) { 1143 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1144 return ret; 1145 } 1146 1147 /* external clock must be 37.125 MHz */ 1148 if (xclk_freq != 37125000) { 1149 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1150 xclk_freq); 1151 return -EINVAL; 1152 } 1153 1154 ret = clk_set_rate(imx290->xclk, xclk_freq); 1155 if (ret) { 1156 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1157 return ret; 1158 } 1159 1160 return 0; 1161 } 1162 1163 /* 1164 * Returns 0 if all link frequencies used by the driver for the given number 1165 * of MIPI data lanes are mentioned in the device tree, or the value of the 1166 * first missing frequency otherwise. 1167 */ 1168 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1169 const struct v4l2_fwnode_endpoint *ep) 1170 { 1171 int i, j; 1172 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1173 int freqs_count = imx290_link_freqs_num(imx290); 1174 1175 for (i = 0; i < freqs_count; i++) { 1176 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1177 if (freqs[i] == ep->link_frequencies[j]) 1178 break; 1179 if (j == ep->nr_of_link_frequencies) 1180 return freqs[i]; 1181 } 1182 return 0; 1183 } 1184 1185 static int imx290_parse_dt(struct imx290 *imx290) 1186 { 1187 /* Only CSI2 is supported for now: */ 1188 struct v4l2_fwnode_endpoint ep = { 1189 .bus_type = V4L2_MBUS_CSI2_DPHY 1190 }; 1191 struct fwnode_handle *endpoint; 1192 int ret; 1193 s64 fq; 1194 1195 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1196 if (!endpoint) { 1197 dev_err(imx290->dev, "Endpoint node not found\n"); 1198 return -EINVAL; 1199 } 1200 1201 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1202 fwnode_handle_put(endpoint); 1203 if (ret == -ENXIO) { 1204 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1205 goto done; 1206 } else if (ret) { 1207 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1208 goto done; 1209 } 1210 1211 /* Get number of data lanes */ 1212 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1213 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1214 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1215 ret = -EINVAL; 1216 goto done; 1217 } 1218 1219 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1220 1221 if (!ep.nr_of_link_frequencies) { 1222 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1223 ret = -EINVAL; 1224 goto done; 1225 } 1226 1227 /* Check that link frequences for all the modes are in device tree */ 1228 fq = imx290_check_link_freqs(imx290, &ep); 1229 if (fq) { 1230 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1231 fq); 1232 ret = -EINVAL; 1233 goto done; 1234 } 1235 1236 ret = 0; 1237 1238 done: 1239 v4l2_fwnode_endpoint_free(&ep); 1240 return ret; 1241 } 1242 1243 static int imx290_probe(struct i2c_client *client) 1244 { 1245 struct device *dev = &client->dev; 1246 struct imx290 *imx290; 1247 int ret; 1248 1249 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1250 if (!imx290) 1251 return -ENOMEM; 1252 1253 imx290->dev = dev; 1254 imx290->regmap = devm_regmap_init_i2c(client, &imx290_regmap_config); 1255 if (IS_ERR(imx290->regmap)) { 1256 dev_err(dev, "Unable to initialize I2C\n"); 1257 return -ENODEV; 1258 } 1259 1260 ret = imx290_parse_dt(imx290); 1261 if (ret) 1262 return ret; 1263 1264 /* Acquire resources. */ 1265 imx290->xclk = devm_clk_get(dev, "xclk"); 1266 if (IS_ERR(imx290->xclk)) 1267 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1268 "Could not get xclk"); 1269 1270 ret = imx290_get_regulators(dev, imx290); 1271 if (ret < 0) 1272 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1273 1274 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1275 GPIOD_OUT_HIGH); 1276 if (IS_ERR(imx290->rst_gpio)) 1277 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1278 "Cannot get reset gpio\n"); 1279 1280 /* Initialize external clock frequency. */ 1281 ret = imx290_init_clk(imx290); 1282 if (ret) 1283 return ret; 1284 1285 /* 1286 * Enable power management. The driver supports runtime PM, but needs to 1287 * work when runtime PM is disabled in the kernel. To that end, power 1288 * the sensor on manually here. 1289 */ 1290 ret = imx290_power_on(imx290); 1291 if (ret < 0) { 1292 dev_err(dev, "Could not power on the device\n"); 1293 return ret; 1294 } 1295 1296 /* 1297 * Enable runtime PM with autosuspend. As the device has been powered 1298 * manually, mark it as active, and increase the usage count without 1299 * resuming the device. 1300 */ 1301 pm_runtime_set_active(dev); 1302 pm_runtime_get_noresume(dev); 1303 pm_runtime_enable(dev); 1304 pm_runtime_set_autosuspend_delay(dev, 1000); 1305 pm_runtime_use_autosuspend(dev); 1306 1307 /* Initialize the V4L2 subdev. */ 1308 ret = imx290_subdev_init(imx290); 1309 if (ret) 1310 goto err_pm; 1311 1312 /* 1313 * Finally, register the V4L2 subdev. This must be done after 1314 * initializing everything as the subdev can be used immediately after 1315 * being registered. 1316 */ 1317 ret = v4l2_async_register_subdev(&imx290->sd); 1318 if (ret < 0) { 1319 dev_err(dev, "Could not register v4l2 device\n"); 1320 goto err_subdev; 1321 } 1322 1323 /* 1324 * Decrease the PM usage count. The device will get suspended after the 1325 * autosuspend delay, turning the power off. 1326 */ 1327 pm_runtime_mark_last_busy(dev); 1328 pm_runtime_put_autosuspend(dev); 1329 1330 return 0; 1331 1332 err_subdev: 1333 imx290_subdev_cleanup(imx290); 1334 err_pm: 1335 pm_runtime_disable(dev); 1336 pm_runtime_put_noidle(dev); 1337 imx290_power_off(imx290); 1338 return ret; 1339 } 1340 1341 static void imx290_remove(struct i2c_client *client) 1342 { 1343 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1344 struct imx290 *imx290 = to_imx290(sd); 1345 1346 v4l2_async_unregister_subdev(sd); 1347 imx290_subdev_cleanup(imx290); 1348 1349 /* 1350 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1351 * make sure to turn power off manually. 1352 */ 1353 pm_runtime_disable(imx290->dev); 1354 if (!pm_runtime_status_suspended(imx290->dev)) 1355 imx290_power_off(imx290); 1356 pm_runtime_set_suspended(imx290->dev); 1357 } 1358 1359 static const struct of_device_id imx290_of_match[] = { 1360 { .compatible = "sony,imx290" }, 1361 { /* sentinel */ } 1362 }; 1363 MODULE_DEVICE_TABLE(of, imx290_of_match); 1364 1365 static struct i2c_driver imx290_i2c_driver = { 1366 .probe_new = imx290_probe, 1367 .remove = imx290_remove, 1368 .driver = { 1369 .name = "imx290", 1370 .pm = pm_ptr(&imx290_pm_ops), 1371 .of_match_table = imx290_of_match, 1372 }, 1373 }; 1374 1375 module_i2c_driver(imx290_i2c_driver); 1376 1377 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1378 MODULE_AUTHOR("FRAMOS GmbH"); 1379 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1380 MODULE_LICENSE("GPL v2"); 1381