1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sony IMX290 CMOS Image Sensor Driver 4 * 5 * Copyright (C) 2019 FRAMOS GmbH. 6 * 7 * Copyright (C) 2019 Linaro Ltd. 8 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/unaligned.h> 22 23 #include <media/media-entity.h> 24 #include <media/v4l2-cci.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-device.h> 27 #include <media/v4l2-event.h> 28 #include <media/v4l2-fwnode.h> 29 #include <media/v4l2-subdev.h> 30 31 #define IMX290_STANDBY CCI_REG8(0x3000) 32 #define IMX290_REGHOLD CCI_REG8(0x3001) 33 #define IMX290_XMSTA CCI_REG8(0x3002) 34 #define IMX290_ADBIT CCI_REG8(0x3005) 35 #define IMX290_ADBIT_10BIT (0 << 0) 36 #define IMX290_ADBIT_12BIT (1 << 0) 37 #define IMX290_CTRL_07 CCI_REG8(0x3007) 38 #define IMX290_VREVERSE BIT(0) 39 #define IMX290_HREVERSE BIT(1) 40 #define IMX290_WINMODE_1080P (0 << 4) 41 #define IMX290_WINMODE_720P (1 << 4) 42 #define IMX290_WINMODE_CROP (4 << 4) 43 #define IMX290_FR_FDG_SEL CCI_REG8(0x3009) 44 #define IMX290_BLKLEVEL CCI_REG16_LE(0x300a) 45 #define IMX290_GAIN CCI_REG8(0x3014) 46 #define IMX290_VMAX CCI_REG24_LE(0x3018) 47 #define IMX290_VMAX_MAX 0x3ffff 48 #define IMX290_HMAX CCI_REG16_LE(0x301c) 49 #define IMX290_HMAX_MAX 0xffff 50 #define IMX290_SHS1 CCI_REG24_LE(0x3020) 51 #define IMX290_WINWV_OB CCI_REG8(0x303a) 52 #define IMX290_WINPV CCI_REG16_LE(0x303c) 53 #define IMX290_WINWV CCI_REG16_LE(0x303e) 54 #define IMX290_WINPH CCI_REG16_LE(0x3040) 55 #define IMX290_WINWH CCI_REG16_LE(0x3042) 56 #define IMX290_OUT_CTRL CCI_REG8(0x3046) 57 #define IMX290_ODBIT_10BIT (0 << 0) 58 #define IMX290_ODBIT_12BIT (1 << 0) 59 #define IMX290_OPORTSEL_PARALLEL (0x0 << 4) 60 #define IMX290_OPORTSEL_LVDS_2CH (0xd << 4) 61 #define IMX290_OPORTSEL_LVDS_4CH (0xe << 4) 62 #define IMX290_OPORTSEL_LVDS_8CH (0xf << 4) 63 #define IMX290_XSOUTSEL CCI_REG8(0x304b) 64 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0) 65 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0) 66 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2) 67 #define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2) 68 #define IMX290_INCKSEL1 CCI_REG8(0x305c) 69 #define IMX290_INCKSEL2 CCI_REG8(0x305d) 70 #define IMX290_INCKSEL3 CCI_REG8(0x305e) 71 #define IMX290_INCKSEL4 CCI_REG8(0x305f) 72 #define IMX290_PGCTRL CCI_REG8(0x308c) 73 #define IMX290_ADBIT1 CCI_REG8(0x3129) 74 #define IMX290_ADBIT1_10BIT 0x1d 75 #define IMX290_ADBIT1_12BIT 0x00 76 #define IMX290_INCKSEL5 CCI_REG8(0x315e) 77 #define IMX290_INCKSEL6 CCI_REG8(0x3164) 78 #define IMX290_ADBIT2 CCI_REG8(0x317c) 79 #define IMX290_ADBIT2_10BIT 0x12 80 #define IMX290_ADBIT2_12BIT 0x00 81 #define IMX290_CHIP_ID CCI_REG16_LE(0x319a) 82 #define IMX290_ADBIT3 CCI_REG8(0x31ec) 83 #define IMX290_ADBIT3_10BIT 0x37 84 #define IMX290_ADBIT3_12BIT 0x0e 85 #define IMX290_REPETITION CCI_REG8(0x3405) 86 #define IMX290_PHY_LANE_NUM CCI_REG8(0x3407) 87 #define IMX290_OPB_SIZE_V CCI_REG8(0x3414) 88 #define IMX290_Y_OUT_SIZE CCI_REG16_LE(0x3418) 89 #define IMX290_CSI_DT_FMT CCI_REG16_LE(0x3441) 90 #define IMX290_CSI_DT_FMT_RAW10 0x0a0a 91 #define IMX290_CSI_DT_FMT_RAW12 0x0c0c 92 #define IMX290_CSI_LANE_MODE CCI_REG8(0x3443) 93 #define IMX290_EXTCK_FREQ CCI_REG16_LE(0x3444) 94 #define IMX290_TCLKPOST CCI_REG16_LE(0x3446) 95 #define IMX290_THSZERO CCI_REG16_LE(0x3448) 96 #define IMX290_THSPREPARE CCI_REG16_LE(0x344a) 97 #define IMX290_TCLKTRAIL CCI_REG16_LE(0x344c) 98 #define IMX290_THSTRAIL CCI_REG16_LE(0x344e) 99 #define IMX290_TCLKZERO CCI_REG16_LE(0x3450) 100 #define IMX290_TCLKPREPARE CCI_REG16_LE(0x3452) 101 #define IMX290_TLPX CCI_REG16_LE(0x3454) 102 #define IMX290_X_OUT_SIZE CCI_REG16_LE(0x3472) 103 #define IMX290_INCKSEL7 CCI_REG8(0x3480) 104 105 #define IMX290_PGCTRL_REGEN BIT(0) 106 #define IMX290_PGCTRL_THRU BIT(1) 107 #define IMX290_PGCTRL_MODE(n) ((n) << 4) 108 109 /* Number of lines by which exposure must be less than VMAX */ 110 #define IMX290_EXPOSURE_OFFSET 2 111 112 #define IMX290_PIXEL_RATE 148500000 113 114 /* 115 * The IMX290 pixel array is organized as follows: 116 * 117 * +------------------------------------+ 118 * | Optical Black | } Vertical effective optical black (10) 119 * +---+------------------------------------+---+ 120 * | | | | } Effective top margin (8) 121 * | | +----------------------------+ | | \ 122 * | | | | | | | 123 * | | | | | | | 124 * | | | | | | | 125 * | | | Recording Pixel Area | | | | Recommended height (1080) 126 * | | | | | | | 127 * | | | | | | | 128 * | | | | | | | 129 * | | +----------------------------+ | | / 130 * | | | | } Effective bottom margin (9) 131 * +---+------------------------------------+---+ 132 * <-> <-> <--------------------------> <-> <-> 133 * \---- Ignored right margin (4) 134 * \-------- Effective right margin (9) 135 * \------------------------- Recommended width (1920) 136 * \----------------------------------------- Effective left margin (8) 137 * \--------------------------------------------- Ignored left margin (4) 138 * 139 * The optical black lines are output over CSI-2 with a separate data type. 140 * 141 * The pixel array is meant to have 1920x1080 usable pixels after image 142 * processing in an ISP. It has 8 (9) extra active pixels usable for color 143 * processing in the ISP on the top and left (bottom and right) sides of the 144 * image. In addition, 4 additional pixels are present on the left and right 145 * sides of the image, documented as "ignored area". 146 * 147 * As far as is understood, all pixels of the pixel array (ignored area, color 148 * processing margins and recording area) can be output by the sensor. 149 */ 150 151 #define IMX290_PIXEL_ARRAY_WIDTH 1945 152 #define IMX290_PIXEL_ARRAY_HEIGHT 1097 153 #define IMX920_PIXEL_ARRAY_MARGIN_LEFT 12 154 #define IMX920_PIXEL_ARRAY_MARGIN_RIGHT 13 155 #define IMX920_PIXEL_ARRAY_MARGIN_TOP 8 156 #define IMX920_PIXEL_ARRAY_MARGIN_BOTTOM 9 157 #define IMX290_PIXEL_ARRAY_RECORDING_WIDTH 1920 158 #define IMX290_PIXEL_ARRAY_RECORDING_HEIGHT 1080 159 160 /* Equivalent value for 16bpp */ 161 #define IMX290_BLACK_LEVEL_DEFAULT 3840 162 163 #define IMX290_NUM_SUPPLIES 3 164 165 enum imx290_colour_variant { 166 IMX290_VARIANT_COLOUR, 167 IMX290_VARIANT_MONO, 168 IMX290_VARIANT_MAX 169 }; 170 171 enum imx290_model { 172 IMX290_MODEL_IMX290LQR, 173 IMX290_MODEL_IMX290LLR, 174 IMX290_MODEL_IMX327LQR, 175 }; 176 177 struct imx290_model_info { 178 enum imx290_colour_variant colour_variant; 179 const struct cci_reg_sequence *init_regs; 180 size_t init_regs_num; 181 const char *name; 182 }; 183 184 enum imx290_clk_freq { 185 IMX290_CLK_37_125, 186 IMX290_CLK_74_25, 187 IMX290_NUM_CLK 188 }; 189 190 /* 191 * Clock configuration for registers INCKSEL1 to INCKSEL6. 192 */ 193 struct imx290_clk_cfg { 194 u8 incksel1; 195 u8 incksel2; 196 u8 incksel3; 197 u8 incksel4; 198 u8 incksel5; 199 u8 incksel6; 200 }; 201 202 struct imx290_mode { 203 u32 width; 204 u32 height; 205 u32 hmax_min; 206 u32 vmax_min; 207 u8 link_freq_index; 208 u8 ctrl_07; 209 210 const struct cci_reg_sequence *data; 211 u32 data_size; 212 213 const struct imx290_clk_cfg *clk_cfg; 214 }; 215 216 struct imx290_csi_cfg { 217 u16 repetition; 218 u16 tclkpost; 219 u16 thszero; 220 u16 thsprepare; 221 u16 tclktrail; 222 u16 thstrail; 223 u16 tclkzero; 224 u16 tclkprepare; 225 u16 tlpx; 226 }; 227 228 struct imx290 { 229 struct device *dev; 230 struct clk *xclk; 231 struct regmap *regmap; 232 enum imx290_clk_freq xclk_idx; 233 u8 nlanes; 234 const struct imx290_model_info *model; 235 236 struct v4l2_subdev sd; 237 struct media_pad pad; 238 239 const struct imx290_mode *current_mode; 240 241 struct regulator_bulk_data supplies[IMX290_NUM_SUPPLIES]; 242 struct gpio_desc *rst_gpio; 243 244 struct v4l2_ctrl_handler ctrls; 245 struct v4l2_ctrl *link_freq; 246 struct v4l2_ctrl *hblank; 247 struct v4l2_ctrl *vblank; 248 struct v4l2_ctrl *exposure; 249 struct { 250 struct v4l2_ctrl *hflip; 251 struct v4l2_ctrl *vflip; 252 }; 253 }; 254 255 static inline struct imx290 *to_imx290(struct v4l2_subdev *_sd) 256 { 257 return container_of(_sd, struct imx290, sd); 258 } 259 260 /* ----------------------------------------------------------------------------- 261 * Modes and formats 262 */ 263 264 static const struct cci_reg_sequence imx290_global_init_settings[] = { 265 { IMX290_WINWV_OB, 12 }, 266 { IMX290_WINPH, 0 }, 267 { IMX290_WINPV, 0 }, 268 { IMX290_WINWH, 1948 }, 269 { IMX290_WINWV, 1097 }, 270 { IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC | 271 IMX290_XSOUTSEL_XHSOUTSEL_HSYNC }, 272 { CCI_REG8(0x3011), 0x02 }, 273 { CCI_REG8(0x3012), 0x64 }, 274 { CCI_REG8(0x3013), 0x00 }, 275 }; 276 277 static const struct cci_reg_sequence imx290_global_init_settings_290[] = { 278 { CCI_REG8(0x300f), 0x00 }, 279 { CCI_REG8(0x3010), 0x21 }, 280 { CCI_REG8(0x3016), 0x09 }, 281 { CCI_REG8(0x3070), 0x02 }, 282 { CCI_REG8(0x3071), 0x11 }, 283 { CCI_REG8(0x309b), 0x10 }, 284 { CCI_REG8(0x309c), 0x22 }, 285 { CCI_REG8(0x30a2), 0x02 }, 286 { CCI_REG8(0x30a6), 0x20 }, 287 { CCI_REG8(0x30a8), 0x20 }, 288 { CCI_REG8(0x30aa), 0x20 }, 289 { CCI_REG8(0x30ac), 0x20 }, 290 { CCI_REG8(0x30b0), 0x43 }, 291 { CCI_REG8(0x3119), 0x9e }, 292 { CCI_REG8(0x311c), 0x1e }, 293 { CCI_REG8(0x311e), 0x08 }, 294 { CCI_REG8(0x3128), 0x05 }, 295 { CCI_REG8(0x313d), 0x83 }, 296 { CCI_REG8(0x3150), 0x03 }, 297 { CCI_REG8(0x317e), 0x00 }, 298 { CCI_REG8(0x32b8), 0x50 }, 299 { CCI_REG8(0x32b9), 0x10 }, 300 { CCI_REG8(0x32ba), 0x00 }, 301 { CCI_REG8(0x32bb), 0x04 }, 302 { CCI_REG8(0x32c8), 0x50 }, 303 { CCI_REG8(0x32c9), 0x10 }, 304 { CCI_REG8(0x32ca), 0x00 }, 305 { CCI_REG8(0x32cb), 0x04 }, 306 { CCI_REG8(0x332c), 0xd3 }, 307 { CCI_REG8(0x332d), 0x10 }, 308 { CCI_REG8(0x332e), 0x0d }, 309 { CCI_REG8(0x3358), 0x06 }, 310 { CCI_REG8(0x3359), 0xe1 }, 311 { CCI_REG8(0x335a), 0x11 }, 312 { CCI_REG8(0x3360), 0x1e }, 313 { CCI_REG8(0x3361), 0x61 }, 314 { CCI_REG8(0x3362), 0x10 }, 315 { CCI_REG8(0x33b0), 0x50 }, 316 { CCI_REG8(0x33b2), 0x1a }, 317 { CCI_REG8(0x33b3), 0x04 }, 318 }; 319 320 #define IMX290_NUM_CLK_REGS 2 321 static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = { 322 [IMX290_CLK_37_125] = { 323 { IMX290_EXTCK_FREQ, (37125 * 256) / 1000 }, 324 { IMX290_INCKSEL7, 0x49 }, 325 }, 326 [IMX290_CLK_74_25] = { 327 { IMX290_EXTCK_FREQ, (74250 * 256) / 1000 }, 328 { IMX290_INCKSEL7, 0x92 }, 329 }, 330 }; 331 332 static const struct cci_reg_sequence imx290_global_init_settings_327[] = { 333 { CCI_REG8(0x309e), 0x4A }, 334 { CCI_REG8(0x309f), 0x4A }, 335 { CCI_REG8(0x313b), 0x61 }, 336 }; 337 338 static const struct cci_reg_sequence imx290_1080p_settings[] = { 339 /* mode settings */ 340 { IMX290_WINWV_OB, 12 }, 341 { IMX290_OPB_SIZE_V, 10 }, 342 { IMX290_X_OUT_SIZE, 1920 }, 343 { IMX290_Y_OUT_SIZE, 1080 }, 344 }; 345 346 static const struct cci_reg_sequence imx290_720p_settings[] = { 347 /* mode settings */ 348 { IMX290_WINWV_OB, 6 }, 349 { IMX290_OPB_SIZE_V, 4 }, 350 { IMX290_X_OUT_SIZE, 1280 }, 351 { IMX290_Y_OUT_SIZE, 720 }, 352 }; 353 354 static const struct cci_reg_sequence imx290_10bit_settings[] = { 355 { IMX290_ADBIT, IMX290_ADBIT_10BIT }, 356 { IMX290_OUT_CTRL, IMX290_ODBIT_10BIT }, 357 { IMX290_ADBIT1, IMX290_ADBIT1_10BIT }, 358 { IMX290_ADBIT2, IMX290_ADBIT2_10BIT }, 359 { IMX290_ADBIT3, IMX290_ADBIT3_10BIT }, 360 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 }, 361 }; 362 363 static const struct cci_reg_sequence imx290_12bit_settings[] = { 364 { IMX290_ADBIT, IMX290_ADBIT_12BIT }, 365 { IMX290_OUT_CTRL, IMX290_ODBIT_12BIT }, 366 { IMX290_ADBIT1, IMX290_ADBIT1_12BIT }, 367 { IMX290_ADBIT2, IMX290_ADBIT2_12BIT }, 368 { IMX290_ADBIT3, IMX290_ADBIT3_12BIT }, 369 { IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 }, 370 }; 371 372 static const struct imx290_csi_cfg imx290_csi_222_75mhz = { 373 /* 222.75MHz or 445.5Mbit/s per lane */ 374 .repetition = 0x10, 375 .tclkpost = 87, 376 .thszero = 55, 377 .thsprepare = 31, 378 .tclktrail = 31, 379 .thstrail = 31, 380 .tclkzero = 119, 381 .tclkprepare = 31, 382 .tlpx = 23, 383 }; 384 385 static const struct imx290_csi_cfg imx290_csi_445_5mhz = { 386 /* 445.5MHz or 891Mbit/s per lane */ 387 .repetition = 0x00, 388 .tclkpost = 119, 389 .thszero = 103, 390 .thsprepare = 71, 391 .tclktrail = 55, 392 .thstrail = 63, 393 .tclkzero = 255, 394 .tclkprepare = 63, 395 .tlpx = 55, 396 }; 397 398 static const struct imx290_csi_cfg imx290_csi_148_5mhz = { 399 /* 148.5MHz or 297Mbit/s per lane */ 400 .repetition = 0x10, 401 .tclkpost = 79, 402 .thszero = 47, 403 .thsprepare = 23, 404 .tclktrail = 23, 405 .thstrail = 23, 406 .tclkzero = 87, 407 .tclkprepare = 23, 408 .tlpx = 23, 409 }; 410 411 static const struct imx290_csi_cfg imx290_csi_297mhz = { 412 /* 297MHz or 594Mbit/s per lane */ 413 .repetition = 0x00, 414 .tclkpost = 103, 415 .thszero = 87, 416 .thsprepare = 47, 417 .tclktrail = 39, 418 .thstrail = 47, 419 .tclkzero = 191, 420 .tclkprepare = 47, 421 .tlpx = 39, 422 }; 423 424 /* supported link frequencies */ 425 #define FREQ_INDEX_1080P 0 426 #define FREQ_INDEX_720P 1 427 static const s64 imx290_link_freq_2lanes[] = { 428 [FREQ_INDEX_1080P] = 445500000, 429 [FREQ_INDEX_720P] = 297000000, 430 }; 431 432 static const s64 imx290_link_freq_4lanes[] = { 433 [FREQ_INDEX_1080P] = 222750000, 434 [FREQ_INDEX_720P] = 148500000, 435 }; 436 437 /* 438 * In this function and in the similar ones below We rely on imx290_probe() 439 * to ensure that nlanes is either 2 or 4. 440 */ 441 static inline const s64 *imx290_link_freqs_ptr(const struct imx290 *imx290) 442 { 443 if (imx290->nlanes == 2) 444 return imx290_link_freq_2lanes; 445 else 446 return imx290_link_freq_4lanes; 447 } 448 449 static inline int imx290_link_freqs_num(const struct imx290 *imx290) 450 { 451 if (imx290->nlanes == 2) 452 return ARRAY_SIZE(imx290_link_freq_2lanes); 453 else 454 return ARRAY_SIZE(imx290_link_freq_4lanes); 455 } 456 457 static const struct imx290_clk_cfg imx290_1080p_clock_config[] = { 458 [IMX290_CLK_37_125] = { 459 /* 37.125MHz clock config */ 460 .incksel1 = 0x18, 461 .incksel2 = 0x03, 462 .incksel3 = 0x20, 463 .incksel4 = 0x01, 464 .incksel5 = 0x1a, 465 .incksel6 = 0x1a, 466 }, 467 [IMX290_CLK_74_25] = { 468 /* 74.25MHz clock config */ 469 .incksel1 = 0x0c, 470 .incksel2 = 0x03, 471 .incksel3 = 0x10, 472 .incksel4 = 0x01, 473 .incksel5 = 0x1b, 474 .incksel6 = 0x1b, 475 }, 476 }; 477 478 static const struct imx290_clk_cfg imx290_720p_clock_config[] = { 479 [IMX290_CLK_37_125] = { 480 /* 37.125MHz clock config */ 481 .incksel1 = 0x20, 482 .incksel2 = 0x00, 483 .incksel3 = 0x20, 484 .incksel4 = 0x01, 485 .incksel5 = 0x1a, 486 .incksel6 = 0x1a, 487 }, 488 [IMX290_CLK_74_25] = { 489 /* 74.25MHz clock config */ 490 .incksel1 = 0x10, 491 .incksel2 = 0x00, 492 .incksel3 = 0x10, 493 .incksel4 = 0x01, 494 .incksel5 = 0x1b, 495 .incksel6 = 0x1b, 496 }, 497 }; 498 499 /* Mode configs */ 500 static const struct imx290_mode imx290_modes_2lanes[] = { 501 { 502 .width = 1920, 503 .height = 1080, 504 .hmax_min = 2200, 505 .vmax_min = 1125, 506 .link_freq_index = FREQ_INDEX_1080P, 507 .ctrl_07 = IMX290_WINMODE_1080P, 508 .data = imx290_1080p_settings, 509 .data_size = ARRAY_SIZE(imx290_1080p_settings), 510 .clk_cfg = imx290_1080p_clock_config, 511 }, 512 { 513 .width = 1280, 514 .height = 720, 515 .hmax_min = 3300, 516 .vmax_min = 750, 517 .link_freq_index = FREQ_INDEX_720P, 518 .ctrl_07 = IMX290_WINMODE_720P, 519 .data = imx290_720p_settings, 520 .data_size = ARRAY_SIZE(imx290_720p_settings), 521 .clk_cfg = imx290_720p_clock_config, 522 }, 523 }; 524 525 static const struct imx290_mode imx290_modes_4lanes[] = { 526 { 527 .width = 1920, 528 .height = 1080, 529 .hmax_min = 2200, 530 .vmax_min = 1125, 531 .link_freq_index = FREQ_INDEX_1080P, 532 .ctrl_07 = IMX290_WINMODE_1080P, 533 .data = imx290_1080p_settings, 534 .data_size = ARRAY_SIZE(imx290_1080p_settings), 535 .clk_cfg = imx290_1080p_clock_config, 536 }, 537 { 538 .width = 1280, 539 .height = 720, 540 .hmax_min = 3300, 541 .vmax_min = 750, 542 .link_freq_index = FREQ_INDEX_720P, 543 .ctrl_07 = IMX290_WINMODE_720P, 544 .data = imx290_720p_settings, 545 .data_size = ARRAY_SIZE(imx290_720p_settings), 546 .clk_cfg = imx290_720p_clock_config, 547 }, 548 }; 549 550 static inline const struct imx290_mode *imx290_modes_ptr(const struct imx290 *imx290) 551 { 552 if (imx290->nlanes == 2) 553 return imx290_modes_2lanes; 554 else 555 return imx290_modes_4lanes; 556 } 557 558 static inline int imx290_modes_num(const struct imx290 *imx290) 559 { 560 if (imx290->nlanes == 2) 561 return ARRAY_SIZE(imx290_modes_2lanes); 562 else 563 return ARRAY_SIZE(imx290_modes_4lanes); 564 } 565 566 struct imx290_format_info { 567 u32 code[IMX290_VARIANT_MAX]; 568 u8 bpp; 569 const struct cci_reg_sequence *regs; 570 unsigned int num_regs; 571 }; 572 573 static const struct imx290_format_info imx290_formats[] = { 574 { 575 .code = { 576 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB10_1X10, 577 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y10_1X10 578 }, 579 .bpp = 10, 580 .regs = imx290_10bit_settings, 581 .num_regs = ARRAY_SIZE(imx290_10bit_settings), 582 }, { 583 .code = { 584 [IMX290_VARIANT_COLOUR] = MEDIA_BUS_FMT_SRGGB12_1X12, 585 [IMX290_VARIANT_MONO] = MEDIA_BUS_FMT_Y12_1X12 586 }, 587 .bpp = 12, 588 .regs = imx290_12bit_settings, 589 .num_regs = ARRAY_SIZE(imx290_12bit_settings), 590 } 591 }; 592 593 static const struct imx290_format_info * 594 imx290_format_info(const struct imx290 *imx290, u32 code) 595 { 596 unsigned int i; 597 598 for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) { 599 const struct imx290_format_info *info = &imx290_formats[i]; 600 601 if (info->code[imx290->model->colour_variant] == code) 602 return info; 603 } 604 605 return NULL; 606 } 607 608 static int imx290_set_register_array(struct imx290 *imx290, 609 const struct cci_reg_sequence *settings, 610 unsigned int num_settings) 611 { 612 int ret; 613 614 ret = cci_multi_reg_write(imx290->regmap, settings, num_settings, NULL); 615 if (ret < 0) 616 return ret; 617 618 /* Provide 10ms settle time */ 619 usleep_range(10000, 11000); 620 621 return 0; 622 } 623 624 static int imx290_set_clock(struct imx290 *imx290) 625 { 626 const struct imx290_mode *mode = imx290->current_mode; 627 enum imx290_clk_freq clk_idx = imx290->xclk_idx; 628 const struct imx290_clk_cfg *clk_cfg = &mode->clk_cfg[clk_idx]; 629 int ret; 630 631 ret = imx290_set_register_array(imx290, xclk_regs[clk_idx], 632 IMX290_NUM_CLK_REGS); 633 634 cci_write(imx290->regmap, IMX290_INCKSEL1, clk_cfg->incksel1, &ret); 635 cci_write(imx290->regmap, IMX290_INCKSEL2, clk_cfg->incksel2, &ret); 636 cci_write(imx290->regmap, IMX290_INCKSEL3, clk_cfg->incksel3, &ret); 637 cci_write(imx290->regmap, IMX290_INCKSEL4, clk_cfg->incksel4, &ret); 638 cci_write(imx290->regmap, IMX290_INCKSEL5, clk_cfg->incksel5, &ret); 639 cci_write(imx290->regmap, IMX290_INCKSEL6, clk_cfg->incksel6, &ret); 640 641 return ret; 642 } 643 644 static int imx290_set_data_lanes(struct imx290 *imx290) 645 { 646 int ret = 0; 647 648 cci_write(imx290->regmap, IMX290_PHY_LANE_NUM, imx290->nlanes - 1, 649 &ret); 650 cci_write(imx290->regmap, IMX290_CSI_LANE_MODE, imx290->nlanes - 1, 651 &ret); 652 cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret); 653 654 return ret; 655 } 656 657 static int imx290_set_black_level(struct imx290 *imx290, 658 const struct v4l2_mbus_framefmt *format, 659 unsigned int black_level, int *err) 660 { 661 unsigned int bpp = imx290_format_info(imx290, format->code)->bpp; 662 663 return cci_write(imx290->regmap, IMX290_BLKLEVEL, 664 black_level >> (16 - bpp), err); 665 } 666 667 static int imx290_set_csi_config(struct imx290 *imx290) 668 { 669 const s64 *link_freqs = imx290_link_freqs_ptr(imx290); 670 const struct imx290_csi_cfg *csi_cfg; 671 int ret = 0; 672 673 switch (link_freqs[imx290->current_mode->link_freq_index]) { 674 case 445500000: 675 csi_cfg = &imx290_csi_445_5mhz; 676 break; 677 case 297000000: 678 csi_cfg = &imx290_csi_297mhz; 679 break; 680 case 222750000: 681 csi_cfg = &imx290_csi_222_75mhz; 682 break; 683 case 148500000: 684 csi_cfg = &imx290_csi_148_5mhz; 685 break; 686 default: 687 return -EINVAL; 688 } 689 690 cci_write(imx290->regmap, IMX290_REPETITION, csi_cfg->repetition, &ret); 691 cci_write(imx290->regmap, IMX290_TCLKPOST, csi_cfg->tclkpost, &ret); 692 cci_write(imx290->regmap, IMX290_THSZERO, csi_cfg->thszero, &ret); 693 cci_write(imx290->regmap, IMX290_THSPREPARE, csi_cfg->thsprepare, &ret); 694 cci_write(imx290->regmap, IMX290_TCLKTRAIL, csi_cfg->tclktrail, &ret); 695 cci_write(imx290->regmap, IMX290_THSTRAIL, csi_cfg->thstrail, &ret); 696 cci_write(imx290->regmap, IMX290_TCLKZERO, csi_cfg->tclkzero, &ret); 697 cci_write(imx290->regmap, IMX290_TCLKPREPARE, csi_cfg->tclkprepare, 698 &ret); 699 cci_write(imx290->regmap, IMX290_TLPX, csi_cfg->tlpx, &ret); 700 701 return ret; 702 } 703 704 static int imx290_setup_format(struct imx290 *imx290, 705 const struct v4l2_mbus_framefmt *format) 706 { 707 const struct imx290_format_info *info; 708 int ret; 709 710 info = imx290_format_info(imx290, format->code); 711 712 ret = imx290_set_register_array(imx290, info->regs, info->num_regs); 713 if (ret < 0) { 714 dev_err(imx290->dev, "Could not set format registers\n"); 715 return ret; 716 } 717 718 return imx290_set_black_level(imx290, format, 719 IMX290_BLACK_LEVEL_DEFAULT, &ret); 720 } 721 722 /* ---------------------------------------------------------------------------- 723 * Controls 724 */ 725 static void imx290_exposure_update(struct imx290 *imx290, 726 const struct imx290_mode *mode) 727 { 728 unsigned int exposure_max; 729 730 exposure_max = imx290->vblank->val + mode->height - 731 IMX290_EXPOSURE_OFFSET; 732 __v4l2_ctrl_modify_range(imx290->exposure, 1, exposure_max, 1, 733 exposure_max); 734 } 735 736 static int imx290_set_ctrl(struct v4l2_ctrl *ctrl) 737 { 738 struct imx290 *imx290 = container_of(ctrl->handler, 739 struct imx290, ctrls); 740 const struct v4l2_mbus_framefmt *format; 741 struct v4l2_subdev_state *state; 742 int ret = 0, vmax; 743 744 /* 745 * Return immediately for controls that don't need to be applied to the 746 * device. 747 */ 748 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) 749 return 0; 750 751 if (ctrl->id == V4L2_CID_VBLANK) { 752 /* Changing vblank changes the allowed range for exposure. */ 753 imx290_exposure_update(imx290, imx290->current_mode); 754 } 755 756 /* V4L2 controls values will be applied only when power is already up */ 757 if (!pm_runtime_get_if_in_use(imx290->dev)) 758 return 0; 759 760 state = v4l2_subdev_get_locked_active_state(&imx290->sd); 761 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 762 763 switch (ctrl->id) { 764 case V4L2_CID_ANALOGUE_GAIN: 765 ret = cci_write(imx290->regmap, IMX290_GAIN, ctrl->val, NULL); 766 break; 767 768 case V4L2_CID_VBLANK: 769 ret = cci_write(imx290->regmap, IMX290_VMAX, 770 ctrl->val + imx290->current_mode->height, NULL); 771 /* 772 * Due to the way that exposure is programmed in this sensor in 773 * relation to VMAX, we have to reprogramme it whenever VMAX is 774 * changed. 775 * Update ctrl so that the V4L2_CID_EXPOSURE case can refer to 776 * it. 777 */ 778 ctrl = imx290->exposure; 779 fallthrough; 780 case V4L2_CID_EXPOSURE: 781 vmax = imx290->vblank->val + imx290->current_mode->height; 782 ret = cci_write(imx290->regmap, IMX290_SHS1, 783 vmax - ctrl->val - 1, NULL); 784 break; 785 786 case V4L2_CID_TEST_PATTERN: 787 if (ctrl->val) { 788 imx290_set_black_level(imx290, format, 0, &ret); 789 usleep_range(10000, 11000); 790 cci_write(imx290->regmap, IMX290_PGCTRL, 791 (u8)(IMX290_PGCTRL_REGEN | 792 IMX290_PGCTRL_THRU | 793 IMX290_PGCTRL_MODE(ctrl->val)), &ret); 794 } else { 795 cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret); 796 usleep_range(10000, 11000); 797 imx290_set_black_level(imx290, format, 798 IMX290_BLACK_LEVEL_DEFAULT, &ret); 799 } 800 break; 801 802 case V4L2_CID_HBLANK: 803 ret = cci_write(imx290->regmap, IMX290_HMAX, 804 ctrl->val + imx290->current_mode->width, NULL); 805 break; 806 807 case V4L2_CID_HFLIP: 808 case V4L2_CID_VFLIP: 809 { 810 u32 reg; 811 812 reg = imx290->current_mode->ctrl_07; 813 if (imx290->hflip->val) 814 reg |= IMX290_HREVERSE; 815 if (imx290->vflip->val) 816 reg |= IMX290_VREVERSE; 817 ret = cci_write(imx290->regmap, IMX290_CTRL_07, reg, NULL); 818 break; 819 } 820 821 default: 822 ret = -EINVAL; 823 break; 824 } 825 826 pm_runtime_mark_last_busy(imx290->dev); 827 pm_runtime_put_autosuspend(imx290->dev); 828 829 return ret; 830 } 831 832 static const struct v4l2_ctrl_ops imx290_ctrl_ops = { 833 .s_ctrl = imx290_set_ctrl, 834 }; 835 836 static const char * const imx290_test_pattern_menu[] = { 837 "Disabled", 838 "Sequence Pattern 1", 839 "Horizontal Color-bar Chart", 840 "Vertical Color-bar Chart", 841 "Sequence Pattern 2", 842 "Gradation Pattern 1", 843 "Gradation Pattern 2", 844 "000/555h Toggle Pattern", 845 }; 846 847 static void imx290_ctrl_update(struct imx290 *imx290, 848 const struct imx290_mode *mode) 849 { 850 unsigned int hblank_min = mode->hmax_min - mode->width; 851 unsigned int hblank_max = IMX290_HMAX_MAX - mode->width; 852 unsigned int vblank_min = mode->vmax_min - mode->height; 853 unsigned int vblank_max = IMX290_VMAX_MAX - mode->height; 854 855 __v4l2_ctrl_s_ctrl(imx290->link_freq, mode->link_freq_index); 856 857 __v4l2_ctrl_modify_range(imx290->hblank, hblank_min, hblank_max, 1, 858 hblank_min); 859 __v4l2_ctrl_modify_range(imx290->vblank, vblank_min, vblank_max, 1, 860 vblank_min); 861 } 862 863 static int imx290_ctrl_init(struct imx290 *imx290) 864 { 865 struct v4l2_fwnode_device_properties props; 866 int ret; 867 868 ret = v4l2_fwnode_device_parse(imx290->dev, &props); 869 if (ret < 0) 870 return ret; 871 872 v4l2_ctrl_handler_init(&imx290->ctrls, 11); 873 874 /* 875 * The sensor has an analog gain and a digital gain, both controlled 876 * through a single gain value, expressed in 0.3dB increments. Values 877 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values 878 * up to 72.0dB (240) add further digital gain. Limit the range to 879 * analog gain only, support for digital gain can be added separately 880 * if needed. 881 * 882 * The IMX327 and IMX462 are largely compatible with the IMX290, but 883 * have an analog gain range of 0.0dB to 29.4dB and 42dB of digital 884 * gain. When support for those sensors gets added to the driver, the 885 * gain control should be adjusted accordingly. 886 */ 887 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 888 V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0); 889 890 /* 891 * Correct range will be determined through imx290_ctrl_update setting 892 * V4L2_CID_VBLANK. 893 */ 894 imx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 895 V4L2_CID_EXPOSURE, 1, 65535, 1, 896 65535); 897 898 /* 899 * Set the link frequency, pixel rate, horizontal blanking and vertical 900 * blanking to hardcoded values, they will be updated by 901 * imx290_ctrl_update(). 902 */ 903 imx290->link_freq = 904 v4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops, 905 V4L2_CID_LINK_FREQ, 906 imx290_link_freqs_num(imx290) - 1, 0, 907 imx290_link_freqs_ptr(imx290)); 908 if (imx290->link_freq) 909 imx290->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 910 911 v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, V4L2_CID_PIXEL_RATE, 912 IMX290_PIXEL_RATE, IMX290_PIXEL_RATE, 1, 913 IMX290_PIXEL_RATE); 914 915 v4l2_ctrl_new_std_menu_items(&imx290->ctrls, &imx290_ctrl_ops, 916 V4L2_CID_TEST_PATTERN, 917 ARRAY_SIZE(imx290_test_pattern_menu) - 1, 918 0, 0, imx290_test_pattern_menu); 919 920 /* 921 * Actual range will be set from imx290_ctrl_update later in the probe. 922 */ 923 imx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 924 V4L2_CID_HBLANK, 1, 1, 1, 1); 925 926 imx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 927 V4L2_CID_VBLANK, 1, 1, 1, 1); 928 929 imx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 930 V4L2_CID_HFLIP, 0, 1, 1, 0); 931 imx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops, 932 V4L2_CID_VFLIP, 0, 1, 1, 0); 933 v4l2_ctrl_cluster(2, &imx290->hflip); 934 935 v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops, 936 &props); 937 938 imx290->sd.ctrl_handler = &imx290->ctrls; 939 940 if (imx290->ctrls.error) { 941 ret = imx290->ctrls.error; 942 v4l2_ctrl_handler_free(&imx290->ctrls); 943 return ret; 944 } 945 946 return 0; 947 } 948 949 /* ---------------------------------------------------------------------------- 950 * Subdev operations 951 */ 952 953 /* Start streaming */ 954 static int imx290_start_streaming(struct imx290 *imx290, 955 struct v4l2_subdev_state *state) 956 { 957 const struct v4l2_mbus_framefmt *format; 958 int ret; 959 960 /* Set init register settings */ 961 ret = imx290_set_register_array(imx290, imx290_global_init_settings, 962 ARRAY_SIZE(imx290_global_init_settings)); 963 if (ret < 0) { 964 dev_err(imx290->dev, "Could not set init registers\n"); 965 return ret; 966 } 967 968 /* Set mdel specific init register settings */ 969 ret = imx290_set_register_array(imx290, imx290->model->init_regs, 970 imx290->model->init_regs_num); 971 if (ret < 0) { 972 dev_err(imx290->dev, "Could not set model specific init registers\n"); 973 return ret; 974 } 975 976 /* Set clock parameters based on mode and xclk */ 977 ret = imx290_set_clock(imx290); 978 if (ret < 0) { 979 dev_err(imx290->dev, "Could not set clocks - %d\n", ret); 980 return ret; 981 } 982 983 /* Set data lane count */ 984 ret = imx290_set_data_lanes(imx290); 985 if (ret < 0) { 986 dev_err(imx290->dev, "Could not set data lanes - %d\n", ret); 987 return ret; 988 } 989 990 ret = imx290_set_csi_config(imx290); 991 if (ret < 0) { 992 dev_err(imx290->dev, "Could not set csi cfg - %d\n", ret); 993 return ret; 994 } 995 996 /* Apply the register values related to current frame format */ 997 format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0); 998 ret = imx290_setup_format(imx290, format); 999 if (ret < 0) { 1000 dev_err(imx290->dev, "Could not set frame format - %d\n", ret); 1001 return ret; 1002 } 1003 1004 /* Apply default values of current mode */ 1005 ret = imx290_set_register_array(imx290, imx290->current_mode->data, 1006 imx290->current_mode->data_size); 1007 if (ret < 0) { 1008 dev_err(imx290->dev, "Could not set current mode - %d\n", ret); 1009 return ret; 1010 } 1011 1012 /* Apply customized values from user */ 1013 ret = __v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler); 1014 if (ret) { 1015 dev_err(imx290->dev, "Could not sync v4l2 controls - %d\n", ret); 1016 return ret; 1017 } 1018 1019 cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret); 1020 1021 msleep(30); 1022 1023 /* Start streaming */ 1024 return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret); 1025 } 1026 1027 /* Stop streaming */ 1028 static int imx290_stop_streaming(struct imx290 *imx290) 1029 { 1030 int ret = 0; 1031 1032 cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret); 1033 1034 msleep(30); 1035 1036 return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret); 1037 } 1038 1039 static int imx290_set_stream(struct v4l2_subdev *sd, int enable) 1040 { 1041 struct imx290 *imx290 = to_imx290(sd); 1042 struct v4l2_subdev_state *state; 1043 int ret = 0; 1044 1045 state = v4l2_subdev_lock_and_get_active_state(sd); 1046 1047 if (enable) { 1048 ret = pm_runtime_resume_and_get(imx290->dev); 1049 if (ret < 0) 1050 goto unlock; 1051 1052 ret = imx290_start_streaming(imx290, state); 1053 if (ret) { 1054 dev_err(imx290->dev, "Start stream failed\n"); 1055 pm_runtime_put_sync(imx290->dev); 1056 goto unlock; 1057 } 1058 } else { 1059 imx290_stop_streaming(imx290); 1060 pm_runtime_mark_last_busy(imx290->dev); 1061 pm_runtime_put_autosuspend(imx290->dev); 1062 } 1063 1064 /* 1065 * vflip and hflip should not be changed during streaming as the sensor 1066 * will produce an invalid frame. 1067 */ 1068 __v4l2_ctrl_grab(imx290->vflip, enable); 1069 __v4l2_ctrl_grab(imx290->hflip, enable); 1070 1071 unlock: 1072 v4l2_subdev_unlock_state(state); 1073 return ret; 1074 } 1075 1076 static int imx290_enum_mbus_code(struct v4l2_subdev *sd, 1077 struct v4l2_subdev_state *sd_state, 1078 struct v4l2_subdev_mbus_code_enum *code) 1079 { 1080 const struct imx290 *imx290 = to_imx290(sd); 1081 1082 if (code->index >= ARRAY_SIZE(imx290_formats)) 1083 return -EINVAL; 1084 1085 code->code = imx290_formats[code->index].code[imx290->model->colour_variant]; 1086 1087 return 0; 1088 } 1089 1090 static int imx290_enum_frame_size(struct v4l2_subdev *sd, 1091 struct v4l2_subdev_state *sd_state, 1092 struct v4l2_subdev_frame_size_enum *fse) 1093 { 1094 const struct imx290 *imx290 = to_imx290(sd); 1095 const struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290); 1096 1097 if (!imx290_format_info(imx290, fse->code)) 1098 return -EINVAL; 1099 1100 if (fse->index >= imx290_modes_num(imx290)) 1101 return -EINVAL; 1102 1103 fse->min_width = imx290_modes[fse->index].width; 1104 fse->max_width = imx290_modes[fse->index].width; 1105 fse->min_height = imx290_modes[fse->index].height; 1106 fse->max_height = imx290_modes[fse->index].height; 1107 1108 return 0; 1109 } 1110 1111 static int imx290_set_fmt(struct v4l2_subdev *sd, 1112 struct v4l2_subdev_state *sd_state, 1113 struct v4l2_subdev_format *fmt) 1114 { 1115 struct imx290 *imx290 = to_imx290(sd); 1116 const struct imx290_mode *mode; 1117 struct v4l2_mbus_framefmt *format; 1118 1119 mode = v4l2_find_nearest_size(imx290_modes_ptr(imx290), 1120 imx290_modes_num(imx290), width, height, 1121 fmt->format.width, fmt->format.height); 1122 1123 fmt->format.width = mode->width; 1124 fmt->format.height = mode->height; 1125 1126 if (!imx290_format_info(imx290, fmt->format.code)) 1127 fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant]; 1128 1129 fmt->format.field = V4L2_FIELD_NONE; 1130 fmt->format.colorspace = V4L2_COLORSPACE_RAW; 1131 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601; 1132 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE; 1133 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; 1134 1135 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1136 1137 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 1138 imx290->current_mode = mode; 1139 1140 imx290_ctrl_update(imx290, mode); 1141 imx290_exposure_update(imx290, mode); 1142 } 1143 1144 *format = fmt->format; 1145 1146 return 0; 1147 } 1148 1149 static int imx290_get_selection(struct v4l2_subdev *sd, 1150 struct v4l2_subdev_state *sd_state, 1151 struct v4l2_subdev_selection *sel) 1152 { 1153 struct imx290 *imx290 = to_imx290(sd); 1154 struct v4l2_mbus_framefmt *format; 1155 1156 switch (sel->target) { 1157 case V4L2_SEL_TGT_CROP: { 1158 format = v4l2_subdev_get_pad_format(sd, sd_state, 0); 1159 1160 /* 1161 * The sensor moves the readout by 1 pixel based on flips to 1162 * keep the Bayer order the same. 1163 */ 1164 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP 1165 + (IMX290_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2 1166 + imx290->vflip->val; 1167 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT 1168 + (IMX290_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2 1169 + imx290->hflip->val; 1170 sel->r.width = format->width; 1171 sel->r.height = format->height; 1172 1173 return 0; 1174 } 1175 1176 case V4L2_SEL_TGT_NATIVE_SIZE: 1177 case V4L2_SEL_TGT_CROP_BOUNDS: 1178 sel->r.top = 0; 1179 sel->r.left = 0; 1180 sel->r.width = IMX290_PIXEL_ARRAY_WIDTH; 1181 sel->r.height = IMX290_PIXEL_ARRAY_HEIGHT; 1182 1183 return 0; 1184 1185 case V4L2_SEL_TGT_CROP_DEFAULT: 1186 sel->r.top = IMX920_PIXEL_ARRAY_MARGIN_TOP; 1187 sel->r.left = IMX920_PIXEL_ARRAY_MARGIN_LEFT; 1188 sel->r.width = IMX290_PIXEL_ARRAY_RECORDING_WIDTH; 1189 sel->r.height = IMX290_PIXEL_ARRAY_RECORDING_HEIGHT; 1190 1191 return 0; 1192 1193 default: 1194 return -EINVAL; 1195 } 1196 } 1197 1198 static int imx290_entity_init_cfg(struct v4l2_subdev *subdev, 1199 struct v4l2_subdev_state *sd_state) 1200 { 1201 struct v4l2_subdev_format fmt = { 1202 .which = V4L2_SUBDEV_FORMAT_TRY, 1203 .format = { 1204 .width = 1920, 1205 .height = 1080, 1206 }, 1207 }; 1208 1209 imx290_set_fmt(subdev, sd_state, &fmt); 1210 1211 return 0; 1212 } 1213 1214 static const struct v4l2_subdev_core_ops imx290_core_ops = { 1215 .subscribe_event = v4l2_ctrl_subdev_subscribe_event, 1216 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1217 }; 1218 1219 static const struct v4l2_subdev_video_ops imx290_video_ops = { 1220 .s_stream = imx290_set_stream, 1221 }; 1222 1223 static const struct v4l2_subdev_pad_ops imx290_pad_ops = { 1224 .init_cfg = imx290_entity_init_cfg, 1225 .enum_mbus_code = imx290_enum_mbus_code, 1226 .enum_frame_size = imx290_enum_frame_size, 1227 .get_fmt = v4l2_subdev_get_fmt, 1228 .set_fmt = imx290_set_fmt, 1229 .get_selection = imx290_get_selection, 1230 }; 1231 1232 static const struct v4l2_subdev_ops imx290_subdev_ops = { 1233 .core = &imx290_core_ops, 1234 .video = &imx290_video_ops, 1235 .pad = &imx290_pad_ops, 1236 }; 1237 1238 static const struct media_entity_operations imx290_subdev_entity_ops = { 1239 .link_validate = v4l2_subdev_link_validate, 1240 }; 1241 1242 static int imx290_subdev_init(struct imx290 *imx290) 1243 { 1244 struct i2c_client *client = to_i2c_client(imx290->dev); 1245 struct v4l2_subdev_state *state; 1246 int ret; 1247 1248 imx290->current_mode = &imx290_modes_ptr(imx290)[0]; 1249 1250 v4l2_i2c_subdev_init(&imx290->sd, client, &imx290_subdev_ops); 1251 imx290->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | 1252 V4L2_SUBDEV_FL_HAS_EVENTS; 1253 imx290->sd.dev = imx290->dev; 1254 imx290->sd.entity.ops = &imx290_subdev_entity_ops; 1255 imx290->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1256 1257 imx290->pad.flags = MEDIA_PAD_FL_SOURCE; 1258 ret = media_entity_pads_init(&imx290->sd.entity, 1, &imx290->pad); 1259 if (ret < 0) { 1260 dev_err(imx290->dev, "Could not register media entity\n"); 1261 return ret; 1262 } 1263 1264 ret = imx290_ctrl_init(imx290); 1265 if (ret < 0) { 1266 dev_err(imx290->dev, "Control initialization error %d\n", ret); 1267 goto err_media; 1268 } 1269 1270 imx290->sd.state_lock = imx290->ctrls.lock; 1271 1272 ret = v4l2_subdev_init_finalize(&imx290->sd); 1273 if (ret < 0) { 1274 dev_err(imx290->dev, "subdev initialization error %d\n", ret); 1275 goto err_ctrls; 1276 } 1277 1278 state = v4l2_subdev_lock_and_get_active_state(&imx290->sd); 1279 imx290_ctrl_update(imx290, imx290->current_mode); 1280 v4l2_subdev_unlock_state(state); 1281 1282 return 0; 1283 1284 err_ctrls: 1285 v4l2_ctrl_handler_free(&imx290->ctrls); 1286 err_media: 1287 media_entity_cleanup(&imx290->sd.entity); 1288 return ret; 1289 } 1290 1291 static void imx290_subdev_cleanup(struct imx290 *imx290) 1292 { 1293 v4l2_subdev_cleanup(&imx290->sd); 1294 media_entity_cleanup(&imx290->sd.entity); 1295 v4l2_ctrl_handler_free(&imx290->ctrls); 1296 } 1297 1298 /* ---------------------------------------------------------------------------- 1299 * Power management 1300 */ 1301 1302 static int imx290_power_on(struct imx290 *imx290) 1303 { 1304 int ret; 1305 1306 ret = clk_prepare_enable(imx290->xclk); 1307 if (ret) { 1308 dev_err(imx290->dev, "Failed to enable clock\n"); 1309 return ret; 1310 } 1311 1312 ret = regulator_bulk_enable(ARRAY_SIZE(imx290->supplies), 1313 imx290->supplies); 1314 if (ret) { 1315 dev_err(imx290->dev, "Failed to enable regulators\n"); 1316 clk_disable_unprepare(imx290->xclk); 1317 return ret; 1318 } 1319 1320 usleep_range(1, 2); 1321 gpiod_set_value_cansleep(imx290->rst_gpio, 0); 1322 usleep_range(30000, 31000); 1323 1324 return 0; 1325 } 1326 1327 static void imx290_power_off(struct imx290 *imx290) 1328 { 1329 clk_disable_unprepare(imx290->xclk); 1330 gpiod_set_value_cansleep(imx290->rst_gpio, 1); 1331 regulator_bulk_disable(ARRAY_SIZE(imx290->supplies), imx290->supplies); 1332 } 1333 1334 static int imx290_runtime_resume(struct device *dev) 1335 { 1336 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1337 struct imx290 *imx290 = to_imx290(sd); 1338 1339 return imx290_power_on(imx290); 1340 } 1341 1342 static int imx290_runtime_suspend(struct device *dev) 1343 { 1344 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1345 struct imx290 *imx290 = to_imx290(sd); 1346 1347 imx290_power_off(imx290); 1348 1349 return 0; 1350 } 1351 1352 static const struct dev_pm_ops imx290_pm_ops = { 1353 RUNTIME_PM_OPS(imx290_runtime_suspend, imx290_runtime_resume, NULL) 1354 }; 1355 1356 /* ---------------------------------------------------------------------------- 1357 * Probe & remove 1358 */ 1359 1360 static const char * const imx290_supply_name[IMX290_NUM_SUPPLIES] = { 1361 "vdda", 1362 "vddd", 1363 "vdddo", 1364 }; 1365 1366 static int imx290_get_regulators(struct device *dev, struct imx290 *imx290) 1367 { 1368 unsigned int i; 1369 1370 for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++) 1371 imx290->supplies[i].supply = imx290_supply_name[i]; 1372 1373 return devm_regulator_bulk_get(dev, ARRAY_SIZE(imx290->supplies), 1374 imx290->supplies); 1375 } 1376 1377 static int imx290_init_clk(struct imx290 *imx290) 1378 { 1379 u32 xclk_freq; 1380 int ret; 1381 1382 ret = device_property_read_u32(imx290->dev, "clock-frequency", 1383 &xclk_freq); 1384 if (ret) { 1385 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1386 return ret; 1387 } 1388 1389 /* external clock must be 37.125 MHz or 74.25MHz */ 1390 switch (xclk_freq) { 1391 case 37125000: 1392 imx290->xclk_idx = IMX290_CLK_37_125; 1393 break; 1394 case 74250000: 1395 imx290->xclk_idx = IMX290_CLK_74_25; 1396 break; 1397 default: 1398 dev_err(imx290->dev, "External clock frequency %u is not supported\n", 1399 xclk_freq); 1400 return -EINVAL; 1401 } 1402 1403 ret = clk_set_rate(imx290->xclk, xclk_freq); 1404 if (ret) { 1405 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1406 return ret; 1407 } 1408 1409 return 0; 1410 } 1411 1412 /* 1413 * Returns 0 if all link frequencies used by the driver for the given number 1414 * of MIPI data lanes are mentioned in the device tree, or the value of the 1415 * first missing frequency otherwise. 1416 */ 1417 static s64 imx290_check_link_freqs(const struct imx290 *imx290, 1418 const struct v4l2_fwnode_endpoint *ep) 1419 { 1420 int i, j; 1421 const s64 *freqs = imx290_link_freqs_ptr(imx290); 1422 int freqs_count = imx290_link_freqs_num(imx290); 1423 1424 for (i = 0; i < freqs_count; i++) { 1425 for (j = 0; j < ep->nr_of_link_frequencies; j++) 1426 if (freqs[i] == ep->link_frequencies[j]) 1427 break; 1428 if (j == ep->nr_of_link_frequencies) 1429 return freqs[i]; 1430 } 1431 return 0; 1432 } 1433 1434 static const struct imx290_model_info imx290_models[] = { 1435 [IMX290_MODEL_IMX290LQR] = { 1436 .colour_variant = IMX290_VARIANT_COLOUR, 1437 .init_regs = imx290_global_init_settings_290, 1438 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1439 .name = "imx290", 1440 }, 1441 [IMX290_MODEL_IMX290LLR] = { 1442 .colour_variant = IMX290_VARIANT_MONO, 1443 .init_regs = imx290_global_init_settings_290, 1444 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290), 1445 .name = "imx290", 1446 }, 1447 [IMX290_MODEL_IMX327LQR] = { 1448 .colour_variant = IMX290_VARIANT_COLOUR, 1449 .init_regs = imx290_global_init_settings_327, 1450 .init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327), 1451 .name = "imx327", 1452 }, 1453 }; 1454 1455 static int imx290_parse_dt(struct imx290 *imx290) 1456 { 1457 /* Only CSI2 is supported for now: */ 1458 struct v4l2_fwnode_endpoint ep = { 1459 .bus_type = V4L2_MBUS_CSI2_DPHY 1460 }; 1461 struct fwnode_handle *endpoint; 1462 int ret; 1463 s64 fq; 1464 1465 imx290->model = of_device_get_match_data(imx290->dev); 1466 1467 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(imx290->dev), NULL); 1468 if (!endpoint) { 1469 dev_err(imx290->dev, "Endpoint node not found\n"); 1470 return -EINVAL; 1471 } 1472 1473 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep); 1474 fwnode_handle_put(endpoint); 1475 if (ret == -ENXIO) { 1476 dev_err(imx290->dev, "Unsupported bus type, should be CSI2\n"); 1477 goto done; 1478 } else if (ret) { 1479 dev_err(imx290->dev, "Parsing endpoint node failed\n"); 1480 goto done; 1481 } 1482 1483 /* Get number of data lanes */ 1484 imx290->nlanes = ep.bus.mipi_csi2.num_data_lanes; 1485 if (imx290->nlanes != 2 && imx290->nlanes != 4) { 1486 dev_err(imx290->dev, "Invalid data lanes: %d\n", imx290->nlanes); 1487 ret = -EINVAL; 1488 goto done; 1489 } 1490 1491 dev_dbg(imx290->dev, "Using %u data lanes\n", imx290->nlanes); 1492 1493 if (!ep.nr_of_link_frequencies) { 1494 dev_err(imx290->dev, "link-frequency property not found in DT\n"); 1495 ret = -EINVAL; 1496 goto done; 1497 } 1498 1499 /* Check that link frequences for all the modes are in device tree */ 1500 fq = imx290_check_link_freqs(imx290, &ep); 1501 if (fq) { 1502 dev_err(imx290->dev, "Link frequency of %lld is not supported\n", 1503 fq); 1504 ret = -EINVAL; 1505 goto done; 1506 } 1507 1508 ret = 0; 1509 1510 done: 1511 v4l2_fwnode_endpoint_free(&ep); 1512 return ret; 1513 } 1514 1515 static int imx290_probe(struct i2c_client *client) 1516 { 1517 struct device *dev = &client->dev; 1518 struct imx290 *imx290; 1519 int ret; 1520 1521 imx290 = devm_kzalloc(dev, sizeof(*imx290), GFP_KERNEL); 1522 if (!imx290) 1523 return -ENOMEM; 1524 1525 imx290->dev = dev; 1526 imx290->regmap = devm_cci_regmap_init_i2c(client, 16); 1527 if (IS_ERR(imx290->regmap)) { 1528 dev_err(dev, "Unable to initialize I2C\n"); 1529 return -ENODEV; 1530 } 1531 1532 ret = imx290_parse_dt(imx290); 1533 if (ret) 1534 return ret; 1535 1536 /* Acquire resources. */ 1537 imx290->xclk = devm_clk_get(dev, "xclk"); 1538 if (IS_ERR(imx290->xclk)) 1539 return dev_err_probe(dev, PTR_ERR(imx290->xclk), 1540 "Could not get xclk\n"); 1541 1542 ret = imx290_get_regulators(dev, imx290); 1543 if (ret < 0) 1544 return dev_err_probe(dev, ret, "Cannot get regulators\n"); 1545 1546 imx290->rst_gpio = devm_gpiod_get_optional(dev, "reset", 1547 GPIOD_OUT_HIGH); 1548 if (IS_ERR(imx290->rst_gpio)) 1549 return dev_err_probe(dev, PTR_ERR(imx290->rst_gpio), 1550 "Cannot get reset gpio\n"); 1551 1552 /* Initialize external clock frequency. */ 1553 ret = imx290_init_clk(imx290); 1554 if (ret) 1555 return ret; 1556 1557 /* 1558 * Enable power management. The driver supports runtime PM, but needs to 1559 * work when runtime PM is disabled in the kernel. To that end, power 1560 * the sensor on manually here. 1561 */ 1562 ret = imx290_power_on(imx290); 1563 if (ret < 0) { 1564 dev_err(dev, "Could not power on the device\n"); 1565 return ret; 1566 } 1567 1568 /* 1569 * Enable runtime PM with autosuspend. As the device has been powered 1570 * manually, mark it as active, and increase the usage count without 1571 * resuming the device. 1572 */ 1573 pm_runtime_set_active(dev); 1574 pm_runtime_get_noresume(dev); 1575 pm_runtime_enable(dev); 1576 pm_runtime_set_autosuspend_delay(dev, 1000); 1577 pm_runtime_use_autosuspend(dev); 1578 1579 /* Initialize the V4L2 subdev. */ 1580 ret = imx290_subdev_init(imx290); 1581 if (ret) 1582 goto err_pm; 1583 1584 v4l2_i2c_subdev_set_name(&imx290->sd, client, 1585 imx290->model->name, NULL); 1586 1587 /* 1588 * Finally, register the V4L2 subdev. This must be done after 1589 * initializing everything as the subdev can be used immediately after 1590 * being registered. 1591 */ 1592 ret = v4l2_async_register_subdev(&imx290->sd); 1593 if (ret < 0) { 1594 dev_err(dev, "Could not register v4l2 device\n"); 1595 goto err_subdev; 1596 } 1597 1598 /* 1599 * Decrease the PM usage count. The device will get suspended after the 1600 * autosuspend delay, turning the power off. 1601 */ 1602 pm_runtime_mark_last_busy(dev); 1603 pm_runtime_put_autosuspend(dev); 1604 1605 return 0; 1606 1607 err_subdev: 1608 imx290_subdev_cleanup(imx290); 1609 err_pm: 1610 pm_runtime_disable(dev); 1611 pm_runtime_put_noidle(dev); 1612 imx290_power_off(imx290); 1613 return ret; 1614 } 1615 1616 static void imx290_remove(struct i2c_client *client) 1617 { 1618 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1619 struct imx290 *imx290 = to_imx290(sd); 1620 1621 v4l2_async_unregister_subdev(sd); 1622 imx290_subdev_cleanup(imx290); 1623 1624 /* 1625 * Disable runtime PM. In case runtime PM is disabled in the kernel, 1626 * make sure to turn power off manually. 1627 */ 1628 pm_runtime_disable(imx290->dev); 1629 if (!pm_runtime_status_suspended(imx290->dev)) 1630 imx290_power_off(imx290); 1631 pm_runtime_set_suspended(imx290->dev); 1632 } 1633 1634 static const struct of_device_id imx290_of_match[] = { 1635 { 1636 /* Deprecated - synonym for "sony,imx290lqr" */ 1637 .compatible = "sony,imx290", 1638 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1639 }, { 1640 .compatible = "sony,imx290lqr", 1641 .data = &imx290_models[IMX290_MODEL_IMX290LQR], 1642 }, { 1643 .compatible = "sony,imx290llr", 1644 .data = &imx290_models[IMX290_MODEL_IMX290LLR], 1645 }, { 1646 .compatible = "sony,imx327lqr", 1647 .data = &imx290_models[IMX290_MODEL_IMX327LQR], 1648 }, 1649 { /* sentinel */ }, 1650 }; 1651 MODULE_DEVICE_TABLE(of, imx290_of_match); 1652 1653 static struct i2c_driver imx290_i2c_driver = { 1654 .probe = imx290_probe, 1655 .remove = imx290_remove, 1656 .driver = { 1657 .name = "imx290", 1658 .pm = pm_ptr(&imx290_pm_ops), 1659 .of_match_table = imx290_of_match, 1660 }, 1661 }; 1662 1663 module_i2c_driver(imx290_i2c_driver); 1664 1665 MODULE_DESCRIPTION("Sony IMX290 CMOS Image Sensor Driver"); 1666 MODULE_AUTHOR("FRAMOS GmbH"); 1667 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 1668 MODULE_LICENSE("GPL v2"); 1669