1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/slab.h> 15 #include <linux/of.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/videodev2.h> 18 #include <media/v4l2-ioctl.h> 19 #include <media/v4l2-event.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ctrls.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 29 #define ADV7180_STD_NTSC_J 0x4 30 #define ADV7180_STD_NTSC_M 0x5 31 #define ADV7180_STD_PAL60 0x6 32 #define ADV7180_STD_NTSC_443 0x7 33 #define ADV7180_STD_PAL_BG 0x8 34 #define ADV7180_STD_PAL_N 0x9 35 #define ADV7180_STD_PAL_M 0xa 36 #define ADV7180_STD_PAL_M_PED 0xb 37 #define ADV7180_STD_PAL_COMB_N 0xc 38 #define ADV7180_STD_PAL_COMB_N_PED 0xd 39 #define ADV7180_STD_PAL_SECAM 0xe 40 #define ADV7180_STD_PAL_SECAM_PED 0xf 41 42 #define ADV7180_REG_INPUT_CONTROL 0x0000 43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 44 45 #define ADV7182_REG_INPUT_VIDSEL 0x0002 46 47 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 48 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 49 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 50 51 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 52 #define ADV7180_AUTODETECT_DEFAULT 0x7f 53 /* Contrast */ 54 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 55 #define ADV7180_CON_MIN 0 56 #define ADV7180_CON_DEF 128 57 #define ADV7180_CON_MAX 255 58 /* Brightness*/ 59 #define ADV7180_REG_BRI 0x000a /*Signed */ 60 #define ADV7180_BRI_MIN -128 61 #define ADV7180_BRI_DEF 0 62 #define ADV7180_BRI_MAX 127 63 /* Hue */ 64 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 65 #define ADV7180_HUE_MIN -127 66 #define ADV7180_HUE_DEF 0 67 #define ADV7180_HUE_MAX 128 68 69 #define ADV7180_REG_DEF_VALUE_Y 0x000c 70 #define ADV7180_DEF_VAL_EN 0x1 71 #define ADV7180_DEF_VAL_AUTO_EN 0x2 72 #define ADV7180_REG_CTRL 0x000e 73 #define ADV7180_CTRL_IRQ_SPACE 0x20 74 75 #define ADV7180_REG_PWR_MAN 0x0f 76 #define ADV7180_PWR_MAN_ON 0x04 77 #define ADV7180_PWR_MAN_OFF 0x24 78 #define ADV7180_PWR_MAN_RES 0x80 79 80 #define ADV7180_REG_STATUS1 0x0010 81 #define ADV7180_STATUS1_IN_LOCK 0x01 82 #define ADV7180_STATUS1_AUTOD_MASK 0x70 83 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 84 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 85 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 86 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 87 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 88 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 89 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 90 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 91 92 #define ADV7180_REG_IDENT 0x0011 93 #define ADV7180_ID_7180 0x18 94 95 #define ADV7180_REG_STATUS3 0x0013 96 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 97 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 98 #define ADV7180_REG_CTRL_2 0x001d 99 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 100 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12 101 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 102 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 103 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 104 #define ADV7180_REG_LOCK_CNT 0x0051 105 #define ADV7180_REG_CVBS_TRIM 0x0052 106 #define ADV7180_REG_CLAMP_ADJ 0x005a 107 #define ADV7180_REG_RES_CIR 0x005f 108 #define ADV7180_REG_DIFF_MODE 0x0060 109 110 #define ADV7180_REG_ICONF1 0x2040 111 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 112 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 113 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 114 /* Saturation */ 115 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 116 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 117 #define ADV7180_SAT_MIN 0 118 #define ADV7180_SAT_DEF 128 119 #define ADV7180_SAT_MAX 255 120 121 #define ADV7180_IRQ1_LOCK 0x01 122 #define ADV7180_IRQ1_UNLOCK 0x02 123 #define ADV7180_REG_ISR1 0x2042 124 #define ADV7180_REG_ICR1 0x2043 125 #define ADV7180_REG_IMR1 0x2044 126 #define ADV7180_REG_IMR2 0x2048 127 #define ADV7180_IRQ3_AD_CHANGE 0x08 128 #define ADV7180_REG_ISR3 0x204A 129 #define ADV7180_REG_ICR3 0x204B 130 #define ADV7180_REG_IMR3 0x204C 131 #define ADV7180_REG_IMR4 0x2050 132 133 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 134 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 135 136 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 137 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 138 139 #define ADV7180_REG_ACE_CTRL1 0x4080 140 #define ADV7180_REG_ACE_CTRL5 0x4084 141 #define ADV7180_REG_FLCONTROL 0x40e0 142 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 143 144 #define ADV7180_REG_RST_CLAMP 0x809c 145 #define ADV7180_REG_AGC_ADJ1 0x80b6 146 #define ADV7180_REG_AGC_ADJ2 0x80c0 147 148 #define ADV7180_CSI_REG_PWRDN 0x00 149 #define ADV7180_CSI_PWRDN 0x80 150 151 #define ADV7180_INPUT_CVBS_AIN1 0x00 152 #define ADV7180_INPUT_CVBS_AIN2 0x01 153 #define ADV7180_INPUT_CVBS_AIN3 0x02 154 #define ADV7180_INPUT_CVBS_AIN4 0x03 155 #define ADV7180_INPUT_CVBS_AIN5 0x04 156 #define ADV7180_INPUT_CVBS_AIN6 0x05 157 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 158 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 159 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 160 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 161 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 162 163 #define ADV7182_INPUT_CVBS_AIN1 0x00 164 #define ADV7182_INPUT_CVBS_AIN2 0x01 165 #define ADV7182_INPUT_CVBS_AIN3 0x02 166 #define ADV7182_INPUT_CVBS_AIN4 0x03 167 #define ADV7182_INPUT_CVBS_AIN5 0x04 168 #define ADV7182_INPUT_CVBS_AIN6 0x05 169 #define ADV7182_INPUT_CVBS_AIN7 0x06 170 #define ADV7182_INPUT_CVBS_AIN8 0x07 171 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 172 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 173 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 174 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 175 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 176 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 177 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 178 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 179 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 180 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 181 182 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 183 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 184 185 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 186 187 /* Initial number of frames to skip to avoid possible garbage */ 188 #define ADV7180_NUM_OF_SKIP_FRAMES 2 189 190 struct adv7180_state; 191 192 #define ADV7180_FLAG_RESET_POWERED BIT(0) 193 #define ADV7180_FLAG_V2 BIT(1) 194 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 195 #define ADV7180_FLAG_I2P BIT(3) 196 197 struct adv7180_chip_info { 198 unsigned int flags; 199 unsigned int valid_input_mask; 200 int (*set_std)(struct adv7180_state *st, unsigned int std); 201 int (*select_input)(struct adv7180_state *st, unsigned int input); 202 int (*init)(struct adv7180_state *state); 203 }; 204 205 struct adv7180_state { 206 struct v4l2_ctrl_handler ctrl_hdl; 207 struct v4l2_subdev sd; 208 struct media_pad pad; 209 struct mutex mutex; /* mutual excl. when accessing chip */ 210 int irq; 211 struct gpio_desc *pwdn_gpio; 212 struct gpio_desc *rst_gpio; 213 v4l2_std_id curr_norm; 214 bool powered; 215 bool streaming; 216 u8 input; 217 218 struct i2c_client *client; 219 unsigned int register_page; 220 struct i2c_client *csi_client; 221 struct i2c_client *vpp_client; 222 const struct adv7180_chip_info *chip_info; 223 enum v4l2_field field; 224 bool force_bt656_4; 225 }; 226 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 227 struct adv7180_state, \ 228 ctrl_hdl)->sd) 229 230 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 231 { 232 if (state->register_page != page) { 233 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 234 page); 235 state->register_page = page; 236 } 237 238 return 0; 239 } 240 241 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 242 unsigned int value) 243 { 244 lockdep_assert_held(&state->mutex); 245 adv7180_select_page(state, reg >> 8); 246 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 247 } 248 249 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 250 { 251 lockdep_assert_held(&state->mutex); 252 adv7180_select_page(state, reg >> 8); 253 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 254 } 255 256 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 257 unsigned int value) 258 { 259 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 260 } 261 262 static int adv7180_set_video_standard(struct adv7180_state *state, 263 unsigned int std) 264 { 265 return state->chip_info->set_std(state, std); 266 } 267 268 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 269 unsigned int value) 270 { 271 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 272 } 273 274 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 275 { 276 /* in case V4L2_IN_ST_NO_SIGNAL */ 277 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 278 return V4L2_STD_UNKNOWN; 279 280 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 281 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 282 return V4L2_STD_NTSC; 283 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 284 return V4L2_STD_NTSC_443; 285 case ADV7180_STATUS1_AUTOD_PAL_M: 286 return V4L2_STD_PAL_M; 287 case ADV7180_STATUS1_AUTOD_PAL_60: 288 return V4L2_STD_PAL_60; 289 case ADV7180_STATUS1_AUTOD_PAL_B_G: 290 return V4L2_STD_PAL; 291 case ADV7180_STATUS1_AUTOD_SECAM: 292 return V4L2_STD_SECAM; 293 case ADV7180_STATUS1_AUTOD_PAL_COMB: 294 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 295 case ADV7180_STATUS1_AUTOD_SECAM_525: 296 return V4L2_STD_SECAM; 297 default: 298 return V4L2_STD_UNKNOWN; 299 } 300 } 301 302 static int v4l2_std_to_adv7180(v4l2_std_id std) 303 { 304 if (std == V4L2_STD_PAL_60) 305 return ADV7180_STD_PAL60; 306 if (std == V4L2_STD_NTSC_443) 307 return ADV7180_STD_NTSC_443; 308 if (std == V4L2_STD_PAL_N) 309 return ADV7180_STD_PAL_N; 310 if (std == V4L2_STD_PAL_M) 311 return ADV7180_STD_PAL_M; 312 if (std == V4L2_STD_PAL_Nc) 313 return ADV7180_STD_PAL_COMB_N; 314 315 if (std & V4L2_STD_PAL) 316 return ADV7180_STD_PAL_BG; 317 if (std & V4L2_STD_NTSC) 318 return ADV7180_STD_NTSC_M; 319 if (std & V4L2_STD_SECAM) 320 return ADV7180_STD_PAL_SECAM; 321 322 return -EINVAL; 323 } 324 325 static u32 adv7180_status_to_v4l2(u8 status1) 326 { 327 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 328 return V4L2_IN_ST_NO_SIGNAL; 329 330 return 0; 331 } 332 333 static int __adv7180_status(struct adv7180_state *state, u32 *status, 334 v4l2_std_id *std) 335 { 336 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 337 338 if (status1 < 0) 339 return status1; 340 341 if (status) 342 *status = adv7180_status_to_v4l2(status1); 343 if (std) 344 *std = adv7180_std_to_v4l2(status1); 345 346 return 0; 347 } 348 349 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 350 { 351 return container_of(sd, struct adv7180_state, sd); 352 } 353 354 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 355 { 356 struct adv7180_state *state = to_state(sd); 357 int err = mutex_lock_interruptible(&state->mutex); 358 if (err) 359 return err; 360 361 if (state->streaming) { 362 err = -EBUSY; 363 goto unlock; 364 } 365 366 err = adv7180_set_video_standard(state, 367 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 368 if (err) 369 goto unlock; 370 371 msleep(100); 372 __adv7180_status(state, NULL, std); 373 374 err = v4l2_std_to_adv7180(state->curr_norm); 375 if (err < 0) 376 goto unlock; 377 378 err = adv7180_set_video_standard(state, err); 379 380 unlock: 381 mutex_unlock(&state->mutex); 382 return err; 383 } 384 385 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 386 u32 output, u32 config) 387 { 388 struct adv7180_state *state = to_state(sd); 389 int ret = mutex_lock_interruptible(&state->mutex); 390 391 if (ret) 392 return ret; 393 394 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 395 ret = -EINVAL; 396 goto out; 397 } 398 399 ret = state->chip_info->select_input(state, input); 400 401 if (ret == 0) 402 state->input = input; 403 out: 404 mutex_unlock(&state->mutex); 405 return ret; 406 } 407 408 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 409 { 410 struct adv7180_state *state = to_state(sd); 411 int ret = mutex_lock_interruptible(&state->mutex); 412 if (ret) 413 return ret; 414 415 ret = __adv7180_status(state, status, NULL); 416 mutex_unlock(&state->mutex); 417 return ret; 418 } 419 420 static int adv7180_program_std(struct adv7180_state *state) 421 { 422 int ret; 423 424 ret = v4l2_std_to_adv7180(state->curr_norm); 425 if (ret < 0) 426 return ret; 427 428 ret = adv7180_set_video_standard(state, ret); 429 if (ret < 0) 430 return ret; 431 return 0; 432 } 433 434 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 435 { 436 struct adv7180_state *state = to_state(sd); 437 int ret = mutex_lock_interruptible(&state->mutex); 438 439 if (ret) 440 return ret; 441 442 /* Make sure we can support this std */ 443 ret = v4l2_std_to_adv7180(std); 444 if (ret < 0) 445 goto out; 446 447 state->curr_norm = std; 448 449 ret = adv7180_program_std(state); 450 out: 451 mutex_unlock(&state->mutex); 452 return ret; 453 } 454 455 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 456 { 457 struct adv7180_state *state = to_state(sd); 458 459 *norm = state->curr_norm; 460 461 return 0; 462 } 463 464 static int adv7180_g_frame_interval(struct v4l2_subdev *sd, 465 struct v4l2_subdev_frame_interval *fi) 466 { 467 struct adv7180_state *state = to_state(sd); 468 469 if (state->curr_norm & V4L2_STD_525_60) { 470 fi->interval.numerator = 1001; 471 fi->interval.denominator = 30000; 472 } else { 473 fi->interval.numerator = 1; 474 fi->interval.denominator = 25; 475 } 476 477 return 0; 478 } 479 480 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 481 { 482 if (!state->pwdn_gpio) 483 return; 484 485 if (on) { 486 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 487 usleep_range(5000, 10000); 488 } else { 489 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 490 } 491 } 492 493 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on) 494 { 495 if (!state->rst_gpio) 496 return; 497 498 if (on) { 499 gpiod_set_value_cansleep(state->rst_gpio, 1); 500 } else { 501 gpiod_set_value_cansleep(state->rst_gpio, 0); 502 usleep_range(5000, 10000); 503 } 504 } 505 506 static int adv7180_set_power(struct adv7180_state *state, bool on) 507 { 508 u8 val; 509 int ret; 510 511 if (on) 512 val = ADV7180_PWR_MAN_ON; 513 else 514 val = ADV7180_PWR_MAN_OFF; 515 516 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 517 if (ret) 518 return ret; 519 520 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 521 if (on) { 522 adv7180_csi_write(state, 0xDE, 0x02); 523 adv7180_csi_write(state, 0xD2, 0xF7); 524 adv7180_csi_write(state, 0xD8, 0x65); 525 adv7180_csi_write(state, 0xE0, 0x09); 526 adv7180_csi_write(state, 0x2C, 0x00); 527 if (state->field == V4L2_FIELD_NONE) 528 adv7180_csi_write(state, 0x1D, 0x80); 529 adv7180_csi_write(state, 0x00, 0x00); 530 } else { 531 adv7180_csi_write(state, 0x00, 0x80); 532 } 533 } 534 535 return 0; 536 } 537 538 static int adv7180_s_power(struct v4l2_subdev *sd, int on) 539 { 540 struct adv7180_state *state = to_state(sd); 541 int ret; 542 543 ret = mutex_lock_interruptible(&state->mutex); 544 if (ret) 545 return ret; 546 547 ret = adv7180_set_power(state, on); 548 if (ret == 0) 549 state->powered = on; 550 551 mutex_unlock(&state->mutex); 552 return ret; 553 } 554 555 static const char * const test_pattern_menu[] = { 556 "Single color", 557 "Color bars", 558 "Luma ramp", 559 "Boundary box", 560 "Disable", 561 }; 562 563 static int adv7180_test_pattern(struct adv7180_state *state, int value) 564 { 565 unsigned int reg = 0; 566 567 /* Map menu value into register value */ 568 if (value < 3) 569 reg = value; 570 if (value == 3) 571 reg = 5; 572 573 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg); 574 575 if (value == ARRAY_SIZE(test_pattern_menu) - 1) { 576 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 577 reg &= ~ADV7180_DEF_VAL_EN; 578 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 579 return 0; 580 } 581 582 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y); 583 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN; 584 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg); 585 586 return 0; 587 } 588 589 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 590 { 591 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 592 struct adv7180_state *state = to_state(sd); 593 int ret = mutex_lock_interruptible(&state->mutex); 594 int val; 595 596 if (ret) 597 return ret; 598 val = ctrl->val; 599 switch (ctrl->id) { 600 case V4L2_CID_BRIGHTNESS: 601 ret = adv7180_write(state, ADV7180_REG_BRI, val); 602 break; 603 case V4L2_CID_HUE: 604 /*Hue is inverted according to HSL chart */ 605 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 606 break; 607 case V4L2_CID_CONTRAST: 608 ret = adv7180_write(state, ADV7180_REG_CON, val); 609 break; 610 case V4L2_CID_SATURATION: 611 /* 612 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 613 *Let's not confuse the user, everybody understands saturation 614 */ 615 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 616 if (ret < 0) 617 break; 618 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 619 break; 620 case V4L2_CID_ADV_FAST_SWITCH: 621 if (ctrl->val) { 622 /* ADI required write */ 623 adv7180_write(state, 0x80d9, 0x44); 624 adv7180_write(state, ADV7180_REG_FLCONTROL, 625 ADV7180_FLCONTROL_FL_ENABLE); 626 } else { 627 /* ADI required write */ 628 adv7180_write(state, 0x80d9, 0xc4); 629 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 630 } 631 break; 632 case V4L2_CID_TEST_PATTERN: 633 ret = adv7180_test_pattern(state, val); 634 break; 635 default: 636 ret = -EINVAL; 637 } 638 639 mutex_unlock(&state->mutex); 640 return ret; 641 } 642 643 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 644 .s_ctrl = adv7180_s_ctrl, 645 }; 646 647 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 648 .ops = &adv7180_ctrl_ops, 649 .id = V4L2_CID_ADV_FAST_SWITCH, 650 .name = "Fast Switching", 651 .type = V4L2_CTRL_TYPE_BOOLEAN, 652 .min = 0, 653 .max = 1, 654 .step = 1, 655 }; 656 657 static int adv7180_init_controls(struct adv7180_state *state) 658 { 659 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 660 661 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 662 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 663 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 664 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 665 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 666 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 667 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 668 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 669 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 670 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 671 V4L2_CID_HUE, ADV7180_HUE_MIN, 672 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 673 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 674 675 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops, 676 V4L2_CID_TEST_PATTERN, 677 ARRAY_SIZE(test_pattern_menu) - 1, 678 0, ARRAY_SIZE(test_pattern_menu) - 1, 679 test_pattern_menu); 680 681 state->sd.ctrl_handler = &state->ctrl_hdl; 682 if (state->ctrl_hdl.error) { 683 int err = state->ctrl_hdl.error; 684 685 v4l2_ctrl_handler_free(&state->ctrl_hdl); 686 return err; 687 } 688 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 689 690 return 0; 691 } 692 static void adv7180_exit_controls(struct adv7180_state *state) 693 { 694 v4l2_ctrl_handler_free(&state->ctrl_hdl); 695 } 696 697 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 698 struct v4l2_subdev_state *sd_state, 699 struct v4l2_subdev_mbus_code_enum *code) 700 { 701 if (code->index != 0) 702 return -EINVAL; 703 704 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 705 706 return 0; 707 } 708 709 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 710 struct v4l2_mbus_framefmt *fmt) 711 { 712 struct adv7180_state *state = to_state(sd); 713 714 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 715 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 716 fmt->width = 720; 717 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 718 719 if (state->field == V4L2_FIELD_ALTERNATE) 720 fmt->height /= 2; 721 722 return 0; 723 } 724 725 static int adv7180_set_field_mode(struct adv7180_state *state) 726 { 727 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 728 return 0; 729 730 if (state->field == V4L2_FIELD_NONE) { 731 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 732 adv7180_csi_write(state, 0x01, 0x20); 733 adv7180_csi_write(state, 0x02, 0x28); 734 adv7180_csi_write(state, 0x03, 0x38); 735 adv7180_csi_write(state, 0x04, 0x30); 736 adv7180_csi_write(state, 0x05, 0x30); 737 adv7180_csi_write(state, 0x06, 0x80); 738 adv7180_csi_write(state, 0x07, 0x70); 739 adv7180_csi_write(state, 0x08, 0x50); 740 } 741 adv7180_vpp_write(state, 0xa3, 0x00); 742 adv7180_vpp_write(state, 0x5b, 0x00); 743 adv7180_vpp_write(state, 0x55, 0x80); 744 } else { 745 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 746 adv7180_csi_write(state, 0x01, 0x18); 747 adv7180_csi_write(state, 0x02, 0x18); 748 adv7180_csi_write(state, 0x03, 0x30); 749 adv7180_csi_write(state, 0x04, 0x20); 750 adv7180_csi_write(state, 0x05, 0x28); 751 adv7180_csi_write(state, 0x06, 0x40); 752 adv7180_csi_write(state, 0x07, 0x58); 753 adv7180_csi_write(state, 0x08, 0x30); 754 } 755 adv7180_vpp_write(state, 0xa3, 0x70); 756 adv7180_vpp_write(state, 0x5b, 0x80); 757 adv7180_vpp_write(state, 0x55, 0x00); 758 } 759 760 return 0; 761 } 762 763 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 764 struct v4l2_subdev_state *sd_state, 765 struct v4l2_subdev_format *format) 766 { 767 struct adv7180_state *state = to_state(sd); 768 769 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 770 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0); 771 } else { 772 adv7180_mbus_fmt(sd, &format->format); 773 format->format.field = state->field; 774 } 775 776 return 0; 777 } 778 779 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 780 struct v4l2_subdev_state *sd_state, 781 struct v4l2_subdev_format *format) 782 { 783 struct adv7180_state *state = to_state(sd); 784 struct v4l2_mbus_framefmt *framefmt; 785 int ret; 786 787 switch (format->format.field) { 788 case V4L2_FIELD_NONE: 789 if (state->chip_info->flags & ADV7180_FLAG_I2P) 790 break; 791 fallthrough; 792 default: 793 format->format.field = V4L2_FIELD_ALTERNATE; 794 break; 795 } 796 797 ret = adv7180_mbus_fmt(sd, &format->format); 798 799 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 800 if (state->field != format->format.field) { 801 state->field = format->format.field; 802 adv7180_set_power(state, false); 803 adv7180_set_field_mode(state); 804 adv7180_set_power(state, true); 805 } 806 } else { 807 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0); 808 *framefmt = format->format; 809 } 810 811 return ret; 812 } 813 814 static int adv7180_init_cfg(struct v4l2_subdev *sd, 815 struct v4l2_subdev_state *sd_state) 816 { 817 struct v4l2_subdev_format fmt = { 818 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 819 : V4L2_SUBDEV_FORMAT_ACTIVE, 820 }; 821 822 return adv7180_set_pad_format(sd, sd_state, &fmt); 823 } 824 825 static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 826 unsigned int pad, 827 struct v4l2_mbus_config *cfg) 828 { 829 struct adv7180_state *state = to_state(sd); 830 831 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 832 cfg->type = V4L2_MBUS_CSI2_DPHY; 833 cfg->bus.mipi_csi2.num_data_lanes = 1; 834 cfg->bus.mipi_csi2.flags = 0; 835 } else { 836 /* 837 * The ADV7180 sensor supports BT.601/656 output modes. 838 * The BT.656 is default and not yet configurable by s/w. 839 */ 840 cfg->bus.parallel.flags = V4L2_MBUS_MASTER | 841 V4L2_MBUS_PCLK_SAMPLE_RISING | 842 V4L2_MBUS_DATA_ACTIVE_HIGH; 843 cfg->type = V4L2_MBUS_BT656; 844 } 845 846 return 0; 847 } 848 849 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 850 { 851 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 852 853 return 0; 854 } 855 856 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) 857 { 858 struct adv7180_state *state = to_state(sd); 859 860 if (state->curr_norm & V4L2_STD_525_60) { 861 aspect->numerator = 11; 862 aspect->denominator = 10; 863 } else { 864 aspect->numerator = 54; 865 aspect->denominator = 59; 866 } 867 868 return 0; 869 } 870 871 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 872 { 873 *norm = V4L2_STD_ALL; 874 return 0; 875 } 876 877 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 878 { 879 struct adv7180_state *state = to_state(sd); 880 int ret; 881 882 /* It's always safe to stop streaming, no need to take the lock */ 883 if (!enable) { 884 state->streaming = enable; 885 return 0; 886 } 887 888 /* Must wait until querystd released the lock */ 889 ret = mutex_lock_interruptible(&state->mutex); 890 if (ret) 891 return ret; 892 state->streaming = enable; 893 mutex_unlock(&state->mutex); 894 return 0; 895 } 896 897 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 898 struct v4l2_fh *fh, 899 struct v4l2_event_subscription *sub) 900 { 901 switch (sub->type) { 902 case V4L2_EVENT_SOURCE_CHANGE: 903 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 904 case V4L2_EVENT_CTRL: 905 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 906 default: 907 return -EINVAL; 908 } 909 } 910 911 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 912 .s_std = adv7180_s_std, 913 .g_std = adv7180_g_std, 914 .g_frame_interval = adv7180_g_frame_interval, 915 .querystd = adv7180_querystd, 916 .g_input_status = adv7180_g_input_status, 917 .s_routing = adv7180_s_routing, 918 .g_pixelaspect = adv7180_g_pixelaspect, 919 .g_tvnorms = adv7180_g_tvnorms, 920 .s_stream = adv7180_s_stream, 921 }; 922 923 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 924 .s_power = adv7180_s_power, 925 .subscribe_event = adv7180_subscribe_event, 926 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 927 }; 928 929 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 930 .init_cfg = adv7180_init_cfg, 931 .enum_mbus_code = adv7180_enum_mbus_code, 932 .set_fmt = adv7180_set_pad_format, 933 .get_fmt = adv7180_get_pad_format, 934 .get_mbus_config = adv7180_get_mbus_config, 935 }; 936 937 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 938 .g_skip_frames = adv7180_get_skip_frames, 939 }; 940 941 static const struct v4l2_subdev_ops adv7180_ops = { 942 .core = &adv7180_core_ops, 943 .video = &adv7180_video_ops, 944 .pad = &adv7180_pad_ops, 945 .sensor = &adv7180_sensor_ops, 946 }; 947 948 static irqreturn_t adv7180_irq(int irq, void *devid) 949 { 950 struct adv7180_state *state = devid; 951 u8 isr3; 952 953 mutex_lock(&state->mutex); 954 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 955 /* clear */ 956 adv7180_write(state, ADV7180_REG_ICR3, isr3); 957 958 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 959 static const struct v4l2_event src_ch = { 960 .type = V4L2_EVENT_SOURCE_CHANGE, 961 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 962 }; 963 964 v4l2_subdev_notify_event(&state->sd, &src_ch); 965 } 966 mutex_unlock(&state->mutex); 967 968 return IRQ_HANDLED; 969 } 970 971 static int adv7180_init(struct adv7180_state *state) 972 { 973 int ret; 974 975 /* ITU-R BT.656-4 compatible */ 976 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 977 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 978 if (ret < 0) 979 return ret; 980 981 /* Manually set V bit end position in NTSC mode */ 982 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 983 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 984 } 985 986 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 987 { 988 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 989 (std << 4) | state->input); 990 } 991 992 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 993 { 994 int ret; 995 996 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 997 if (ret < 0) 998 return ret; 999 1000 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 1001 ret |= input; 1002 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 1003 } 1004 1005 static int adv7182_init(struct adv7180_state *state) 1006 { 1007 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 1008 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 1009 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 1010 1011 if (state->chip_info->flags & ADV7180_FLAG_I2P) 1012 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 1013 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 1014 1015 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1016 /* ADI recommended writes for improved video quality */ 1017 adv7180_write(state, 0x0080, 0x51); 1018 adv7180_write(state, 0x0081, 0x51); 1019 adv7180_write(state, 0x0082, 0x68); 1020 } 1021 1022 /* ADI required writes */ 1023 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1024 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 1025 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 1026 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 1027 } else { 1028 if (state->chip_info->flags & ADV7180_FLAG_V2) { 1029 if (state->force_bt656_4) { 1030 /* ITU-R BT.656-4 compatible */ 1031 adv7180_write(state, 1032 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1033 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 1034 /* Manually set NEWAVMODE */ 1035 adv7180_write(state, 1036 ADV7180_REG_VSYNC_FIELD_CTL_1, 1037 ADV7180_VSYNC_FIELD_CTL_1_NEWAV); 1038 /* Manually set V bit end position in NTSC mode */ 1039 adv7180_write(state, 1040 ADV7180_REG_NTSC_V_BIT_END, 1041 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 1042 } else { 1043 adv7180_write(state, 1044 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1045 0x17); 1046 } 1047 } 1048 else 1049 adv7180_write(state, 1050 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1051 0x07); 1052 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 1053 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 1054 } 1055 1056 adv7180_write(state, 0x0013, 0x00); 1057 1058 return 0; 1059 } 1060 1061 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 1062 { 1063 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); 1064 } 1065 1066 enum adv7182_input_type { 1067 ADV7182_INPUT_TYPE_CVBS, 1068 ADV7182_INPUT_TYPE_DIFF_CVBS, 1069 ADV7182_INPUT_TYPE_SVIDEO, 1070 ADV7182_INPUT_TYPE_YPBPR, 1071 }; 1072 1073 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 1074 { 1075 switch (input) { 1076 case ADV7182_INPUT_CVBS_AIN1: 1077 case ADV7182_INPUT_CVBS_AIN2: 1078 case ADV7182_INPUT_CVBS_AIN3: 1079 case ADV7182_INPUT_CVBS_AIN4: 1080 case ADV7182_INPUT_CVBS_AIN5: 1081 case ADV7182_INPUT_CVBS_AIN6: 1082 case ADV7182_INPUT_CVBS_AIN7: 1083 case ADV7182_INPUT_CVBS_AIN8: 1084 return ADV7182_INPUT_TYPE_CVBS; 1085 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 1086 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 1087 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 1088 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 1089 return ADV7182_INPUT_TYPE_SVIDEO; 1090 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1091 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1092 return ADV7182_INPUT_TYPE_YPBPR; 1093 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1094 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1095 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1096 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1097 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1098 default: /* Will never happen */ 1099 return 0; 1100 } 1101 } 1102 1103 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1104 static unsigned int adv7182_lbias_settings[][3] = { 1105 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1106 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1107 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1108 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1109 }; 1110 1111 static unsigned int adv7280_lbias_settings[][3] = { 1112 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1113 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1114 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1115 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1116 }; 1117 1118 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1119 { 1120 enum adv7182_input_type input_type; 1121 unsigned int *lbias; 1122 unsigned int i; 1123 int ret; 1124 1125 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1126 if (ret) 1127 return ret; 1128 1129 /* Reset clamp circuitry - ADI recommended writes */ 1130 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1131 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1132 1133 input_type = adv7182_get_input_type(input); 1134 1135 switch (input_type) { 1136 case ADV7182_INPUT_TYPE_CVBS: 1137 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1138 /* ADI recommends to use the SH1 filter */ 1139 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1140 break; 1141 default: 1142 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1143 break; 1144 } 1145 1146 if (state->chip_info->flags & ADV7180_FLAG_V2) 1147 lbias = adv7280_lbias_settings[input_type]; 1148 else 1149 lbias = adv7182_lbias_settings[input_type]; 1150 1151 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1152 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1153 1154 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1155 /* ADI required writes to make differential CVBS work */ 1156 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1157 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1158 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1159 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1160 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1161 } else { 1162 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1163 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1164 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1165 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1166 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1167 } 1168 1169 return 0; 1170 } 1171 1172 static const struct adv7180_chip_info adv7180_info = { 1173 .flags = ADV7180_FLAG_RESET_POWERED, 1174 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1175 * all inputs and let the card driver take care of validation 1176 */ 1177 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1178 BIT(ADV7180_INPUT_CVBS_AIN2) | 1179 BIT(ADV7180_INPUT_CVBS_AIN3) | 1180 BIT(ADV7180_INPUT_CVBS_AIN4) | 1181 BIT(ADV7180_INPUT_CVBS_AIN5) | 1182 BIT(ADV7180_INPUT_CVBS_AIN6) | 1183 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1184 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1185 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1186 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1187 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1188 .init = adv7180_init, 1189 .set_std = adv7180_set_std, 1190 .select_input = adv7180_select_input, 1191 }; 1192 1193 static const struct adv7180_chip_info adv7182_info = { 1194 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1195 BIT(ADV7182_INPUT_CVBS_AIN2) | 1196 BIT(ADV7182_INPUT_CVBS_AIN3) | 1197 BIT(ADV7182_INPUT_CVBS_AIN4) | 1198 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1199 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1200 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1201 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1202 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1203 .init = adv7182_init, 1204 .set_std = adv7182_set_std, 1205 .select_input = adv7182_select_input, 1206 }; 1207 1208 static const struct adv7180_chip_info adv7280_info = { 1209 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1210 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1211 BIT(ADV7182_INPUT_CVBS_AIN2) | 1212 BIT(ADV7182_INPUT_CVBS_AIN3) | 1213 BIT(ADV7182_INPUT_CVBS_AIN4) | 1214 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1215 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1216 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1217 .init = adv7182_init, 1218 .set_std = adv7182_set_std, 1219 .select_input = adv7182_select_input, 1220 }; 1221 1222 static const struct adv7180_chip_info adv7280_m_info = { 1223 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1224 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1225 BIT(ADV7182_INPUT_CVBS_AIN2) | 1226 BIT(ADV7182_INPUT_CVBS_AIN3) | 1227 BIT(ADV7182_INPUT_CVBS_AIN4) | 1228 BIT(ADV7182_INPUT_CVBS_AIN5) | 1229 BIT(ADV7182_INPUT_CVBS_AIN6) | 1230 BIT(ADV7182_INPUT_CVBS_AIN7) | 1231 BIT(ADV7182_INPUT_CVBS_AIN8) | 1232 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1233 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1234 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1235 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1236 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1237 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1238 .init = adv7182_init, 1239 .set_std = adv7182_set_std, 1240 .select_input = adv7182_select_input, 1241 }; 1242 1243 static const struct adv7180_chip_info adv7281_info = { 1244 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1245 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1246 BIT(ADV7182_INPUT_CVBS_AIN2) | 1247 BIT(ADV7182_INPUT_CVBS_AIN7) | 1248 BIT(ADV7182_INPUT_CVBS_AIN8) | 1249 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1250 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1251 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1252 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1253 .init = adv7182_init, 1254 .set_std = adv7182_set_std, 1255 .select_input = adv7182_select_input, 1256 }; 1257 1258 static const struct adv7180_chip_info adv7281_m_info = { 1259 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1260 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1261 BIT(ADV7182_INPUT_CVBS_AIN2) | 1262 BIT(ADV7182_INPUT_CVBS_AIN3) | 1263 BIT(ADV7182_INPUT_CVBS_AIN4) | 1264 BIT(ADV7182_INPUT_CVBS_AIN7) | 1265 BIT(ADV7182_INPUT_CVBS_AIN8) | 1266 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1267 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1268 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1269 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1270 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1271 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1272 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1273 .init = adv7182_init, 1274 .set_std = adv7182_set_std, 1275 .select_input = adv7182_select_input, 1276 }; 1277 1278 static const struct adv7180_chip_info adv7281_ma_info = { 1279 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1280 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1281 BIT(ADV7182_INPUT_CVBS_AIN2) | 1282 BIT(ADV7182_INPUT_CVBS_AIN3) | 1283 BIT(ADV7182_INPUT_CVBS_AIN4) | 1284 BIT(ADV7182_INPUT_CVBS_AIN5) | 1285 BIT(ADV7182_INPUT_CVBS_AIN6) | 1286 BIT(ADV7182_INPUT_CVBS_AIN7) | 1287 BIT(ADV7182_INPUT_CVBS_AIN8) | 1288 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1289 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1290 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1291 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1292 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1293 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1294 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1295 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1296 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1297 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1298 .init = adv7182_init, 1299 .set_std = adv7182_set_std, 1300 .select_input = adv7182_select_input, 1301 }; 1302 1303 static const struct adv7180_chip_info adv7282_info = { 1304 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1305 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1306 BIT(ADV7182_INPUT_CVBS_AIN2) | 1307 BIT(ADV7182_INPUT_CVBS_AIN7) | 1308 BIT(ADV7182_INPUT_CVBS_AIN8) | 1309 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1310 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1311 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1312 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1313 .init = adv7182_init, 1314 .set_std = adv7182_set_std, 1315 .select_input = adv7182_select_input, 1316 }; 1317 1318 static const struct adv7180_chip_info adv7282_m_info = { 1319 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1320 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1321 BIT(ADV7182_INPUT_CVBS_AIN2) | 1322 BIT(ADV7182_INPUT_CVBS_AIN3) | 1323 BIT(ADV7182_INPUT_CVBS_AIN4) | 1324 BIT(ADV7182_INPUT_CVBS_AIN7) | 1325 BIT(ADV7182_INPUT_CVBS_AIN8) | 1326 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1327 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1328 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1329 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1330 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1331 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1332 .init = adv7182_init, 1333 .set_std = adv7182_set_std, 1334 .select_input = adv7182_select_input, 1335 }; 1336 1337 static int init_device(struct adv7180_state *state) 1338 { 1339 int ret; 1340 1341 mutex_lock(&state->mutex); 1342 1343 adv7180_set_power_pin(state, true); 1344 adv7180_set_reset_pin(state, false); 1345 1346 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1347 usleep_range(5000, 10000); 1348 1349 ret = state->chip_info->init(state); 1350 if (ret) 1351 goto out_unlock; 1352 1353 ret = adv7180_program_std(state); 1354 if (ret) 1355 goto out_unlock; 1356 1357 adv7180_set_field_mode(state); 1358 1359 /* register for interrupts */ 1360 if (state->irq > 0) { 1361 /* config the Interrupt pin to be active low */ 1362 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1363 ADV7180_ICONF1_ACTIVE_LOW | 1364 ADV7180_ICONF1_PSYNC_ONLY); 1365 if (ret < 0) 1366 goto out_unlock; 1367 1368 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1369 if (ret < 0) 1370 goto out_unlock; 1371 1372 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1373 if (ret < 0) 1374 goto out_unlock; 1375 1376 /* enable AD change interrupts interrupts */ 1377 ret = adv7180_write(state, ADV7180_REG_IMR3, 1378 ADV7180_IRQ3_AD_CHANGE); 1379 if (ret < 0) 1380 goto out_unlock; 1381 1382 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1383 if (ret < 0) 1384 goto out_unlock; 1385 } 1386 1387 out_unlock: 1388 mutex_unlock(&state->mutex); 1389 1390 return ret; 1391 } 1392 1393 static int adv7180_probe(struct i2c_client *client, 1394 const struct i2c_device_id *id) 1395 { 1396 struct device_node *np = client->dev.of_node; 1397 struct adv7180_state *state; 1398 struct v4l2_subdev *sd; 1399 int ret; 1400 1401 /* Check if the adapter supports the needed features */ 1402 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1403 return -EIO; 1404 1405 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1406 if (state == NULL) 1407 return -ENOMEM; 1408 1409 state->client = client; 1410 state->field = V4L2_FIELD_ALTERNATE; 1411 state->chip_info = (struct adv7180_chip_info *)id->driver_data; 1412 1413 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1414 GPIOD_OUT_HIGH); 1415 if (IS_ERR(state->pwdn_gpio)) { 1416 ret = PTR_ERR(state->pwdn_gpio); 1417 v4l_err(client, "request for power pin failed: %d\n", ret); 1418 return ret; 1419 } 1420 1421 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1422 GPIOD_OUT_HIGH); 1423 if (IS_ERR(state->rst_gpio)) { 1424 ret = PTR_ERR(state->rst_gpio); 1425 v4l_err(client, "request for reset pin failed: %d\n", ret); 1426 return ret; 1427 } 1428 1429 if (of_property_read_bool(np, "adv,force-bt656-4")) 1430 state->force_bt656_4 = true; 1431 1432 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1433 state->csi_client = i2c_new_dummy_device(client->adapter, 1434 ADV7180_DEFAULT_CSI_I2C_ADDR); 1435 if (IS_ERR(state->csi_client)) 1436 return PTR_ERR(state->csi_client); 1437 } 1438 1439 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1440 state->vpp_client = i2c_new_dummy_device(client->adapter, 1441 ADV7180_DEFAULT_VPP_I2C_ADDR); 1442 if (IS_ERR(state->vpp_client)) { 1443 ret = PTR_ERR(state->vpp_client); 1444 goto err_unregister_csi_client; 1445 } 1446 } 1447 1448 state->irq = client->irq; 1449 mutex_init(&state->mutex); 1450 state->curr_norm = V4L2_STD_NTSC; 1451 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1452 state->powered = true; 1453 else 1454 state->powered = false; 1455 state->input = 0; 1456 sd = &state->sd; 1457 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1458 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1459 1460 ret = adv7180_init_controls(state); 1461 if (ret) 1462 goto err_unregister_vpp_client; 1463 1464 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1465 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1466 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1467 if (ret) 1468 goto err_free_ctrl; 1469 1470 ret = init_device(state); 1471 if (ret) 1472 goto err_media_entity_cleanup; 1473 1474 if (state->irq) { 1475 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1476 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1477 KBUILD_MODNAME, state); 1478 if (ret) 1479 goto err_media_entity_cleanup; 1480 } 1481 1482 ret = v4l2_async_register_subdev(sd); 1483 if (ret) 1484 goto err_free_irq; 1485 1486 mutex_lock(&state->mutex); 1487 ret = adv7180_read(state, ADV7180_REG_IDENT); 1488 mutex_unlock(&state->mutex); 1489 if (ret < 0) 1490 goto err_v4l2_async_unregister; 1491 1492 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n", 1493 ret, client->addr, client->adapter->name); 1494 1495 return 0; 1496 1497 err_v4l2_async_unregister: 1498 v4l2_async_unregister_subdev(sd); 1499 err_free_irq: 1500 if (state->irq > 0) 1501 free_irq(client->irq, state); 1502 err_media_entity_cleanup: 1503 media_entity_cleanup(&sd->entity); 1504 err_free_ctrl: 1505 adv7180_exit_controls(state); 1506 err_unregister_vpp_client: 1507 i2c_unregister_device(state->vpp_client); 1508 err_unregister_csi_client: 1509 i2c_unregister_device(state->csi_client); 1510 mutex_destroy(&state->mutex); 1511 return ret; 1512 } 1513 1514 static int adv7180_remove(struct i2c_client *client) 1515 { 1516 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1517 struct adv7180_state *state = to_state(sd); 1518 1519 v4l2_async_unregister_subdev(sd); 1520 1521 if (state->irq > 0) 1522 free_irq(client->irq, state); 1523 1524 media_entity_cleanup(&sd->entity); 1525 adv7180_exit_controls(state); 1526 1527 i2c_unregister_device(state->vpp_client); 1528 i2c_unregister_device(state->csi_client); 1529 1530 adv7180_set_reset_pin(state, true); 1531 adv7180_set_power_pin(state, false); 1532 1533 mutex_destroy(&state->mutex); 1534 1535 return 0; 1536 } 1537 1538 static const struct i2c_device_id adv7180_id[] = { 1539 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1540 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1541 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1542 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1543 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1544 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1545 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1546 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1547 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1548 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1549 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1550 {}, 1551 }; 1552 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1553 1554 #ifdef CONFIG_PM_SLEEP 1555 static int adv7180_suspend(struct device *dev) 1556 { 1557 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1558 struct adv7180_state *state = to_state(sd); 1559 1560 return adv7180_set_power(state, false); 1561 } 1562 1563 static int adv7180_resume(struct device *dev) 1564 { 1565 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1566 struct adv7180_state *state = to_state(sd); 1567 int ret; 1568 1569 ret = init_device(state); 1570 if (ret < 0) 1571 return ret; 1572 1573 ret = adv7180_set_power(state, state->powered); 1574 if (ret) 1575 return ret; 1576 1577 return 0; 1578 } 1579 1580 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1581 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1582 1583 #else 1584 #define ADV7180_PM_OPS NULL 1585 #endif 1586 1587 #ifdef CONFIG_OF 1588 static const struct of_device_id adv7180_of_id[] = { 1589 { .compatible = "adi,adv7180", }, 1590 { .compatible = "adi,adv7180cp", }, 1591 { .compatible = "adi,adv7180st", }, 1592 { .compatible = "adi,adv7182", }, 1593 { .compatible = "adi,adv7280", }, 1594 { .compatible = "adi,adv7280-m", }, 1595 { .compatible = "adi,adv7281", }, 1596 { .compatible = "adi,adv7281-m", }, 1597 { .compatible = "adi,adv7281-ma", }, 1598 { .compatible = "adi,adv7282", }, 1599 { .compatible = "adi,adv7282-m", }, 1600 { }, 1601 }; 1602 1603 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1604 #endif 1605 1606 static struct i2c_driver adv7180_driver = { 1607 .driver = { 1608 .name = KBUILD_MODNAME, 1609 .pm = ADV7180_PM_OPS, 1610 .of_match_table = of_match_ptr(adv7180_of_id), 1611 }, 1612 .probe = adv7180_probe, 1613 .remove = adv7180_remove, 1614 .id_table = adv7180_id, 1615 }; 1616 1617 module_i2c_driver(adv7180_driver); 1618 1619 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1620 MODULE_AUTHOR("Mocean Laboratories"); 1621 MODULE_LICENSE("GPL v2"); 1622