xref: /openbmc/linux/drivers/media/i2c/adv7180.c (revision aaeb31c0)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * adv7180.c Analog Devices ADV7180 video decoder driver
4  * Copyright (c) 2009 Intel Corporation
5  * Copyright (C) 2013 Cogent Embedded, Inc.
6  * Copyright (C) 2013 Renesas Solutions Corp.
7  */
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/errno.h>
11 #include <linux/kernel.h>
12 #include <linux/interrupt.h>
13 #include <linux/i2c.h>
14 #include <linux/slab.h>
15 #include <linux/of.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-ctrls.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
24 
25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM		0x0
26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED		0x1
27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM		0x2
28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM		0x3
29 #define ADV7180_STD_NTSC_J				0x4
30 #define ADV7180_STD_NTSC_M				0x5
31 #define ADV7180_STD_PAL60				0x6
32 #define ADV7180_STD_NTSC_443				0x7
33 #define ADV7180_STD_PAL_BG				0x8
34 #define ADV7180_STD_PAL_N				0x9
35 #define ADV7180_STD_PAL_M				0xa
36 #define ADV7180_STD_PAL_M_PED				0xb
37 #define ADV7180_STD_PAL_COMB_N				0xc
38 #define ADV7180_STD_PAL_COMB_N_PED			0xd
39 #define ADV7180_STD_PAL_SECAM				0xe
40 #define ADV7180_STD_PAL_SECAM_PED			0xf
41 
42 #define ADV7180_REG_INPUT_CONTROL			0x0000
43 #define ADV7180_INPUT_CONTROL_INSEL_MASK		0x0f
44 
45 #define ADV7182_REG_INPUT_VIDSEL			0x0002
46 #define ADV7182_REG_INPUT_RESERVED			BIT(2)
47 
48 #define ADV7180_REG_OUTPUT_CONTROL			0x0003
49 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL		0x0004
50 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS		0xC5
51 
52 #define ADV7180_REG_AUTODETECT_ENABLE			0x0007
53 #define ADV7180_AUTODETECT_DEFAULT			0x7f
54 /* Contrast */
55 #define ADV7180_REG_CON		0x0008	/*Unsigned */
56 #define ADV7180_CON_MIN		0
57 #define ADV7180_CON_DEF		128
58 #define ADV7180_CON_MAX		255
59 /* Brightness*/
60 #define ADV7180_REG_BRI		0x000a	/*Signed */
61 #define ADV7180_BRI_MIN		-128
62 #define ADV7180_BRI_DEF		0
63 #define ADV7180_BRI_MAX		127
64 /* Hue */
65 #define ADV7180_REG_HUE		0x000b	/*Signed, inverted */
66 #define ADV7180_HUE_MIN		-127
67 #define ADV7180_HUE_DEF		0
68 #define ADV7180_HUE_MAX		128
69 
70 #define ADV7180_REG_DEF_VALUE_Y	0x000c
71 #define ADV7180_DEF_VAL_EN		0x1
72 #define ADV7180_DEF_VAL_AUTO_EN	0x2
73 #define ADV7180_REG_CTRL		0x000e
74 #define ADV7180_CTRL_IRQ_SPACE		0x20
75 
76 #define ADV7180_REG_PWR_MAN		0x0f
77 #define ADV7180_PWR_MAN_ON		0x04
78 #define ADV7180_PWR_MAN_OFF		0x24
79 #define ADV7180_PWR_MAN_RES		0x80
80 
81 #define ADV7180_REG_STATUS1		0x0010
82 #define ADV7180_STATUS1_IN_LOCK		0x01
83 #define ADV7180_STATUS1_AUTOD_MASK	0x70
84 #define ADV7180_STATUS1_AUTOD_NTSM_M_J	0x00
85 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
86 #define ADV7180_STATUS1_AUTOD_PAL_M	0x20
87 #define ADV7180_STATUS1_AUTOD_PAL_60	0x30
88 #define ADV7180_STATUS1_AUTOD_PAL_B_G	0x40
89 #define ADV7180_STATUS1_AUTOD_SECAM	0x50
90 #define ADV7180_STATUS1_AUTOD_PAL_COMB	0x60
91 #define ADV7180_STATUS1_AUTOD_SECAM_525	0x70
92 
93 #define ADV7180_REG_IDENT 0x0011
94 #define ADV7180_ID_7180 0x18
95 
96 #define ADV7180_REG_STATUS3		0x0013
97 #define ADV7180_REG_ANALOG_CLAMP_CTL	0x0014
98 #define ADV7180_REG_SHAP_FILTER_CTL_1	0x0017
99 #define ADV7180_REG_CTRL_2		0x001d
100 #define ADV7180_REG_VSYNC_FIELD_CTL_1	0x0031
101 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
102 #define ADV7180_REG_MANUAL_WIN_CTL_1	0x003d
103 #define ADV7180_REG_MANUAL_WIN_CTL_2	0x003e
104 #define ADV7180_REG_MANUAL_WIN_CTL_3	0x003f
105 #define ADV7180_REG_LOCK_CNT		0x0051
106 #define ADV7180_REG_CVBS_TRIM		0x0052
107 #define ADV7180_REG_CLAMP_ADJ		0x005a
108 #define ADV7180_REG_RES_CIR		0x005f
109 #define ADV7180_REG_DIFF_MODE		0x0060
110 
111 #define ADV7180_REG_ICONF1		0x2040
112 #define ADV7180_ICONF1_ACTIVE_LOW	0x01
113 #define ADV7180_ICONF1_PSYNC_ONLY	0x10
114 #define ADV7180_ICONF1_ACTIVE_TO_CLR	0xC0
115 /* Saturation */
116 #define ADV7180_REG_SD_SAT_CB	0x00e3	/*Unsigned */
117 #define ADV7180_REG_SD_SAT_CR	0x00e4	/*Unsigned */
118 #define ADV7180_SAT_MIN		0
119 #define ADV7180_SAT_DEF		128
120 #define ADV7180_SAT_MAX		255
121 
122 #define ADV7180_IRQ1_LOCK	0x01
123 #define ADV7180_IRQ1_UNLOCK	0x02
124 #define ADV7180_REG_ISR1	0x2042
125 #define ADV7180_REG_ICR1	0x2043
126 #define ADV7180_REG_IMR1	0x2044
127 #define ADV7180_REG_IMR2	0x2048
128 #define ADV7180_IRQ3_AD_CHANGE	0x08
129 #define ADV7180_REG_ISR3	0x204A
130 #define ADV7180_REG_ICR3	0x204B
131 #define ADV7180_REG_IMR3	0x204C
132 #define ADV7180_REG_IMR4	0x2050
133 
134 #define ADV7180_REG_NTSC_V_BIT_END	0x00E6
135 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND	0x4F
136 
137 #define ADV7180_REG_VPP_SLAVE_ADDR	0xFD
138 #define ADV7180_REG_CSI_SLAVE_ADDR	0xFE
139 
140 #define ADV7180_REG_ACE_CTRL1		0x4080
141 #define ADV7180_REG_ACE_CTRL5		0x4084
142 #define ADV7180_REG_FLCONTROL		0x40e0
143 #define ADV7180_FLCONTROL_FL_ENABLE 0x1
144 
145 #define ADV7180_REG_RST_CLAMP	0x809c
146 #define ADV7180_REG_AGC_ADJ1	0x80b6
147 #define ADV7180_REG_AGC_ADJ2	0x80c0
148 
149 #define ADV7180_CSI_REG_PWRDN	0x00
150 #define ADV7180_CSI_PWRDN	0x80
151 
152 #define ADV7180_INPUT_CVBS_AIN1 0x00
153 #define ADV7180_INPUT_CVBS_AIN2 0x01
154 #define ADV7180_INPUT_CVBS_AIN3 0x02
155 #define ADV7180_INPUT_CVBS_AIN4 0x03
156 #define ADV7180_INPUT_CVBS_AIN5 0x04
157 #define ADV7180_INPUT_CVBS_AIN6 0x05
158 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
159 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
160 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
161 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
162 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
163 
164 #define ADV7182_INPUT_CVBS_AIN1 0x00
165 #define ADV7182_INPUT_CVBS_AIN2 0x01
166 #define ADV7182_INPUT_CVBS_AIN3 0x02
167 #define ADV7182_INPUT_CVBS_AIN4 0x03
168 #define ADV7182_INPUT_CVBS_AIN5 0x04
169 #define ADV7182_INPUT_CVBS_AIN6 0x05
170 #define ADV7182_INPUT_CVBS_AIN7 0x06
171 #define ADV7182_INPUT_CVBS_AIN8 0x07
172 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
173 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
174 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
175 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
176 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
177 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
178 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
179 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
180 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
181 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
182 
183 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
184 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
185 
186 #define V4L2_CID_ADV_FAST_SWITCH	(V4L2_CID_USER_ADV7180_BASE + 0x00)
187 
188 /* Initial number of frames to skip to avoid possible garbage */
189 #define ADV7180_NUM_OF_SKIP_FRAMES       2
190 
191 struct adv7180_state;
192 
193 #define ADV7180_FLAG_RESET_POWERED	BIT(0)
194 #define ADV7180_FLAG_V2			BIT(1)
195 #define ADV7180_FLAG_MIPI_CSI2		BIT(2)
196 #define ADV7180_FLAG_I2P		BIT(3)
197 
198 struct adv7180_chip_info {
199 	unsigned int flags;
200 	unsigned int valid_input_mask;
201 	int (*set_std)(struct adv7180_state *st, unsigned int std);
202 	int (*select_input)(struct adv7180_state *st, unsigned int input);
203 	int (*init)(struct adv7180_state *state);
204 };
205 
206 struct adv7180_state {
207 	struct v4l2_ctrl_handler ctrl_hdl;
208 	struct v4l2_subdev	sd;
209 	struct media_pad	pad;
210 	struct mutex		mutex; /* mutual excl. when accessing chip */
211 	int			irq;
212 	struct gpio_desc	*pwdn_gpio;
213 	struct gpio_desc	*rst_gpio;
214 	v4l2_std_id		curr_norm;
215 	bool			powered;
216 	bool			streaming;
217 	u8			input;
218 
219 	struct i2c_client	*client;
220 	unsigned int		register_page;
221 	struct i2c_client	*csi_client;
222 	struct i2c_client	*vpp_client;
223 	const struct adv7180_chip_info *chip_info;
224 	enum v4l2_field		field;
225 	bool			force_bt656_4;
226 };
227 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler,		\
228 					    struct adv7180_state,	\
229 					    ctrl_hdl)->sd)
230 
adv7180_select_page(struct adv7180_state * state,unsigned int page)231 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
232 {
233 	if (state->register_page != page) {
234 		i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
235 			page);
236 		state->register_page = page;
237 	}
238 
239 	return 0;
240 }
241 
adv7180_write(struct adv7180_state * state,unsigned int reg,unsigned int value)242 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
243 	unsigned int value)
244 {
245 	lockdep_assert_held(&state->mutex);
246 	adv7180_select_page(state, reg >> 8);
247 	return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
248 }
249 
adv7180_read(struct adv7180_state * state,unsigned int reg)250 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
251 {
252 	lockdep_assert_held(&state->mutex);
253 	adv7180_select_page(state, reg >> 8);
254 	return i2c_smbus_read_byte_data(state->client, reg & 0xff);
255 }
256 
adv7180_csi_write(struct adv7180_state * state,unsigned int reg,unsigned int value)257 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
258 	unsigned int value)
259 {
260 	return i2c_smbus_write_byte_data(state->csi_client, reg, value);
261 }
262 
adv7180_set_video_standard(struct adv7180_state * state,unsigned int std)263 static int adv7180_set_video_standard(struct adv7180_state *state,
264 	unsigned int std)
265 {
266 	return state->chip_info->set_std(state, std);
267 }
268 
adv7180_vpp_write(struct adv7180_state * state,unsigned int reg,unsigned int value)269 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
270 	unsigned int value)
271 {
272 	return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
273 }
274 
adv7180_std_to_v4l2(u8 status1)275 static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
276 {
277 	/* in case V4L2_IN_ST_NO_SIGNAL */
278 	if (!(status1 & ADV7180_STATUS1_IN_LOCK))
279 		return V4L2_STD_UNKNOWN;
280 
281 	switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
282 	case ADV7180_STATUS1_AUTOD_NTSM_M_J:
283 		return V4L2_STD_NTSC;
284 	case ADV7180_STATUS1_AUTOD_NTSC_4_43:
285 		return V4L2_STD_NTSC_443;
286 	case ADV7180_STATUS1_AUTOD_PAL_M:
287 		return V4L2_STD_PAL_M;
288 	case ADV7180_STATUS1_AUTOD_PAL_60:
289 		return V4L2_STD_PAL_60;
290 	case ADV7180_STATUS1_AUTOD_PAL_B_G:
291 		return V4L2_STD_PAL;
292 	case ADV7180_STATUS1_AUTOD_SECAM:
293 		return V4L2_STD_SECAM;
294 	case ADV7180_STATUS1_AUTOD_PAL_COMB:
295 		return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
296 	case ADV7180_STATUS1_AUTOD_SECAM_525:
297 		return V4L2_STD_SECAM;
298 	default:
299 		return V4L2_STD_UNKNOWN;
300 	}
301 }
302 
v4l2_std_to_adv7180(v4l2_std_id std)303 static int v4l2_std_to_adv7180(v4l2_std_id std)
304 {
305 	if (std == V4L2_STD_PAL_60)
306 		return ADV7180_STD_PAL60;
307 	if (std == V4L2_STD_NTSC_443)
308 		return ADV7180_STD_NTSC_443;
309 	if (std == V4L2_STD_PAL_N)
310 		return ADV7180_STD_PAL_N;
311 	if (std == V4L2_STD_PAL_M)
312 		return ADV7180_STD_PAL_M;
313 	if (std == V4L2_STD_PAL_Nc)
314 		return ADV7180_STD_PAL_COMB_N;
315 
316 	if (std & V4L2_STD_PAL)
317 		return ADV7180_STD_PAL_BG;
318 	if (std & V4L2_STD_NTSC)
319 		return ADV7180_STD_NTSC_M;
320 	if (std & V4L2_STD_SECAM)
321 		return ADV7180_STD_PAL_SECAM;
322 
323 	return -EINVAL;
324 }
325 
adv7180_status_to_v4l2(u8 status1)326 static u32 adv7180_status_to_v4l2(u8 status1)
327 {
328 	if (!(status1 & ADV7180_STATUS1_IN_LOCK))
329 		return V4L2_IN_ST_NO_SIGNAL;
330 
331 	return 0;
332 }
333 
__adv7180_status(struct adv7180_state * state,u32 * status,v4l2_std_id * std)334 static int __adv7180_status(struct adv7180_state *state, u32 *status,
335 			    v4l2_std_id *std)
336 {
337 	int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
338 
339 	if (status1 < 0)
340 		return status1;
341 
342 	if (status)
343 		*status = adv7180_status_to_v4l2(status1);
344 	if (std)
345 		*std = adv7180_std_to_v4l2(status1);
346 
347 	return 0;
348 }
349 
to_state(struct v4l2_subdev * sd)350 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
351 {
352 	return container_of(sd, struct adv7180_state, sd);
353 }
354 
adv7180_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)355 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
356 {
357 	struct adv7180_state *state = to_state(sd);
358 	int err = mutex_lock_interruptible(&state->mutex);
359 	if (err)
360 		return err;
361 
362 	if (state->streaming) {
363 		err = -EBUSY;
364 		goto unlock;
365 	}
366 
367 	err = adv7180_set_video_standard(state,
368 			ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
369 	if (err)
370 		goto unlock;
371 
372 	msleep(100);
373 	__adv7180_status(state, NULL, std);
374 
375 	err = v4l2_std_to_adv7180(state->curr_norm);
376 	if (err < 0)
377 		goto unlock;
378 
379 	err = adv7180_set_video_standard(state, err);
380 
381 unlock:
382 	mutex_unlock(&state->mutex);
383 	return err;
384 }
385 
adv7180_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)386 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
387 			     u32 output, u32 config)
388 {
389 	struct adv7180_state *state = to_state(sd);
390 	int ret = mutex_lock_interruptible(&state->mutex);
391 
392 	if (ret)
393 		return ret;
394 
395 	if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
396 		ret = -EINVAL;
397 		goto out;
398 	}
399 
400 	ret = state->chip_info->select_input(state, input);
401 
402 	if (ret == 0)
403 		state->input = input;
404 out:
405 	mutex_unlock(&state->mutex);
406 	return ret;
407 }
408 
adv7180_g_input_status(struct v4l2_subdev * sd,u32 * status)409 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
410 {
411 	struct adv7180_state *state = to_state(sd);
412 	int ret = mutex_lock_interruptible(&state->mutex);
413 	if (ret)
414 		return ret;
415 
416 	ret = __adv7180_status(state, status, NULL);
417 	mutex_unlock(&state->mutex);
418 	return ret;
419 }
420 
adv7180_program_std(struct adv7180_state * state)421 static int adv7180_program_std(struct adv7180_state *state)
422 {
423 	int ret;
424 
425 	ret = v4l2_std_to_adv7180(state->curr_norm);
426 	if (ret < 0)
427 		return ret;
428 
429 	ret = adv7180_set_video_standard(state, ret);
430 	if (ret < 0)
431 		return ret;
432 	return 0;
433 }
434 
adv7180_s_std(struct v4l2_subdev * sd,v4l2_std_id std)435 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
436 {
437 	struct adv7180_state *state = to_state(sd);
438 	int ret = mutex_lock_interruptible(&state->mutex);
439 
440 	if (ret)
441 		return ret;
442 
443 	/* Make sure we can support this std */
444 	ret = v4l2_std_to_adv7180(std);
445 	if (ret < 0)
446 		goto out;
447 
448 	state->curr_norm = std;
449 
450 	ret = adv7180_program_std(state);
451 out:
452 	mutex_unlock(&state->mutex);
453 	return ret;
454 }
455 
adv7180_g_std(struct v4l2_subdev * sd,v4l2_std_id * norm)456 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
457 {
458 	struct adv7180_state *state = to_state(sd);
459 
460 	*norm = state->curr_norm;
461 
462 	return 0;
463 }
464 
adv7180_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)465 static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
466 				    struct v4l2_subdev_frame_interval *fi)
467 {
468 	struct adv7180_state *state = to_state(sd);
469 
470 	if (state->curr_norm & V4L2_STD_525_60) {
471 		fi->interval.numerator = 1001;
472 		fi->interval.denominator = 30000;
473 	} else {
474 		fi->interval.numerator = 1;
475 		fi->interval.denominator = 25;
476 	}
477 
478 	return 0;
479 }
480 
adv7180_set_power_pin(struct adv7180_state * state,bool on)481 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
482 {
483 	if (!state->pwdn_gpio)
484 		return;
485 
486 	if (on) {
487 		gpiod_set_value_cansleep(state->pwdn_gpio, 0);
488 		usleep_range(5000, 10000);
489 	} else {
490 		gpiod_set_value_cansleep(state->pwdn_gpio, 1);
491 	}
492 }
493 
adv7180_set_reset_pin(struct adv7180_state * state,bool on)494 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
495 {
496 	if (!state->rst_gpio)
497 		return;
498 
499 	if (on) {
500 		gpiod_set_value_cansleep(state->rst_gpio, 1);
501 	} else {
502 		gpiod_set_value_cansleep(state->rst_gpio, 0);
503 		usleep_range(5000, 10000);
504 	}
505 }
506 
adv7180_set_power(struct adv7180_state * state,bool on)507 static int adv7180_set_power(struct adv7180_state *state, bool on)
508 {
509 	u8 val;
510 	int ret;
511 
512 	if (on)
513 		val = ADV7180_PWR_MAN_ON;
514 	else
515 		val = ADV7180_PWR_MAN_OFF;
516 
517 	ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
518 	if (ret)
519 		return ret;
520 
521 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
522 		if (on) {
523 			adv7180_csi_write(state, 0xDE, 0x02);
524 			adv7180_csi_write(state, 0xD2, 0xF7);
525 			adv7180_csi_write(state, 0xD8, 0x65);
526 			adv7180_csi_write(state, 0xE0, 0x09);
527 			adv7180_csi_write(state, 0x2C, 0x00);
528 			if (state->field == V4L2_FIELD_NONE)
529 				adv7180_csi_write(state, 0x1D, 0x80);
530 			adv7180_csi_write(state, 0x00, 0x00);
531 		} else {
532 			adv7180_csi_write(state, 0x00, 0x80);
533 		}
534 	}
535 
536 	return 0;
537 }
538 
adv7180_s_power(struct v4l2_subdev * sd,int on)539 static int adv7180_s_power(struct v4l2_subdev *sd, int on)
540 {
541 	struct adv7180_state *state = to_state(sd);
542 	int ret;
543 
544 	ret = mutex_lock_interruptible(&state->mutex);
545 	if (ret)
546 		return ret;
547 
548 	ret = adv7180_set_power(state, on);
549 	if (ret == 0)
550 		state->powered = on;
551 
552 	mutex_unlock(&state->mutex);
553 	return ret;
554 }
555 
556 static const char * const test_pattern_menu[] = {
557 	"Single color",
558 	"Color bars",
559 	"Luma ramp",
560 	"Boundary box",
561 	"Disable",
562 };
563 
adv7180_test_pattern(struct adv7180_state * state,int value)564 static int adv7180_test_pattern(struct adv7180_state *state, int value)
565 {
566 	unsigned int reg = 0;
567 
568 	/* Map menu value into register value */
569 	if (value < 3)
570 		reg = value;
571 	if (value == 3)
572 		reg = 5;
573 
574 	adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
575 
576 	if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
577 		reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
578 		reg &= ~ADV7180_DEF_VAL_EN;
579 		adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
580 		return 0;
581 	}
582 
583 	reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
584 	reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
585 	adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
586 
587 	return 0;
588 }
589 
adv7180_s_ctrl(struct v4l2_ctrl * ctrl)590 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
591 {
592 	struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
593 	struct adv7180_state *state = to_state(sd);
594 	int ret = mutex_lock_interruptible(&state->mutex);
595 	int val;
596 
597 	if (ret)
598 		return ret;
599 	val = ctrl->val;
600 	switch (ctrl->id) {
601 	case V4L2_CID_BRIGHTNESS:
602 		ret = adv7180_write(state, ADV7180_REG_BRI, val);
603 		break;
604 	case V4L2_CID_HUE:
605 		/*Hue is inverted according to HSL chart */
606 		ret = adv7180_write(state, ADV7180_REG_HUE, -val);
607 		break;
608 	case V4L2_CID_CONTRAST:
609 		ret = adv7180_write(state, ADV7180_REG_CON, val);
610 		break;
611 	case V4L2_CID_SATURATION:
612 		/*
613 		 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
614 		 *Let's not confuse the user, everybody understands saturation
615 		 */
616 		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
617 		if (ret < 0)
618 			break;
619 		ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
620 		break;
621 	case V4L2_CID_ADV_FAST_SWITCH:
622 		if (ctrl->val) {
623 			/* ADI required write */
624 			adv7180_write(state, 0x80d9, 0x44);
625 			adv7180_write(state, ADV7180_REG_FLCONTROL,
626 				ADV7180_FLCONTROL_FL_ENABLE);
627 		} else {
628 			/* ADI required write */
629 			adv7180_write(state, 0x80d9, 0xc4);
630 			adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
631 		}
632 		break;
633 	case V4L2_CID_TEST_PATTERN:
634 		ret = adv7180_test_pattern(state, val);
635 		break;
636 	default:
637 		ret = -EINVAL;
638 	}
639 
640 	mutex_unlock(&state->mutex);
641 	return ret;
642 }
643 
644 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
645 	.s_ctrl = adv7180_s_ctrl,
646 };
647 
648 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
649 	.ops = &adv7180_ctrl_ops,
650 	.id = V4L2_CID_ADV_FAST_SWITCH,
651 	.name = "Fast Switching",
652 	.type = V4L2_CTRL_TYPE_BOOLEAN,
653 	.min = 0,
654 	.max = 1,
655 	.step = 1,
656 };
657 
adv7180_init_controls(struct adv7180_state * state)658 static int adv7180_init_controls(struct adv7180_state *state)
659 {
660 	v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
661 
662 	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
663 			  V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
664 			  ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
665 	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
666 			  V4L2_CID_CONTRAST, ADV7180_CON_MIN,
667 			  ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
668 	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
669 			  V4L2_CID_SATURATION, ADV7180_SAT_MIN,
670 			  ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
671 	v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
672 			  V4L2_CID_HUE, ADV7180_HUE_MIN,
673 			  ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
674 	v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
675 
676 	v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops,
677 				      V4L2_CID_TEST_PATTERN,
678 				      ARRAY_SIZE(test_pattern_menu) - 1,
679 				      0, ARRAY_SIZE(test_pattern_menu) - 1,
680 				      test_pattern_menu);
681 
682 	state->sd.ctrl_handler = &state->ctrl_hdl;
683 	if (state->ctrl_hdl.error) {
684 		int err = state->ctrl_hdl.error;
685 
686 		v4l2_ctrl_handler_free(&state->ctrl_hdl);
687 		return err;
688 	}
689 	v4l2_ctrl_handler_setup(&state->ctrl_hdl);
690 
691 	return 0;
692 }
adv7180_exit_controls(struct adv7180_state * state)693 static void adv7180_exit_controls(struct adv7180_state *state)
694 {
695 	v4l2_ctrl_handler_free(&state->ctrl_hdl);
696 }
697 
adv7180_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)698 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
699 				  struct v4l2_subdev_state *sd_state,
700 				  struct v4l2_subdev_mbus_code_enum *code)
701 {
702 	if (code->index != 0)
703 		return -EINVAL;
704 
705 	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
706 
707 	return 0;
708 }
709 
adv7180_mbus_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt)710 static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
711 			    struct v4l2_mbus_framefmt *fmt)
712 {
713 	struct adv7180_state *state = to_state(sd);
714 
715 	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
716 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
717 	fmt->width = 720;
718 	fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
719 
720 	if (state->field == V4L2_FIELD_ALTERNATE)
721 		fmt->height /= 2;
722 
723 	return 0;
724 }
725 
adv7180_set_field_mode(struct adv7180_state * state)726 static int adv7180_set_field_mode(struct adv7180_state *state)
727 {
728 	if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
729 		return 0;
730 
731 	if (state->field == V4L2_FIELD_NONE) {
732 		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
733 			adv7180_csi_write(state, 0x01, 0x20);
734 			adv7180_csi_write(state, 0x02, 0x28);
735 			adv7180_csi_write(state, 0x03, 0x38);
736 			adv7180_csi_write(state, 0x04, 0x30);
737 			adv7180_csi_write(state, 0x05, 0x30);
738 			adv7180_csi_write(state, 0x06, 0x80);
739 			adv7180_csi_write(state, 0x07, 0x70);
740 			adv7180_csi_write(state, 0x08, 0x50);
741 		}
742 		adv7180_vpp_write(state, 0xa3, 0x00);
743 		adv7180_vpp_write(state, 0x5b, 0x00);
744 		adv7180_vpp_write(state, 0x55, 0x80);
745 	} else {
746 		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
747 			adv7180_csi_write(state, 0x01, 0x18);
748 			adv7180_csi_write(state, 0x02, 0x18);
749 			adv7180_csi_write(state, 0x03, 0x30);
750 			adv7180_csi_write(state, 0x04, 0x20);
751 			adv7180_csi_write(state, 0x05, 0x28);
752 			adv7180_csi_write(state, 0x06, 0x40);
753 			adv7180_csi_write(state, 0x07, 0x58);
754 			adv7180_csi_write(state, 0x08, 0x30);
755 		}
756 		adv7180_vpp_write(state, 0xa3, 0x70);
757 		adv7180_vpp_write(state, 0x5b, 0x80);
758 		adv7180_vpp_write(state, 0x55, 0x00);
759 	}
760 
761 	return 0;
762 }
763 
adv7180_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)764 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
765 				  struct v4l2_subdev_state *sd_state,
766 				  struct v4l2_subdev_format *format)
767 {
768 	struct adv7180_state *state = to_state(sd);
769 
770 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
771 		format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
772 	} else {
773 		adv7180_mbus_fmt(sd, &format->format);
774 		format->format.field = state->field;
775 	}
776 
777 	return 0;
778 }
779 
adv7180_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)780 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
781 				  struct v4l2_subdev_state *sd_state,
782 				  struct v4l2_subdev_format *format)
783 {
784 	struct adv7180_state *state = to_state(sd);
785 	struct v4l2_mbus_framefmt *framefmt;
786 	int ret;
787 
788 	switch (format->format.field) {
789 	case V4L2_FIELD_NONE:
790 		if (state->chip_info->flags & ADV7180_FLAG_I2P)
791 			break;
792 		fallthrough;
793 	default:
794 		format->format.field = V4L2_FIELD_ALTERNATE;
795 		break;
796 	}
797 
798 	ret = adv7180_mbus_fmt(sd,  &format->format);
799 
800 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
801 		if (state->field != format->format.field) {
802 			state->field = format->format.field;
803 			adv7180_set_power(state, false);
804 			adv7180_set_field_mode(state);
805 			adv7180_set_power(state, true);
806 		}
807 	} else {
808 		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
809 		*framefmt = format->format;
810 	}
811 
812 	return ret;
813 }
814 
adv7180_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)815 static int adv7180_init_cfg(struct v4l2_subdev *sd,
816 			    struct v4l2_subdev_state *sd_state)
817 {
818 	struct v4l2_subdev_format fmt = {
819 		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
820 		: V4L2_SUBDEV_FORMAT_ACTIVE,
821 	};
822 
823 	return adv7180_set_pad_format(sd, sd_state, &fmt);
824 }
825 
adv7180_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)826 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
827 				   unsigned int pad,
828 				   struct v4l2_mbus_config *cfg)
829 {
830 	struct adv7180_state *state = to_state(sd);
831 
832 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
833 		cfg->type = V4L2_MBUS_CSI2_DPHY;
834 		cfg->bus.mipi_csi2.num_data_lanes = 1;
835 		cfg->bus.mipi_csi2.flags = 0;
836 	} else {
837 		/*
838 		 * The ADV7180 sensor supports BT.601/656 output modes.
839 		 * The BT.656 is default and not yet configurable by s/w.
840 		 */
841 		cfg->bus.parallel.flags = V4L2_MBUS_MASTER |
842 					  V4L2_MBUS_PCLK_SAMPLE_RISING |
843 					  V4L2_MBUS_DATA_ACTIVE_HIGH;
844 		cfg->type = V4L2_MBUS_BT656;
845 	}
846 
847 	return 0;
848 }
849 
adv7180_get_skip_frames(struct v4l2_subdev * sd,u32 * frames)850 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
851 {
852 	*frames = ADV7180_NUM_OF_SKIP_FRAMES;
853 
854 	return 0;
855 }
856 
adv7180_g_pixelaspect(struct v4l2_subdev * sd,struct v4l2_fract * aspect)857 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)
858 {
859 	struct adv7180_state *state = to_state(sd);
860 
861 	if (state->curr_norm & V4L2_STD_525_60) {
862 		aspect->numerator = 11;
863 		aspect->denominator = 10;
864 	} else {
865 		aspect->numerator = 54;
866 		aspect->denominator = 59;
867 	}
868 
869 	return 0;
870 }
871 
adv7180_g_tvnorms(struct v4l2_subdev * sd,v4l2_std_id * norm)872 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
873 {
874 	*norm = V4L2_STD_ALL;
875 	return 0;
876 }
877 
adv7180_s_stream(struct v4l2_subdev * sd,int enable)878 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
879 {
880 	struct adv7180_state *state = to_state(sd);
881 	int ret;
882 
883 	/* It's always safe to stop streaming, no need to take the lock */
884 	if (!enable) {
885 		state->streaming = enable;
886 		return 0;
887 	}
888 
889 	/* Must wait until querystd released the lock */
890 	ret = mutex_lock_interruptible(&state->mutex);
891 	if (ret)
892 		return ret;
893 	state->streaming = enable;
894 	mutex_unlock(&state->mutex);
895 	return 0;
896 }
897 
adv7180_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)898 static int adv7180_subscribe_event(struct v4l2_subdev *sd,
899 				   struct v4l2_fh *fh,
900 				   struct v4l2_event_subscription *sub)
901 {
902 	switch (sub->type) {
903 	case V4L2_EVENT_SOURCE_CHANGE:
904 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
905 	case V4L2_EVENT_CTRL:
906 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
907 	default:
908 		return -EINVAL;
909 	}
910 }
911 
912 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
913 	.s_std = adv7180_s_std,
914 	.g_std = adv7180_g_std,
915 	.g_frame_interval = adv7180_g_frame_interval,
916 	.querystd = adv7180_querystd,
917 	.g_input_status = adv7180_g_input_status,
918 	.s_routing = adv7180_s_routing,
919 	.g_pixelaspect = adv7180_g_pixelaspect,
920 	.g_tvnorms = adv7180_g_tvnorms,
921 	.s_stream = adv7180_s_stream,
922 };
923 
924 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
925 	.s_power = adv7180_s_power,
926 	.subscribe_event = adv7180_subscribe_event,
927 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
928 };
929 
930 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
931 	.init_cfg = adv7180_init_cfg,
932 	.enum_mbus_code = adv7180_enum_mbus_code,
933 	.set_fmt = adv7180_set_pad_format,
934 	.get_fmt = adv7180_get_pad_format,
935 	.get_mbus_config = adv7180_get_mbus_config,
936 };
937 
938 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
939 	.g_skip_frames = adv7180_get_skip_frames,
940 };
941 
942 static const struct v4l2_subdev_ops adv7180_ops = {
943 	.core = &adv7180_core_ops,
944 	.video = &adv7180_video_ops,
945 	.pad = &adv7180_pad_ops,
946 	.sensor = &adv7180_sensor_ops,
947 };
948 
adv7180_irq(int irq,void * devid)949 static irqreturn_t adv7180_irq(int irq, void *devid)
950 {
951 	struct adv7180_state *state = devid;
952 	u8 isr3;
953 
954 	mutex_lock(&state->mutex);
955 	isr3 = adv7180_read(state, ADV7180_REG_ISR3);
956 	/* clear */
957 	adv7180_write(state, ADV7180_REG_ICR3, isr3);
958 
959 	if (isr3 & ADV7180_IRQ3_AD_CHANGE) {
960 		static const struct v4l2_event src_ch = {
961 			.type = V4L2_EVENT_SOURCE_CHANGE,
962 			.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
963 		};
964 
965 		v4l2_subdev_notify_event(&state->sd, &src_ch);
966 	}
967 	mutex_unlock(&state->mutex);
968 
969 	return IRQ_HANDLED;
970 }
971 
adv7180_init(struct adv7180_state * state)972 static int adv7180_init(struct adv7180_state *state)
973 {
974 	int ret;
975 
976 	/* ITU-R BT.656-4 compatible */
977 	ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
978 			ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
979 	if (ret < 0)
980 		return ret;
981 
982 	/* Manually set V bit end position in NTSC mode */
983 	return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
984 					ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
985 }
986 
adv7180_set_std(struct adv7180_state * state,unsigned int std)987 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
988 {
989 	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
990 		(std << 4) | state->input);
991 }
992 
adv7180_select_input(struct adv7180_state * state,unsigned int input)993 static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
994 {
995 	int ret;
996 
997 	ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
998 	if (ret < 0)
999 		return ret;
1000 
1001 	ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
1002 	ret |= input;
1003 	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1004 }
1005 
adv7182_init(struct adv7180_state * state)1006 static int adv7182_init(struct adv7180_state *state)
1007 {
1008 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
1009 		adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1010 			ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
1011 
1012 	if (state->chip_info->flags & ADV7180_FLAG_I2P)
1013 		adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1014 			ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
1015 
1016 	if (state->chip_info->flags & ADV7180_FLAG_V2) {
1017 		/* ADI recommended writes for improved video quality */
1018 		adv7180_write(state, 0x0080, 0x51);
1019 		adv7180_write(state, 0x0081, 0x51);
1020 		adv7180_write(state, 0x0082, 0x68);
1021 	}
1022 
1023 	/* ADI required writes */
1024 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1025 		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1026 		adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1027 		adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1028 	} else {
1029 		if (state->chip_info->flags & ADV7180_FLAG_V2) {
1030 			if (state->force_bt656_4) {
1031 				/* ITU-R BT.656-4 compatible */
1032 				adv7180_write(state,
1033 					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1034 					      ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
1035 				/* Manually set NEWAVMODE */
1036 				adv7180_write(state,
1037 					      ADV7180_REG_VSYNC_FIELD_CTL_1,
1038 					      ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
1039 				/* Manually set V bit end position in NTSC mode */
1040 				adv7180_write(state,
1041 					      ADV7180_REG_NTSC_V_BIT_END,
1042 					      ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
1043 			} else {
1044 				adv7180_write(state,
1045 					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1046 					      0x17);
1047 			}
1048 		}
1049 		else
1050 			adv7180_write(state,
1051 				      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
1052 				      0x07);
1053 		adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1054 		adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1055 	}
1056 
1057 	adv7180_write(state, 0x0013, 0x00);
1058 
1059 	return 0;
1060 }
1061 
adv7182_set_std(struct adv7180_state * state,unsigned int std)1062 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
1063 {
1064 	/* Failing to set the reserved bit can result in increased video noise */
1065 	return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1066 			     (std << 4) | ADV7182_REG_INPUT_RESERVED);
1067 }
1068 
1069 enum adv7182_input_type {
1070 	ADV7182_INPUT_TYPE_CVBS,
1071 	ADV7182_INPUT_TYPE_DIFF_CVBS,
1072 	ADV7182_INPUT_TYPE_SVIDEO,
1073 	ADV7182_INPUT_TYPE_YPBPR,
1074 };
1075 
adv7182_get_input_type(unsigned int input)1076 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
1077 {
1078 	switch (input) {
1079 	case ADV7182_INPUT_CVBS_AIN1:
1080 	case ADV7182_INPUT_CVBS_AIN2:
1081 	case ADV7182_INPUT_CVBS_AIN3:
1082 	case ADV7182_INPUT_CVBS_AIN4:
1083 	case ADV7182_INPUT_CVBS_AIN5:
1084 	case ADV7182_INPUT_CVBS_AIN6:
1085 	case ADV7182_INPUT_CVBS_AIN7:
1086 	case ADV7182_INPUT_CVBS_AIN8:
1087 		return ADV7182_INPUT_TYPE_CVBS;
1088 	case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
1089 	case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
1090 	case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
1091 	case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
1092 		return ADV7182_INPUT_TYPE_SVIDEO;
1093 	case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
1094 	case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
1095 		return ADV7182_INPUT_TYPE_YPBPR;
1096 	case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
1097 	case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
1098 	case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
1099 	case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
1100 		return ADV7182_INPUT_TYPE_DIFF_CVBS;
1101 	default: /* Will never happen */
1102 		return 0;
1103 	}
1104 }
1105 
1106 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
1107 static unsigned int adv7182_lbias_settings[][3] = {
1108 	[ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
1109 	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1110 	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1111 	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1112 };
1113 
1114 static unsigned int adv7280_lbias_settings[][3] = {
1115 	[ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
1116 	[ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
1117 	[ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
1118 	[ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
1119 };
1120 
adv7182_select_input(struct adv7180_state * state,unsigned int input)1121 static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
1122 {
1123 	enum adv7182_input_type input_type;
1124 	unsigned int *lbias;
1125 	unsigned int i;
1126 	int ret;
1127 
1128 	ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1129 	if (ret)
1130 		return ret;
1131 
1132 	/* Reset clamp circuitry - ADI recommended writes */
1133 	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1134 	adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1135 
1136 	input_type = adv7182_get_input_type(input);
1137 
1138 	switch (input_type) {
1139 	case ADV7182_INPUT_TYPE_CVBS:
1140 	case ADV7182_INPUT_TYPE_DIFF_CVBS:
1141 		/* ADI recommends to use the SH1 filter */
1142 		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1143 		break;
1144 	default:
1145 		adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1146 		break;
1147 	}
1148 
1149 	if (state->chip_info->flags & ADV7180_FLAG_V2)
1150 		lbias = adv7280_lbias_settings[input_type];
1151 	else
1152 		lbias = adv7182_lbias_settings[input_type];
1153 
1154 	for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
1155 		adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1156 
1157 	if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
1158 		/* ADI required writes to make differential CVBS work */
1159 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1160 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1161 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1162 		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1163 		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1164 	} else {
1165 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1166 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1167 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1168 		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1169 		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1170 	}
1171 
1172 	return 0;
1173 }
1174 
1175 static const struct adv7180_chip_info adv7180_info = {
1176 	.flags = ADV7180_FLAG_RESET_POWERED,
1177 	/* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
1178 	 * all inputs and let the card driver take care of validation
1179 	 */
1180 	.valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
1181 		BIT(ADV7180_INPUT_CVBS_AIN2) |
1182 		BIT(ADV7180_INPUT_CVBS_AIN3) |
1183 		BIT(ADV7180_INPUT_CVBS_AIN4) |
1184 		BIT(ADV7180_INPUT_CVBS_AIN5) |
1185 		BIT(ADV7180_INPUT_CVBS_AIN6) |
1186 		BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
1187 		BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
1188 		BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
1189 		BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1190 		BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
1191 	.init = adv7180_init,
1192 	.set_std = adv7180_set_std,
1193 	.select_input = adv7180_select_input,
1194 };
1195 
1196 static const struct adv7180_chip_info adv7182_info = {
1197 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1198 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1199 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1200 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1201 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1202 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1203 		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1204 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1205 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
1206 	.init = adv7182_init,
1207 	.set_std = adv7182_set_std,
1208 	.select_input = adv7182_select_input,
1209 };
1210 
1211 static const struct adv7180_chip_info adv7280_info = {
1212 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1213 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1214 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1215 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1216 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1217 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1218 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1219 		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
1220 	.init = adv7182_init,
1221 	.set_std = adv7182_set_std,
1222 	.select_input = adv7182_select_input,
1223 };
1224 
1225 static const struct adv7180_chip_info adv7280_m_info = {
1226 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1227 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1228 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1229 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1230 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1231 		BIT(ADV7182_INPUT_CVBS_AIN5) |
1232 		BIT(ADV7182_INPUT_CVBS_AIN6) |
1233 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1234 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1235 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1236 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1237 		BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1238 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1239 		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1240 		BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
1241 	.init = adv7182_init,
1242 	.set_std = adv7182_set_std,
1243 	.select_input = adv7182_select_input,
1244 };
1245 
1246 static const struct adv7180_chip_info adv7281_info = {
1247 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1248 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1249 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1250 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1251 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1252 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1253 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1254 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1255 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1256 	.init = adv7182_init,
1257 	.set_std = adv7182_set_std,
1258 	.select_input = adv7182_select_input,
1259 };
1260 
1261 static const struct adv7180_chip_info adv7281_m_info = {
1262 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1263 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1264 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1265 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1266 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1267 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1268 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1269 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1270 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1271 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1272 		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1273 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1274 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1275 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1276 	.init = adv7182_init,
1277 	.set_std = adv7182_set_std,
1278 	.select_input = adv7182_select_input,
1279 };
1280 
1281 static const struct adv7180_chip_info adv7281_ma_info = {
1282 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
1283 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1284 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1285 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1286 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1287 		BIT(ADV7182_INPUT_CVBS_AIN5) |
1288 		BIT(ADV7182_INPUT_CVBS_AIN6) |
1289 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1290 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1291 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1292 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1293 		BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
1294 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1295 		BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
1296 		BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
1297 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1298 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1299 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
1300 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1301 	.init = adv7182_init,
1302 	.set_std = adv7182_set_std,
1303 	.select_input = adv7182_select_input,
1304 };
1305 
1306 static const struct adv7180_chip_info adv7282_info = {
1307 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
1308 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1309 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1310 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1311 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1312 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1313 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1314 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1315 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1316 	.init = adv7182_init,
1317 	.set_std = adv7182_set_std,
1318 	.select_input = adv7182_select_input,
1319 };
1320 
1321 static const struct adv7180_chip_info adv7282_m_info = {
1322 	.flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
1323 	.valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
1324 		BIT(ADV7182_INPUT_CVBS_AIN2) |
1325 		BIT(ADV7182_INPUT_CVBS_AIN3) |
1326 		BIT(ADV7182_INPUT_CVBS_AIN4) |
1327 		BIT(ADV7182_INPUT_CVBS_AIN7) |
1328 		BIT(ADV7182_INPUT_CVBS_AIN8) |
1329 		BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
1330 		BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
1331 		BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
1332 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
1333 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
1334 		BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
1335 	.init = adv7182_init,
1336 	.set_std = adv7182_set_std,
1337 	.select_input = adv7182_select_input,
1338 };
1339 
init_device(struct adv7180_state * state)1340 static int init_device(struct adv7180_state *state)
1341 {
1342 	int ret;
1343 
1344 	mutex_lock(&state->mutex);
1345 
1346 	adv7180_set_power_pin(state, true);
1347 	adv7180_set_reset_pin(state, false);
1348 
1349 	adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1350 	usleep_range(5000, 10000);
1351 
1352 	ret = state->chip_info->init(state);
1353 	if (ret)
1354 		goto out_unlock;
1355 
1356 	ret = adv7180_program_std(state);
1357 	if (ret)
1358 		goto out_unlock;
1359 
1360 	adv7180_set_field_mode(state);
1361 
1362 	/* register for interrupts */
1363 	if (state->irq > 0) {
1364 		/* config the Interrupt pin to be active low */
1365 		ret = adv7180_write(state, ADV7180_REG_ICONF1,
1366 						ADV7180_ICONF1_ACTIVE_LOW |
1367 						ADV7180_ICONF1_PSYNC_ONLY);
1368 		if (ret < 0)
1369 			goto out_unlock;
1370 
1371 		ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1372 		if (ret < 0)
1373 			goto out_unlock;
1374 
1375 		ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1376 		if (ret < 0)
1377 			goto out_unlock;
1378 
1379 		/* enable AD change interrupts interrupts */
1380 		ret = adv7180_write(state, ADV7180_REG_IMR3,
1381 						ADV7180_IRQ3_AD_CHANGE);
1382 		if (ret < 0)
1383 			goto out_unlock;
1384 
1385 		ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
1386 		if (ret < 0)
1387 			goto out_unlock;
1388 	}
1389 
1390 out_unlock:
1391 	mutex_unlock(&state->mutex);
1392 
1393 	return ret;
1394 }
1395 
adv7180_probe(struct i2c_client * client)1396 static int adv7180_probe(struct i2c_client *client)
1397 {
1398 	const struct i2c_device_id *id = i2c_client_get_device_id(client);
1399 	struct device_node *np = client->dev.of_node;
1400 	struct adv7180_state *state;
1401 	struct v4l2_subdev *sd;
1402 	int ret;
1403 
1404 	/* Check if the adapter supports the needed features */
1405 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1406 		return -EIO;
1407 
1408 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1409 	if (state == NULL)
1410 		return -ENOMEM;
1411 
1412 	state->client = client;
1413 	state->field = V4L2_FIELD_ALTERNATE;
1414 	state->chip_info = (struct adv7180_chip_info *)id->driver_data;
1415 
1416 	state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1417 						   GPIOD_OUT_HIGH);
1418 	if (IS_ERR(state->pwdn_gpio)) {
1419 		ret = PTR_ERR(state->pwdn_gpio);
1420 		v4l_err(client, "request for power pin failed: %d\n", ret);
1421 		return ret;
1422 	}
1423 
1424 	state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1425 						  GPIOD_OUT_HIGH);
1426 	if (IS_ERR(state->rst_gpio)) {
1427 		ret = PTR_ERR(state->rst_gpio);
1428 		v4l_err(client, "request for reset pin failed: %d\n", ret);
1429 		return ret;
1430 	}
1431 
1432 	if (of_property_read_bool(np, "adv,force-bt656-4"))
1433 		state->force_bt656_4 = true;
1434 
1435 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
1436 		state->csi_client = i2c_new_dummy_device(client->adapter,
1437 				ADV7180_DEFAULT_CSI_I2C_ADDR);
1438 		if (IS_ERR(state->csi_client))
1439 			return PTR_ERR(state->csi_client);
1440 	}
1441 
1442 	if (state->chip_info->flags & ADV7180_FLAG_I2P) {
1443 		state->vpp_client = i2c_new_dummy_device(client->adapter,
1444 				ADV7180_DEFAULT_VPP_I2C_ADDR);
1445 		if (IS_ERR(state->vpp_client)) {
1446 			ret = PTR_ERR(state->vpp_client);
1447 			goto err_unregister_csi_client;
1448 		}
1449 	}
1450 
1451 	state->irq = client->irq;
1452 	mutex_init(&state->mutex);
1453 	state->curr_norm = V4L2_STD_NTSC;
1454 	if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
1455 		state->powered = true;
1456 	else
1457 		state->powered = false;
1458 	state->input = 0;
1459 	sd = &state->sd;
1460 	v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
1461 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1462 
1463 	ret = adv7180_init_controls(state);
1464 	if (ret)
1465 		goto err_unregister_vpp_client;
1466 
1467 	state->pad.flags = MEDIA_PAD_FL_SOURCE;
1468 	sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1469 	ret = media_entity_pads_init(&sd->entity, 1, &state->pad);
1470 	if (ret)
1471 		goto err_free_ctrl;
1472 
1473 	ret = init_device(state);
1474 	if (ret)
1475 		goto err_media_entity_cleanup;
1476 
1477 	if (state->irq) {
1478 		ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
1479 					   IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
1480 					   KBUILD_MODNAME, state);
1481 		if (ret)
1482 			goto err_media_entity_cleanup;
1483 	}
1484 
1485 	ret = v4l2_async_register_subdev(sd);
1486 	if (ret)
1487 		goto err_free_irq;
1488 
1489 	mutex_lock(&state->mutex);
1490 	ret = adv7180_read(state, ADV7180_REG_IDENT);
1491 	mutex_unlock(&state->mutex);
1492 	if (ret < 0)
1493 		goto err_v4l2_async_unregister;
1494 
1495 	v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
1496 		 ret, client->addr, client->adapter->name);
1497 
1498 	return 0;
1499 
1500 err_v4l2_async_unregister:
1501 	v4l2_async_unregister_subdev(sd);
1502 err_free_irq:
1503 	if (state->irq > 0)
1504 		free_irq(client->irq, state);
1505 err_media_entity_cleanup:
1506 	media_entity_cleanup(&sd->entity);
1507 err_free_ctrl:
1508 	adv7180_exit_controls(state);
1509 err_unregister_vpp_client:
1510 	i2c_unregister_device(state->vpp_client);
1511 err_unregister_csi_client:
1512 	i2c_unregister_device(state->csi_client);
1513 	mutex_destroy(&state->mutex);
1514 	return ret;
1515 }
1516 
adv7180_remove(struct i2c_client * client)1517 static void adv7180_remove(struct i2c_client *client)
1518 {
1519 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1520 	struct adv7180_state *state = to_state(sd);
1521 
1522 	v4l2_async_unregister_subdev(sd);
1523 
1524 	if (state->irq > 0)
1525 		free_irq(client->irq, state);
1526 
1527 	media_entity_cleanup(&sd->entity);
1528 	adv7180_exit_controls(state);
1529 
1530 	i2c_unregister_device(state->vpp_client);
1531 	i2c_unregister_device(state->csi_client);
1532 
1533 	adv7180_set_reset_pin(state, true);
1534 	adv7180_set_power_pin(state, false);
1535 
1536 	mutex_destroy(&state->mutex);
1537 }
1538 
1539 static const struct i2c_device_id adv7180_id[] = {
1540 	{ "adv7180", (kernel_ulong_t)&adv7180_info },
1541 	{ "adv7180cp", (kernel_ulong_t)&adv7180_info },
1542 	{ "adv7180st", (kernel_ulong_t)&adv7180_info },
1543 	{ "adv7182", (kernel_ulong_t)&adv7182_info },
1544 	{ "adv7280", (kernel_ulong_t)&adv7280_info },
1545 	{ "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
1546 	{ "adv7281", (kernel_ulong_t)&adv7281_info },
1547 	{ "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
1548 	{ "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
1549 	{ "adv7282", (kernel_ulong_t)&adv7282_info },
1550 	{ "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
1551 	{},
1552 };
1553 MODULE_DEVICE_TABLE(i2c, adv7180_id);
1554 
1555 #ifdef CONFIG_PM_SLEEP
adv7180_suspend(struct device * dev)1556 static int adv7180_suspend(struct device *dev)
1557 {
1558 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1559 	struct adv7180_state *state = to_state(sd);
1560 
1561 	return adv7180_set_power(state, false);
1562 }
1563 
adv7180_resume(struct device * dev)1564 static int adv7180_resume(struct device *dev)
1565 {
1566 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1567 	struct adv7180_state *state = to_state(sd);
1568 	int ret;
1569 
1570 	ret = init_device(state);
1571 	if (ret < 0)
1572 		return ret;
1573 
1574 	ret = adv7180_set_power(state, state->powered);
1575 	if (ret)
1576 		return ret;
1577 
1578 	return 0;
1579 }
1580 
1581 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
1582 #define ADV7180_PM_OPS (&adv7180_pm_ops)
1583 
1584 #else
1585 #define ADV7180_PM_OPS NULL
1586 #endif
1587 
1588 #ifdef CONFIG_OF
1589 static const struct of_device_id adv7180_of_id[] = {
1590 	{ .compatible = "adi,adv7180", },
1591 	{ .compatible = "adi,adv7180cp", },
1592 	{ .compatible = "adi,adv7180st", },
1593 	{ .compatible = "adi,adv7182", },
1594 	{ .compatible = "adi,adv7280", },
1595 	{ .compatible = "adi,adv7280-m", },
1596 	{ .compatible = "adi,adv7281", },
1597 	{ .compatible = "adi,adv7281-m", },
1598 	{ .compatible = "adi,adv7281-ma", },
1599 	{ .compatible = "adi,adv7282", },
1600 	{ .compatible = "adi,adv7282-m", },
1601 	{ },
1602 };
1603 
1604 MODULE_DEVICE_TABLE(of, adv7180_of_id);
1605 #endif
1606 
1607 static struct i2c_driver adv7180_driver = {
1608 	.driver = {
1609 		   .name = KBUILD_MODNAME,
1610 		   .pm = ADV7180_PM_OPS,
1611 		   .of_match_table = of_match_ptr(adv7180_of_id),
1612 		   },
1613 	.probe = adv7180_probe,
1614 	.remove = adv7180_remove,
1615 	.id_table = adv7180_id,
1616 };
1617 
1618 module_i2c_driver(adv7180_driver);
1619 
1620 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
1621 MODULE_AUTHOR("Mocean Laboratories");
1622 MODULE_LICENSE("GPL v2");
1623