1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/slab.h> 15 #include <linux/of.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/videodev2.h> 18 #include <media/v4l2-ioctl.h> 19 #include <media/v4l2-event.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ctrls.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 29 #define ADV7180_STD_NTSC_J 0x4 30 #define ADV7180_STD_NTSC_M 0x5 31 #define ADV7180_STD_PAL60 0x6 32 #define ADV7180_STD_NTSC_443 0x7 33 #define ADV7180_STD_PAL_BG 0x8 34 #define ADV7180_STD_PAL_N 0x9 35 #define ADV7180_STD_PAL_M 0xa 36 #define ADV7180_STD_PAL_M_PED 0xb 37 #define ADV7180_STD_PAL_COMB_N 0xc 38 #define ADV7180_STD_PAL_COMB_N_PED 0xd 39 #define ADV7180_STD_PAL_SECAM 0xe 40 #define ADV7180_STD_PAL_SECAM_PED 0xf 41 42 #define ADV7180_REG_INPUT_CONTROL 0x0000 43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 44 45 #define ADV7182_REG_INPUT_VIDSEL 0x0002 46 47 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 48 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 49 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 50 51 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 52 #define ADV7180_AUTODETECT_DEFAULT 0x7f 53 /* Contrast */ 54 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 55 #define ADV7180_CON_MIN 0 56 #define ADV7180_CON_DEF 128 57 #define ADV7180_CON_MAX 255 58 /* Brightness*/ 59 #define ADV7180_REG_BRI 0x000a /*Signed */ 60 #define ADV7180_BRI_MIN -128 61 #define ADV7180_BRI_DEF 0 62 #define ADV7180_BRI_MAX 127 63 /* Hue */ 64 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 65 #define ADV7180_HUE_MIN -127 66 #define ADV7180_HUE_DEF 0 67 #define ADV7180_HUE_MAX 128 68 69 #define ADV7180_REG_CTRL 0x000e 70 #define ADV7180_CTRL_IRQ_SPACE 0x20 71 72 #define ADV7180_REG_PWR_MAN 0x0f 73 #define ADV7180_PWR_MAN_ON 0x04 74 #define ADV7180_PWR_MAN_OFF 0x24 75 #define ADV7180_PWR_MAN_RES 0x80 76 77 #define ADV7180_REG_STATUS1 0x0010 78 #define ADV7180_STATUS1_IN_LOCK 0x01 79 #define ADV7180_STATUS1_AUTOD_MASK 0x70 80 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 81 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 82 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 83 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 84 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 85 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 86 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 87 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 88 89 #define ADV7180_REG_IDENT 0x0011 90 #define ADV7180_ID_7180 0x18 91 92 #define ADV7180_REG_STATUS3 0x0013 93 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 94 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 95 #define ADV7180_REG_CTRL_2 0x001d 96 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 97 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 98 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 99 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 100 #define ADV7180_REG_LOCK_CNT 0x0051 101 #define ADV7180_REG_CVBS_TRIM 0x0052 102 #define ADV7180_REG_CLAMP_ADJ 0x005a 103 #define ADV7180_REG_RES_CIR 0x005f 104 #define ADV7180_REG_DIFF_MODE 0x0060 105 106 #define ADV7180_REG_ICONF1 0x2040 107 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 108 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 109 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 110 /* Saturation */ 111 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 112 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 113 #define ADV7180_SAT_MIN 0 114 #define ADV7180_SAT_DEF 128 115 #define ADV7180_SAT_MAX 255 116 117 #define ADV7180_IRQ1_LOCK 0x01 118 #define ADV7180_IRQ1_UNLOCK 0x02 119 #define ADV7180_REG_ISR1 0x2042 120 #define ADV7180_REG_ICR1 0x2043 121 #define ADV7180_REG_IMR1 0x2044 122 #define ADV7180_REG_IMR2 0x2048 123 #define ADV7180_IRQ3_AD_CHANGE 0x08 124 #define ADV7180_REG_ISR3 0x204A 125 #define ADV7180_REG_ICR3 0x204B 126 #define ADV7180_REG_IMR3 0x204C 127 #define ADV7180_REG_IMR4 0x2050 128 129 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 130 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 131 132 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 133 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 134 135 #define ADV7180_REG_ACE_CTRL1 0x4080 136 #define ADV7180_REG_ACE_CTRL5 0x4084 137 #define ADV7180_REG_FLCONTROL 0x40e0 138 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 139 140 #define ADV7180_REG_RST_CLAMP 0x809c 141 #define ADV7180_REG_AGC_ADJ1 0x80b6 142 #define ADV7180_REG_AGC_ADJ2 0x80c0 143 144 #define ADV7180_CSI_REG_PWRDN 0x00 145 #define ADV7180_CSI_PWRDN 0x80 146 147 #define ADV7180_INPUT_CVBS_AIN1 0x00 148 #define ADV7180_INPUT_CVBS_AIN2 0x01 149 #define ADV7180_INPUT_CVBS_AIN3 0x02 150 #define ADV7180_INPUT_CVBS_AIN4 0x03 151 #define ADV7180_INPUT_CVBS_AIN5 0x04 152 #define ADV7180_INPUT_CVBS_AIN6 0x05 153 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 154 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 155 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 156 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 157 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 158 159 #define ADV7182_INPUT_CVBS_AIN1 0x00 160 #define ADV7182_INPUT_CVBS_AIN2 0x01 161 #define ADV7182_INPUT_CVBS_AIN3 0x02 162 #define ADV7182_INPUT_CVBS_AIN4 0x03 163 #define ADV7182_INPUT_CVBS_AIN5 0x04 164 #define ADV7182_INPUT_CVBS_AIN6 0x05 165 #define ADV7182_INPUT_CVBS_AIN7 0x06 166 #define ADV7182_INPUT_CVBS_AIN8 0x07 167 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 168 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 169 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 170 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 171 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 172 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 173 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 174 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 175 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 176 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 177 178 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 179 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 180 181 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 182 183 /* Initial number of frames to skip to avoid possible garbage */ 184 #define ADV7180_NUM_OF_SKIP_FRAMES 2 185 186 struct adv7180_state; 187 188 #define ADV7180_FLAG_RESET_POWERED BIT(0) 189 #define ADV7180_FLAG_V2 BIT(1) 190 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 191 #define ADV7180_FLAG_I2P BIT(3) 192 193 struct adv7180_chip_info { 194 unsigned int flags; 195 unsigned int valid_input_mask; 196 int (*set_std)(struct adv7180_state *st, unsigned int std); 197 int (*select_input)(struct adv7180_state *st, unsigned int input); 198 int (*init)(struct adv7180_state *state); 199 }; 200 201 struct adv7180_state { 202 struct v4l2_ctrl_handler ctrl_hdl; 203 struct v4l2_subdev sd; 204 struct media_pad pad; 205 struct mutex mutex; /* mutual excl. when accessing chip */ 206 int irq; 207 struct gpio_desc *pwdn_gpio; 208 v4l2_std_id curr_norm; 209 bool powered; 210 bool streaming; 211 u8 input; 212 213 struct i2c_client *client; 214 unsigned int register_page; 215 struct i2c_client *csi_client; 216 struct i2c_client *vpp_client; 217 const struct adv7180_chip_info *chip_info; 218 enum v4l2_field field; 219 }; 220 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 221 struct adv7180_state, \ 222 ctrl_hdl)->sd) 223 224 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 225 { 226 if (state->register_page != page) { 227 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 228 page); 229 state->register_page = page; 230 } 231 232 return 0; 233 } 234 235 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 236 unsigned int value) 237 { 238 lockdep_assert_held(&state->mutex); 239 adv7180_select_page(state, reg >> 8); 240 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 241 } 242 243 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 244 { 245 lockdep_assert_held(&state->mutex); 246 adv7180_select_page(state, reg >> 8); 247 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 248 } 249 250 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 251 unsigned int value) 252 { 253 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 254 } 255 256 static int adv7180_set_video_standard(struct adv7180_state *state, 257 unsigned int std) 258 { 259 return state->chip_info->set_std(state, std); 260 } 261 262 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 263 unsigned int value) 264 { 265 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 266 } 267 268 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 269 { 270 /* in case V4L2_IN_ST_NO_SIGNAL */ 271 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 272 return V4L2_STD_UNKNOWN; 273 274 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 275 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 276 return V4L2_STD_NTSC; 277 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 278 return V4L2_STD_NTSC_443; 279 case ADV7180_STATUS1_AUTOD_PAL_M: 280 return V4L2_STD_PAL_M; 281 case ADV7180_STATUS1_AUTOD_PAL_60: 282 return V4L2_STD_PAL_60; 283 case ADV7180_STATUS1_AUTOD_PAL_B_G: 284 return V4L2_STD_PAL; 285 case ADV7180_STATUS1_AUTOD_SECAM: 286 return V4L2_STD_SECAM; 287 case ADV7180_STATUS1_AUTOD_PAL_COMB: 288 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 289 case ADV7180_STATUS1_AUTOD_SECAM_525: 290 return V4L2_STD_SECAM; 291 default: 292 return V4L2_STD_UNKNOWN; 293 } 294 } 295 296 static int v4l2_std_to_adv7180(v4l2_std_id std) 297 { 298 if (std == V4L2_STD_PAL_60) 299 return ADV7180_STD_PAL60; 300 if (std == V4L2_STD_NTSC_443) 301 return ADV7180_STD_NTSC_443; 302 if (std == V4L2_STD_PAL_N) 303 return ADV7180_STD_PAL_N; 304 if (std == V4L2_STD_PAL_M) 305 return ADV7180_STD_PAL_M; 306 if (std == V4L2_STD_PAL_Nc) 307 return ADV7180_STD_PAL_COMB_N; 308 309 if (std & V4L2_STD_PAL) 310 return ADV7180_STD_PAL_BG; 311 if (std & V4L2_STD_NTSC) 312 return ADV7180_STD_NTSC_M; 313 if (std & V4L2_STD_SECAM) 314 return ADV7180_STD_PAL_SECAM; 315 316 return -EINVAL; 317 } 318 319 static u32 adv7180_status_to_v4l2(u8 status1) 320 { 321 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 322 return V4L2_IN_ST_NO_SIGNAL; 323 324 return 0; 325 } 326 327 static int __adv7180_status(struct adv7180_state *state, u32 *status, 328 v4l2_std_id *std) 329 { 330 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 331 332 if (status1 < 0) 333 return status1; 334 335 if (status) 336 *status = adv7180_status_to_v4l2(status1); 337 if (std) 338 *std = adv7180_std_to_v4l2(status1); 339 340 return 0; 341 } 342 343 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 344 { 345 return container_of(sd, struct adv7180_state, sd); 346 } 347 348 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 349 { 350 struct adv7180_state *state = to_state(sd); 351 int err = mutex_lock_interruptible(&state->mutex); 352 if (err) 353 return err; 354 355 if (state->streaming) { 356 err = -EBUSY; 357 goto unlock; 358 } 359 360 err = adv7180_set_video_standard(state, 361 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 362 if (err) 363 goto unlock; 364 365 msleep(100); 366 __adv7180_status(state, NULL, std); 367 368 err = v4l2_std_to_adv7180(state->curr_norm); 369 if (err < 0) 370 goto unlock; 371 372 err = adv7180_set_video_standard(state, err); 373 374 unlock: 375 mutex_unlock(&state->mutex); 376 return err; 377 } 378 379 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 380 u32 output, u32 config) 381 { 382 struct adv7180_state *state = to_state(sd); 383 int ret = mutex_lock_interruptible(&state->mutex); 384 385 if (ret) 386 return ret; 387 388 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 389 ret = -EINVAL; 390 goto out; 391 } 392 393 ret = state->chip_info->select_input(state, input); 394 395 if (ret == 0) 396 state->input = input; 397 out: 398 mutex_unlock(&state->mutex); 399 return ret; 400 } 401 402 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 403 { 404 struct adv7180_state *state = to_state(sd); 405 int ret = mutex_lock_interruptible(&state->mutex); 406 if (ret) 407 return ret; 408 409 ret = __adv7180_status(state, status, NULL); 410 mutex_unlock(&state->mutex); 411 return ret; 412 } 413 414 static int adv7180_program_std(struct adv7180_state *state) 415 { 416 int ret; 417 418 ret = v4l2_std_to_adv7180(state->curr_norm); 419 if (ret < 0) 420 return ret; 421 422 ret = adv7180_set_video_standard(state, ret); 423 if (ret < 0) 424 return ret; 425 return 0; 426 } 427 428 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 429 { 430 struct adv7180_state *state = to_state(sd); 431 int ret = mutex_lock_interruptible(&state->mutex); 432 433 if (ret) 434 return ret; 435 436 /* Make sure we can support this std */ 437 ret = v4l2_std_to_adv7180(std); 438 if (ret < 0) 439 goto out; 440 441 state->curr_norm = std; 442 443 ret = adv7180_program_std(state); 444 out: 445 mutex_unlock(&state->mutex); 446 return ret; 447 } 448 449 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 450 { 451 struct adv7180_state *state = to_state(sd); 452 453 *norm = state->curr_norm; 454 455 return 0; 456 } 457 458 static int adv7180_g_frame_interval(struct v4l2_subdev *sd, 459 struct v4l2_subdev_frame_interval *fi) 460 { 461 struct adv7180_state *state = to_state(sd); 462 463 if (state->curr_norm & V4L2_STD_525_60) { 464 fi->interval.numerator = 1001; 465 fi->interval.denominator = 30000; 466 } else { 467 fi->interval.numerator = 1; 468 fi->interval.denominator = 25; 469 } 470 471 return 0; 472 } 473 474 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 475 { 476 if (!state->pwdn_gpio) 477 return; 478 479 if (on) { 480 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 481 usleep_range(5000, 10000); 482 } else { 483 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 484 } 485 } 486 487 static int adv7180_set_power(struct adv7180_state *state, bool on) 488 { 489 u8 val; 490 int ret; 491 492 if (on) 493 val = ADV7180_PWR_MAN_ON; 494 else 495 val = ADV7180_PWR_MAN_OFF; 496 497 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 498 if (ret) 499 return ret; 500 501 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 502 if (on) { 503 adv7180_csi_write(state, 0xDE, 0x02); 504 adv7180_csi_write(state, 0xD2, 0xF7); 505 adv7180_csi_write(state, 0xD8, 0x65); 506 adv7180_csi_write(state, 0xE0, 0x09); 507 adv7180_csi_write(state, 0x2C, 0x00); 508 if (state->field == V4L2_FIELD_NONE) 509 adv7180_csi_write(state, 0x1D, 0x80); 510 adv7180_csi_write(state, 0x00, 0x00); 511 } else { 512 adv7180_csi_write(state, 0x00, 0x80); 513 } 514 } 515 516 return 0; 517 } 518 519 static int adv7180_s_power(struct v4l2_subdev *sd, int on) 520 { 521 struct adv7180_state *state = to_state(sd); 522 int ret; 523 524 ret = mutex_lock_interruptible(&state->mutex); 525 if (ret) 526 return ret; 527 528 ret = adv7180_set_power(state, on); 529 if (ret == 0) 530 state->powered = on; 531 532 mutex_unlock(&state->mutex); 533 return ret; 534 } 535 536 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 537 { 538 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 539 struct adv7180_state *state = to_state(sd); 540 int ret = mutex_lock_interruptible(&state->mutex); 541 int val; 542 543 if (ret) 544 return ret; 545 val = ctrl->val; 546 switch (ctrl->id) { 547 case V4L2_CID_BRIGHTNESS: 548 ret = adv7180_write(state, ADV7180_REG_BRI, val); 549 break; 550 case V4L2_CID_HUE: 551 /*Hue is inverted according to HSL chart */ 552 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 553 break; 554 case V4L2_CID_CONTRAST: 555 ret = adv7180_write(state, ADV7180_REG_CON, val); 556 break; 557 case V4L2_CID_SATURATION: 558 /* 559 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 560 *Let's not confuse the user, everybody understands saturation 561 */ 562 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 563 if (ret < 0) 564 break; 565 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 566 break; 567 case V4L2_CID_ADV_FAST_SWITCH: 568 if (ctrl->val) { 569 /* ADI required write */ 570 adv7180_write(state, 0x80d9, 0x44); 571 adv7180_write(state, ADV7180_REG_FLCONTROL, 572 ADV7180_FLCONTROL_FL_ENABLE); 573 } else { 574 /* ADI required write */ 575 adv7180_write(state, 0x80d9, 0xc4); 576 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 577 } 578 break; 579 default: 580 ret = -EINVAL; 581 } 582 583 mutex_unlock(&state->mutex); 584 return ret; 585 } 586 587 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 588 .s_ctrl = adv7180_s_ctrl, 589 }; 590 591 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 592 .ops = &adv7180_ctrl_ops, 593 .id = V4L2_CID_ADV_FAST_SWITCH, 594 .name = "Fast Switching", 595 .type = V4L2_CTRL_TYPE_BOOLEAN, 596 .min = 0, 597 .max = 1, 598 .step = 1, 599 }; 600 601 static int adv7180_init_controls(struct adv7180_state *state) 602 { 603 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 604 605 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 606 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 607 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 608 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 609 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 610 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 611 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 612 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 613 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 614 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 615 V4L2_CID_HUE, ADV7180_HUE_MIN, 616 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 617 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 618 619 state->sd.ctrl_handler = &state->ctrl_hdl; 620 if (state->ctrl_hdl.error) { 621 int err = state->ctrl_hdl.error; 622 623 v4l2_ctrl_handler_free(&state->ctrl_hdl); 624 return err; 625 } 626 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 627 628 return 0; 629 } 630 static void adv7180_exit_controls(struct adv7180_state *state) 631 { 632 v4l2_ctrl_handler_free(&state->ctrl_hdl); 633 } 634 635 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 636 struct v4l2_subdev_pad_config *cfg, 637 struct v4l2_subdev_mbus_code_enum *code) 638 { 639 if (code->index != 0) 640 return -EINVAL; 641 642 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 643 644 return 0; 645 } 646 647 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 648 struct v4l2_mbus_framefmt *fmt) 649 { 650 struct adv7180_state *state = to_state(sd); 651 652 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 653 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 654 fmt->width = 720; 655 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 656 657 if (state->field == V4L2_FIELD_ALTERNATE) 658 fmt->height /= 2; 659 660 return 0; 661 } 662 663 static int adv7180_set_field_mode(struct adv7180_state *state) 664 { 665 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 666 return 0; 667 668 if (state->field == V4L2_FIELD_NONE) { 669 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 670 adv7180_csi_write(state, 0x01, 0x20); 671 adv7180_csi_write(state, 0x02, 0x28); 672 adv7180_csi_write(state, 0x03, 0x38); 673 adv7180_csi_write(state, 0x04, 0x30); 674 adv7180_csi_write(state, 0x05, 0x30); 675 adv7180_csi_write(state, 0x06, 0x80); 676 adv7180_csi_write(state, 0x07, 0x70); 677 adv7180_csi_write(state, 0x08, 0x50); 678 } 679 adv7180_vpp_write(state, 0xa3, 0x00); 680 adv7180_vpp_write(state, 0x5b, 0x00); 681 adv7180_vpp_write(state, 0x55, 0x80); 682 } else { 683 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 684 adv7180_csi_write(state, 0x01, 0x18); 685 adv7180_csi_write(state, 0x02, 0x18); 686 adv7180_csi_write(state, 0x03, 0x30); 687 adv7180_csi_write(state, 0x04, 0x20); 688 adv7180_csi_write(state, 0x05, 0x28); 689 adv7180_csi_write(state, 0x06, 0x40); 690 adv7180_csi_write(state, 0x07, 0x58); 691 adv7180_csi_write(state, 0x08, 0x30); 692 } 693 adv7180_vpp_write(state, 0xa3, 0x70); 694 adv7180_vpp_write(state, 0x5b, 0x80); 695 adv7180_vpp_write(state, 0x55, 0x00); 696 } 697 698 return 0; 699 } 700 701 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 702 struct v4l2_subdev_pad_config *cfg, 703 struct v4l2_subdev_format *format) 704 { 705 struct adv7180_state *state = to_state(sd); 706 707 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 708 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0); 709 } else { 710 adv7180_mbus_fmt(sd, &format->format); 711 format->format.field = state->field; 712 } 713 714 return 0; 715 } 716 717 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 718 struct v4l2_subdev_pad_config *cfg, 719 struct v4l2_subdev_format *format) 720 { 721 struct adv7180_state *state = to_state(sd); 722 struct v4l2_mbus_framefmt *framefmt; 723 int ret; 724 725 switch (format->format.field) { 726 case V4L2_FIELD_NONE: 727 if (state->chip_info->flags & ADV7180_FLAG_I2P) 728 break; 729 /* fall through */ 730 default: 731 format->format.field = V4L2_FIELD_ALTERNATE; 732 break; 733 } 734 735 ret = adv7180_mbus_fmt(sd, &format->format); 736 737 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 738 if (state->field != format->format.field) { 739 state->field = format->format.field; 740 adv7180_set_power(state, false); 741 adv7180_set_field_mode(state); 742 adv7180_set_power(state, true); 743 } 744 } else { 745 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0); 746 *framefmt = format->format; 747 } 748 749 return ret; 750 } 751 752 static int adv7180_g_mbus_config(struct v4l2_subdev *sd, 753 struct v4l2_mbus_config *cfg) 754 { 755 struct adv7180_state *state = to_state(sd); 756 757 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 758 cfg->type = V4L2_MBUS_CSI2_DPHY; 759 cfg->flags = V4L2_MBUS_CSI2_1_LANE | 760 V4L2_MBUS_CSI2_CHANNEL_0 | 761 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 762 } else { 763 /* 764 * The ADV7180 sensor supports BT.601/656 output modes. 765 * The BT.656 is default and not yet configurable by s/w. 766 */ 767 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | 768 V4L2_MBUS_DATA_ACTIVE_HIGH; 769 cfg->type = V4L2_MBUS_BT656; 770 } 771 772 return 0; 773 } 774 775 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 776 { 777 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 778 779 return 0; 780 } 781 782 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) 783 { 784 struct adv7180_state *state = to_state(sd); 785 786 if (state->curr_norm & V4L2_STD_525_60) { 787 aspect->numerator = 11; 788 aspect->denominator = 10; 789 } else { 790 aspect->numerator = 54; 791 aspect->denominator = 59; 792 } 793 794 return 0; 795 } 796 797 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 798 { 799 *norm = V4L2_STD_ALL; 800 return 0; 801 } 802 803 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 804 { 805 struct adv7180_state *state = to_state(sd); 806 int ret; 807 808 /* It's always safe to stop streaming, no need to take the lock */ 809 if (!enable) { 810 state->streaming = enable; 811 return 0; 812 } 813 814 /* Must wait until querystd released the lock */ 815 ret = mutex_lock_interruptible(&state->mutex); 816 if (ret) 817 return ret; 818 state->streaming = enable; 819 mutex_unlock(&state->mutex); 820 return 0; 821 } 822 823 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 824 struct v4l2_fh *fh, 825 struct v4l2_event_subscription *sub) 826 { 827 switch (sub->type) { 828 case V4L2_EVENT_SOURCE_CHANGE: 829 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 830 case V4L2_EVENT_CTRL: 831 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 832 default: 833 return -EINVAL; 834 } 835 } 836 837 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 838 .s_std = adv7180_s_std, 839 .g_std = adv7180_g_std, 840 .g_frame_interval = adv7180_g_frame_interval, 841 .querystd = adv7180_querystd, 842 .g_input_status = adv7180_g_input_status, 843 .s_routing = adv7180_s_routing, 844 .g_mbus_config = adv7180_g_mbus_config, 845 .g_pixelaspect = adv7180_g_pixelaspect, 846 .g_tvnorms = adv7180_g_tvnorms, 847 .s_stream = adv7180_s_stream, 848 }; 849 850 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 851 .s_power = adv7180_s_power, 852 .subscribe_event = adv7180_subscribe_event, 853 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 854 }; 855 856 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 857 .enum_mbus_code = adv7180_enum_mbus_code, 858 .set_fmt = adv7180_set_pad_format, 859 .get_fmt = adv7180_get_pad_format, 860 }; 861 862 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 863 .g_skip_frames = adv7180_get_skip_frames, 864 }; 865 866 static const struct v4l2_subdev_ops adv7180_ops = { 867 .core = &adv7180_core_ops, 868 .video = &adv7180_video_ops, 869 .pad = &adv7180_pad_ops, 870 .sensor = &adv7180_sensor_ops, 871 }; 872 873 static irqreturn_t adv7180_irq(int irq, void *devid) 874 { 875 struct adv7180_state *state = devid; 876 u8 isr3; 877 878 mutex_lock(&state->mutex); 879 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 880 /* clear */ 881 adv7180_write(state, ADV7180_REG_ICR3, isr3); 882 883 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 884 static const struct v4l2_event src_ch = { 885 .type = V4L2_EVENT_SOURCE_CHANGE, 886 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 887 }; 888 889 v4l2_subdev_notify_event(&state->sd, &src_ch); 890 } 891 mutex_unlock(&state->mutex); 892 893 return IRQ_HANDLED; 894 } 895 896 static int adv7180_init(struct adv7180_state *state) 897 { 898 int ret; 899 900 /* ITU-R BT.656-4 compatible */ 901 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 902 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 903 if (ret < 0) 904 return ret; 905 906 /* Manually set V bit end position in NTSC mode */ 907 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 908 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 909 } 910 911 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 912 { 913 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 914 (std << 4) | state->input); 915 } 916 917 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 918 { 919 int ret; 920 921 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 922 if (ret < 0) 923 return ret; 924 925 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 926 ret |= input; 927 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 928 } 929 930 static int adv7182_init(struct adv7180_state *state) 931 { 932 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 933 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 934 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 935 936 if (state->chip_info->flags & ADV7180_FLAG_I2P) 937 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 938 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 939 940 if (state->chip_info->flags & ADV7180_FLAG_V2) { 941 /* ADI recommended writes for improved video quality */ 942 adv7180_write(state, 0x0080, 0x51); 943 adv7180_write(state, 0x0081, 0x51); 944 adv7180_write(state, 0x0082, 0x68); 945 } 946 947 /* ADI required writes */ 948 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 949 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 950 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 951 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 952 } else { 953 if (state->chip_info->flags & ADV7180_FLAG_V2) 954 adv7180_write(state, 955 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 956 0x17); 957 else 958 adv7180_write(state, 959 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 960 0x07); 961 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 962 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 963 } 964 965 adv7180_write(state, 0x0013, 0x00); 966 967 return 0; 968 } 969 970 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 971 { 972 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); 973 } 974 975 enum adv7182_input_type { 976 ADV7182_INPUT_TYPE_CVBS, 977 ADV7182_INPUT_TYPE_DIFF_CVBS, 978 ADV7182_INPUT_TYPE_SVIDEO, 979 ADV7182_INPUT_TYPE_YPBPR, 980 }; 981 982 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 983 { 984 switch (input) { 985 case ADV7182_INPUT_CVBS_AIN1: 986 case ADV7182_INPUT_CVBS_AIN2: 987 case ADV7182_INPUT_CVBS_AIN3: 988 case ADV7182_INPUT_CVBS_AIN4: 989 case ADV7182_INPUT_CVBS_AIN5: 990 case ADV7182_INPUT_CVBS_AIN6: 991 case ADV7182_INPUT_CVBS_AIN7: 992 case ADV7182_INPUT_CVBS_AIN8: 993 return ADV7182_INPUT_TYPE_CVBS; 994 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 995 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 996 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 997 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 998 return ADV7182_INPUT_TYPE_SVIDEO; 999 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1000 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1001 return ADV7182_INPUT_TYPE_YPBPR; 1002 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1003 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1004 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1005 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1006 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1007 default: /* Will never happen */ 1008 return 0; 1009 } 1010 } 1011 1012 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1013 static unsigned int adv7182_lbias_settings[][3] = { 1014 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1015 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1016 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1017 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1018 }; 1019 1020 static unsigned int adv7280_lbias_settings[][3] = { 1021 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1022 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1023 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1024 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1025 }; 1026 1027 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1028 { 1029 enum adv7182_input_type input_type; 1030 unsigned int *lbias; 1031 unsigned int i; 1032 int ret; 1033 1034 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1035 if (ret) 1036 return ret; 1037 1038 /* Reset clamp circuitry - ADI recommended writes */ 1039 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1040 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1041 1042 input_type = adv7182_get_input_type(input); 1043 1044 switch (input_type) { 1045 case ADV7182_INPUT_TYPE_CVBS: 1046 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1047 /* ADI recommends to use the SH1 filter */ 1048 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1049 break; 1050 default: 1051 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1052 break; 1053 } 1054 1055 if (state->chip_info->flags & ADV7180_FLAG_V2) 1056 lbias = adv7280_lbias_settings[input_type]; 1057 else 1058 lbias = adv7182_lbias_settings[input_type]; 1059 1060 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1061 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1062 1063 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1064 /* ADI required writes to make differential CVBS work */ 1065 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1066 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1067 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1068 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1069 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1070 } else { 1071 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1072 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1073 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1074 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1075 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1076 } 1077 1078 return 0; 1079 } 1080 1081 static const struct adv7180_chip_info adv7180_info = { 1082 .flags = ADV7180_FLAG_RESET_POWERED, 1083 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1084 * all inputs and let the card driver take care of validation 1085 */ 1086 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1087 BIT(ADV7180_INPUT_CVBS_AIN2) | 1088 BIT(ADV7180_INPUT_CVBS_AIN3) | 1089 BIT(ADV7180_INPUT_CVBS_AIN4) | 1090 BIT(ADV7180_INPUT_CVBS_AIN5) | 1091 BIT(ADV7180_INPUT_CVBS_AIN6) | 1092 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1093 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1094 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1095 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1096 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1097 .init = adv7180_init, 1098 .set_std = adv7180_set_std, 1099 .select_input = adv7180_select_input, 1100 }; 1101 1102 static const struct adv7180_chip_info adv7182_info = { 1103 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1104 BIT(ADV7182_INPUT_CVBS_AIN2) | 1105 BIT(ADV7182_INPUT_CVBS_AIN3) | 1106 BIT(ADV7182_INPUT_CVBS_AIN4) | 1107 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1108 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1109 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1110 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1111 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1112 .init = adv7182_init, 1113 .set_std = adv7182_set_std, 1114 .select_input = adv7182_select_input, 1115 }; 1116 1117 static const struct adv7180_chip_info adv7280_info = { 1118 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1119 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1120 BIT(ADV7182_INPUT_CVBS_AIN2) | 1121 BIT(ADV7182_INPUT_CVBS_AIN3) | 1122 BIT(ADV7182_INPUT_CVBS_AIN4) | 1123 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1124 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1125 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1126 .init = adv7182_init, 1127 .set_std = adv7182_set_std, 1128 .select_input = adv7182_select_input, 1129 }; 1130 1131 static const struct adv7180_chip_info adv7280_m_info = { 1132 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1133 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1134 BIT(ADV7182_INPUT_CVBS_AIN2) | 1135 BIT(ADV7182_INPUT_CVBS_AIN3) | 1136 BIT(ADV7182_INPUT_CVBS_AIN4) | 1137 BIT(ADV7182_INPUT_CVBS_AIN5) | 1138 BIT(ADV7182_INPUT_CVBS_AIN6) | 1139 BIT(ADV7182_INPUT_CVBS_AIN7) | 1140 BIT(ADV7182_INPUT_CVBS_AIN8) | 1141 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1142 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1143 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1144 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1145 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1146 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1147 .init = adv7182_init, 1148 .set_std = adv7182_set_std, 1149 .select_input = adv7182_select_input, 1150 }; 1151 1152 static const struct adv7180_chip_info adv7281_info = { 1153 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1154 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1155 BIT(ADV7182_INPUT_CVBS_AIN2) | 1156 BIT(ADV7182_INPUT_CVBS_AIN7) | 1157 BIT(ADV7182_INPUT_CVBS_AIN8) | 1158 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1159 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1160 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1161 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1162 .init = adv7182_init, 1163 .set_std = adv7182_set_std, 1164 .select_input = adv7182_select_input, 1165 }; 1166 1167 static const struct adv7180_chip_info adv7281_m_info = { 1168 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1169 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1170 BIT(ADV7182_INPUT_CVBS_AIN2) | 1171 BIT(ADV7182_INPUT_CVBS_AIN3) | 1172 BIT(ADV7182_INPUT_CVBS_AIN4) | 1173 BIT(ADV7182_INPUT_CVBS_AIN7) | 1174 BIT(ADV7182_INPUT_CVBS_AIN8) | 1175 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1176 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1177 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1178 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1179 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1180 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1181 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1182 .init = adv7182_init, 1183 .set_std = adv7182_set_std, 1184 .select_input = adv7182_select_input, 1185 }; 1186 1187 static const struct adv7180_chip_info adv7281_ma_info = { 1188 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1189 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1190 BIT(ADV7182_INPUT_CVBS_AIN2) | 1191 BIT(ADV7182_INPUT_CVBS_AIN3) | 1192 BIT(ADV7182_INPUT_CVBS_AIN4) | 1193 BIT(ADV7182_INPUT_CVBS_AIN5) | 1194 BIT(ADV7182_INPUT_CVBS_AIN6) | 1195 BIT(ADV7182_INPUT_CVBS_AIN7) | 1196 BIT(ADV7182_INPUT_CVBS_AIN8) | 1197 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1198 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1199 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1200 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1201 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1202 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1203 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1204 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1205 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1206 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1207 .init = adv7182_init, 1208 .set_std = adv7182_set_std, 1209 .select_input = adv7182_select_input, 1210 }; 1211 1212 static const struct adv7180_chip_info adv7282_info = { 1213 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1214 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1215 BIT(ADV7182_INPUT_CVBS_AIN2) | 1216 BIT(ADV7182_INPUT_CVBS_AIN7) | 1217 BIT(ADV7182_INPUT_CVBS_AIN8) | 1218 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1219 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1220 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1221 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1222 .init = adv7182_init, 1223 .set_std = adv7182_set_std, 1224 .select_input = adv7182_select_input, 1225 }; 1226 1227 static const struct adv7180_chip_info adv7282_m_info = { 1228 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1229 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1230 BIT(ADV7182_INPUT_CVBS_AIN2) | 1231 BIT(ADV7182_INPUT_CVBS_AIN3) | 1232 BIT(ADV7182_INPUT_CVBS_AIN4) | 1233 BIT(ADV7182_INPUT_CVBS_AIN7) | 1234 BIT(ADV7182_INPUT_CVBS_AIN8) | 1235 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1236 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1237 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1238 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1239 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1240 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1241 .init = adv7182_init, 1242 .set_std = adv7182_set_std, 1243 .select_input = adv7182_select_input, 1244 }; 1245 1246 static int init_device(struct adv7180_state *state) 1247 { 1248 int ret; 1249 1250 mutex_lock(&state->mutex); 1251 1252 adv7180_set_power_pin(state, true); 1253 1254 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1255 usleep_range(5000, 10000); 1256 1257 ret = state->chip_info->init(state); 1258 if (ret) 1259 goto out_unlock; 1260 1261 ret = adv7180_program_std(state); 1262 if (ret) 1263 goto out_unlock; 1264 1265 adv7180_set_field_mode(state); 1266 1267 /* register for interrupts */ 1268 if (state->irq > 0) { 1269 /* config the Interrupt pin to be active low */ 1270 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1271 ADV7180_ICONF1_ACTIVE_LOW | 1272 ADV7180_ICONF1_PSYNC_ONLY); 1273 if (ret < 0) 1274 goto out_unlock; 1275 1276 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1277 if (ret < 0) 1278 goto out_unlock; 1279 1280 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1281 if (ret < 0) 1282 goto out_unlock; 1283 1284 /* enable AD change interrupts interrupts */ 1285 ret = adv7180_write(state, ADV7180_REG_IMR3, 1286 ADV7180_IRQ3_AD_CHANGE); 1287 if (ret < 0) 1288 goto out_unlock; 1289 1290 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1291 if (ret < 0) 1292 goto out_unlock; 1293 } 1294 1295 out_unlock: 1296 mutex_unlock(&state->mutex); 1297 1298 return ret; 1299 } 1300 1301 static int adv7180_probe(struct i2c_client *client, 1302 const struct i2c_device_id *id) 1303 { 1304 struct adv7180_state *state; 1305 struct v4l2_subdev *sd; 1306 int ret; 1307 1308 /* Check if the adapter supports the needed features */ 1309 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1310 return -EIO; 1311 1312 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1313 client->addr, client->adapter->name); 1314 1315 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1316 if (state == NULL) 1317 return -ENOMEM; 1318 1319 state->client = client; 1320 state->field = V4L2_FIELD_ALTERNATE; 1321 state->chip_info = (struct adv7180_chip_info *)id->driver_data; 1322 1323 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1324 GPIOD_OUT_HIGH); 1325 if (IS_ERR(state->pwdn_gpio)) { 1326 ret = PTR_ERR(state->pwdn_gpio); 1327 v4l_err(client, "request for power pin failed: %d\n", ret); 1328 return ret; 1329 } 1330 1331 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1332 state->csi_client = i2c_new_dummy(client->adapter, 1333 ADV7180_DEFAULT_CSI_I2C_ADDR); 1334 if (!state->csi_client) 1335 return -ENOMEM; 1336 } 1337 1338 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1339 state->vpp_client = i2c_new_dummy(client->adapter, 1340 ADV7180_DEFAULT_VPP_I2C_ADDR); 1341 if (!state->vpp_client) { 1342 ret = -ENOMEM; 1343 goto err_unregister_csi_client; 1344 } 1345 } 1346 1347 state->irq = client->irq; 1348 mutex_init(&state->mutex); 1349 state->curr_norm = V4L2_STD_NTSC; 1350 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1351 state->powered = true; 1352 else 1353 state->powered = false; 1354 state->input = 0; 1355 sd = &state->sd; 1356 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1357 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1358 1359 ret = adv7180_init_controls(state); 1360 if (ret) 1361 goto err_unregister_vpp_client; 1362 1363 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1364 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1365 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1366 if (ret) 1367 goto err_free_ctrl; 1368 1369 ret = init_device(state); 1370 if (ret) 1371 goto err_media_entity_cleanup; 1372 1373 if (state->irq) { 1374 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1375 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1376 KBUILD_MODNAME, state); 1377 if (ret) 1378 goto err_media_entity_cleanup; 1379 } 1380 1381 ret = v4l2_async_register_subdev(sd); 1382 if (ret) 1383 goto err_free_irq; 1384 1385 return 0; 1386 1387 err_free_irq: 1388 if (state->irq > 0) 1389 free_irq(client->irq, state); 1390 err_media_entity_cleanup: 1391 media_entity_cleanup(&sd->entity); 1392 err_free_ctrl: 1393 adv7180_exit_controls(state); 1394 err_unregister_vpp_client: 1395 i2c_unregister_device(state->vpp_client); 1396 err_unregister_csi_client: 1397 i2c_unregister_device(state->csi_client); 1398 mutex_destroy(&state->mutex); 1399 return ret; 1400 } 1401 1402 static int adv7180_remove(struct i2c_client *client) 1403 { 1404 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1405 struct adv7180_state *state = to_state(sd); 1406 1407 v4l2_async_unregister_subdev(sd); 1408 1409 if (state->irq > 0) 1410 free_irq(client->irq, state); 1411 1412 media_entity_cleanup(&sd->entity); 1413 adv7180_exit_controls(state); 1414 1415 i2c_unregister_device(state->vpp_client); 1416 i2c_unregister_device(state->csi_client); 1417 1418 adv7180_set_power_pin(state, false); 1419 1420 mutex_destroy(&state->mutex); 1421 1422 return 0; 1423 } 1424 1425 static const struct i2c_device_id adv7180_id[] = { 1426 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1427 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1428 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1429 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1430 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1431 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1432 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1433 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1434 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1435 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1436 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1437 {}, 1438 }; 1439 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1440 1441 #ifdef CONFIG_PM_SLEEP 1442 static int adv7180_suspend(struct device *dev) 1443 { 1444 struct i2c_client *client = to_i2c_client(dev); 1445 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1446 struct adv7180_state *state = to_state(sd); 1447 1448 return adv7180_set_power(state, false); 1449 } 1450 1451 static int adv7180_resume(struct device *dev) 1452 { 1453 struct i2c_client *client = to_i2c_client(dev); 1454 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1455 struct adv7180_state *state = to_state(sd); 1456 int ret; 1457 1458 ret = init_device(state); 1459 if (ret < 0) 1460 return ret; 1461 1462 ret = adv7180_set_power(state, state->powered); 1463 if (ret) 1464 return ret; 1465 1466 return 0; 1467 } 1468 1469 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1470 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1471 1472 #else 1473 #define ADV7180_PM_OPS NULL 1474 #endif 1475 1476 #ifdef CONFIG_OF 1477 static const struct of_device_id adv7180_of_id[] = { 1478 { .compatible = "adi,adv7180", }, 1479 { .compatible = "adi,adv7180cp", }, 1480 { .compatible = "adi,adv7180st", }, 1481 { .compatible = "adi,adv7182", }, 1482 { .compatible = "adi,adv7280", }, 1483 { .compatible = "adi,adv7280-m", }, 1484 { .compatible = "adi,adv7281", }, 1485 { .compatible = "adi,adv7281-m", }, 1486 { .compatible = "adi,adv7281-ma", }, 1487 { .compatible = "adi,adv7282", }, 1488 { .compatible = "adi,adv7282-m", }, 1489 { }, 1490 }; 1491 1492 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1493 #endif 1494 1495 static struct i2c_driver adv7180_driver = { 1496 .driver = { 1497 .name = KBUILD_MODNAME, 1498 .pm = ADV7180_PM_OPS, 1499 .of_match_table = of_match_ptr(adv7180_of_id), 1500 }, 1501 .probe = adv7180_probe, 1502 .remove = adv7180_remove, 1503 .id_table = adv7180_id, 1504 }; 1505 1506 module_i2c_driver(adv7180_driver); 1507 1508 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1509 MODULE_AUTHOR("Mocean Laboratories"); 1510 MODULE_LICENSE("GPL v2"); 1511