1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/slab.h> 15 #include <linux/of.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/videodev2.h> 18 #include <media/v4l2-ioctl.h> 19 #include <media/v4l2-event.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ctrls.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 29 #define ADV7180_STD_NTSC_J 0x4 30 #define ADV7180_STD_NTSC_M 0x5 31 #define ADV7180_STD_PAL60 0x6 32 #define ADV7180_STD_NTSC_443 0x7 33 #define ADV7180_STD_PAL_BG 0x8 34 #define ADV7180_STD_PAL_N 0x9 35 #define ADV7180_STD_PAL_M 0xa 36 #define ADV7180_STD_PAL_M_PED 0xb 37 #define ADV7180_STD_PAL_COMB_N 0xc 38 #define ADV7180_STD_PAL_COMB_N_PED 0xd 39 #define ADV7180_STD_PAL_SECAM 0xe 40 #define ADV7180_STD_PAL_SECAM_PED 0xf 41 42 #define ADV7180_REG_INPUT_CONTROL 0x0000 43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 44 45 #define ADV7182_REG_INPUT_VIDSEL 0x0002 46 47 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 48 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 49 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 50 51 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 52 #define ADV7180_AUTODETECT_DEFAULT 0x7f 53 /* Contrast */ 54 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 55 #define ADV7180_CON_MIN 0 56 #define ADV7180_CON_DEF 128 57 #define ADV7180_CON_MAX 255 58 /* Brightness*/ 59 #define ADV7180_REG_BRI 0x000a /*Signed */ 60 #define ADV7180_BRI_MIN -128 61 #define ADV7180_BRI_DEF 0 62 #define ADV7180_BRI_MAX 127 63 /* Hue */ 64 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 65 #define ADV7180_HUE_MIN -127 66 #define ADV7180_HUE_DEF 0 67 #define ADV7180_HUE_MAX 128 68 69 #define ADV7180_REG_CTRL 0x000e 70 #define ADV7180_CTRL_IRQ_SPACE 0x20 71 72 #define ADV7180_REG_PWR_MAN 0x0f 73 #define ADV7180_PWR_MAN_ON 0x04 74 #define ADV7180_PWR_MAN_OFF 0x24 75 #define ADV7180_PWR_MAN_RES 0x80 76 77 #define ADV7180_REG_STATUS1 0x0010 78 #define ADV7180_STATUS1_IN_LOCK 0x01 79 #define ADV7180_STATUS1_AUTOD_MASK 0x70 80 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 81 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 82 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 83 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 84 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 85 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 86 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 87 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 88 89 #define ADV7180_REG_IDENT 0x0011 90 #define ADV7180_ID_7180 0x18 91 92 #define ADV7180_REG_STATUS3 0x0013 93 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 94 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 95 #define ADV7180_REG_CTRL_2 0x001d 96 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 97 #define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12 98 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 99 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 100 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 101 #define ADV7180_REG_LOCK_CNT 0x0051 102 #define ADV7180_REG_CVBS_TRIM 0x0052 103 #define ADV7180_REG_CLAMP_ADJ 0x005a 104 #define ADV7180_REG_RES_CIR 0x005f 105 #define ADV7180_REG_DIFF_MODE 0x0060 106 107 #define ADV7180_REG_ICONF1 0x2040 108 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 109 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 110 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 111 /* Saturation */ 112 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 113 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 114 #define ADV7180_SAT_MIN 0 115 #define ADV7180_SAT_DEF 128 116 #define ADV7180_SAT_MAX 255 117 118 #define ADV7180_IRQ1_LOCK 0x01 119 #define ADV7180_IRQ1_UNLOCK 0x02 120 #define ADV7180_REG_ISR1 0x2042 121 #define ADV7180_REG_ICR1 0x2043 122 #define ADV7180_REG_IMR1 0x2044 123 #define ADV7180_REG_IMR2 0x2048 124 #define ADV7180_IRQ3_AD_CHANGE 0x08 125 #define ADV7180_REG_ISR3 0x204A 126 #define ADV7180_REG_ICR3 0x204B 127 #define ADV7180_REG_IMR3 0x204C 128 #define ADV7180_REG_IMR4 0x2050 129 130 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 131 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 132 133 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 134 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 135 136 #define ADV7180_REG_ACE_CTRL1 0x4080 137 #define ADV7180_REG_ACE_CTRL5 0x4084 138 #define ADV7180_REG_FLCONTROL 0x40e0 139 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 140 141 #define ADV7180_REG_RST_CLAMP 0x809c 142 #define ADV7180_REG_AGC_ADJ1 0x80b6 143 #define ADV7180_REG_AGC_ADJ2 0x80c0 144 145 #define ADV7180_CSI_REG_PWRDN 0x00 146 #define ADV7180_CSI_PWRDN 0x80 147 148 #define ADV7180_INPUT_CVBS_AIN1 0x00 149 #define ADV7180_INPUT_CVBS_AIN2 0x01 150 #define ADV7180_INPUT_CVBS_AIN3 0x02 151 #define ADV7180_INPUT_CVBS_AIN4 0x03 152 #define ADV7180_INPUT_CVBS_AIN5 0x04 153 #define ADV7180_INPUT_CVBS_AIN6 0x05 154 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 155 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 156 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 157 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 158 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 159 160 #define ADV7182_INPUT_CVBS_AIN1 0x00 161 #define ADV7182_INPUT_CVBS_AIN2 0x01 162 #define ADV7182_INPUT_CVBS_AIN3 0x02 163 #define ADV7182_INPUT_CVBS_AIN4 0x03 164 #define ADV7182_INPUT_CVBS_AIN5 0x04 165 #define ADV7182_INPUT_CVBS_AIN6 0x05 166 #define ADV7182_INPUT_CVBS_AIN7 0x06 167 #define ADV7182_INPUT_CVBS_AIN8 0x07 168 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 169 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 170 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 171 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 172 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 173 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 174 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 175 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 176 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 177 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 178 179 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 180 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 181 182 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 183 184 /* Initial number of frames to skip to avoid possible garbage */ 185 #define ADV7180_NUM_OF_SKIP_FRAMES 2 186 187 struct adv7180_state; 188 189 #define ADV7180_FLAG_RESET_POWERED BIT(0) 190 #define ADV7180_FLAG_V2 BIT(1) 191 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 192 #define ADV7180_FLAG_I2P BIT(3) 193 194 struct adv7180_chip_info { 195 unsigned int flags; 196 unsigned int valid_input_mask; 197 int (*set_std)(struct adv7180_state *st, unsigned int std); 198 int (*select_input)(struct adv7180_state *st, unsigned int input); 199 int (*init)(struct adv7180_state *state); 200 }; 201 202 struct adv7180_state { 203 struct v4l2_ctrl_handler ctrl_hdl; 204 struct v4l2_subdev sd; 205 struct media_pad pad; 206 struct mutex mutex; /* mutual excl. when accessing chip */ 207 int irq; 208 struct gpio_desc *pwdn_gpio; 209 struct gpio_desc *rst_gpio; 210 v4l2_std_id curr_norm; 211 bool powered; 212 bool streaming; 213 u8 input; 214 215 struct i2c_client *client; 216 unsigned int register_page; 217 struct i2c_client *csi_client; 218 struct i2c_client *vpp_client; 219 const struct adv7180_chip_info *chip_info; 220 enum v4l2_field field; 221 bool force_bt656_4; 222 }; 223 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 224 struct adv7180_state, \ 225 ctrl_hdl)->sd) 226 227 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 228 { 229 if (state->register_page != page) { 230 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 231 page); 232 state->register_page = page; 233 } 234 235 return 0; 236 } 237 238 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 239 unsigned int value) 240 { 241 lockdep_assert_held(&state->mutex); 242 adv7180_select_page(state, reg >> 8); 243 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 244 } 245 246 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 247 { 248 lockdep_assert_held(&state->mutex); 249 adv7180_select_page(state, reg >> 8); 250 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 251 } 252 253 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 254 unsigned int value) 255 { 256 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 257 } 258 259 static int adv7180_set_video_standard(struct adv7180_state *state, 260 unsigned int std) 261 { 262 return state->chip_info->set_std(state, std); 263 } 264 265 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 266 unsigned int value) 267 { 268 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 269 } 270 271 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 272 { 273 /* in case V4L2_IN_ST_NO_SIGNAL */ 274 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 275 return V4L2_STD_UNKNOWN; 276 277 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 278 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 279 return V4L2_STD_NTSC; 280 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 281 return V4L2_STD_NTSC_443; 282 case ADV7180_STATUS1_AUTOD_PAL_M: 283 return V4L2_STD_PAL_M; 284 case ADV7180_STATUS1_AUTOD_PAL_60: 285 return V4L2_STD_PAL_60; 286 case ADV7180_STATUS1_AUTOD_PAL_B_G: 287 return V4L2_STD_PAL; 288 case ADV7180_STATUS1_AUTOD_SECAM: 289 return V4L2_STD_SECAM; 290 case ADV7180_STATUS1_AUTOD_PAL_COMB: 291 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 292 case ADV7180_STATUS1_AUTOD_SECAM_525: 293 return V4L2_STD_SECAM; 294 default: 295 return V4L2_STD_UNKNOWN; 296 } 297 } 298 299 static int v4l2_std_to_adv7180(v4l2_std_id std) 300 { 301 if (std == V4L2_STD_PAL_60) 302 return ADV7180_STD_PAL60; 303 if (std == V4L2_STD_NTSC_443) 304 return ADV7180_STD_NTSC_443; 305 if (std == V4L2_STD_PAL_N) 306 return ADV7180_STD_PAL_N; 307 if (std == V4L2_STD_PAL_M) 308 return ADV7180_STD_PAL_M; 309 if (std == V4L2_STD_PAL_Nc) 310 return ADV7180_STD_PAL_COMB_N; 311 312 if (std & V4L2_STD_PAL) 313 return ADV7180_STD_PAL_BG; 314 if (std & V4L2_STD_NTSC) 315 return ADV7180_STD_NTSC_M; 316 if (std & V4L2_STD_SECAM) 317 return ADV7180_STD_PAL_SECAM; 318 319 return -EINVAL; 320 } 321 322 static u32 adv7180_status_to_v4l2(u8 status1) 323 { 324 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 325 return V4L2_IN_ST_NO_SIGNAL; 326 327 return 0; 328 } 329 330 static int __adv7180_status(struct adv7180_state *state, u32 *status, 331 v4l2_std_id *std) 332 { 333 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 334 335 if (status1 < 0) 336 return status1; 337 338 if (status) 339 *status = adv7180_status_to_v4l2(status1); 340 if (std) 341 *std = adv7180_std_to_v4l2(status1); 342 343 return 0; 344 } 345 346 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 347 { 348 return container_of(sd, struct adv7180_state, sd); 349 } 350 351 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 352 { 353 struct adv7180_state *state = to_state(sd); 354 int err = mutex_lock_interruptible(&state->mutex); 355 if (err) 356 return err; 357 358 if (state->streaming) { 359 err = -EBUSY; 360 goto unlock; 361 } 362 363 err = adv7180_set_video_standard(state, 364 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 365 if (err) 366 goto unlock; 367 368 msleep(100); 369 __adv7180_status(state, NULL, std); 370 371 err = v4l2_std_to_adv7180(state->curr_norm); 372 if (err < 0) 373 goto unlock; 374 375 err = adv7180_set_video_standard(state, err); 376 377 unlock: 378 mutex_unlock(&state->mutex); 379 return err; 380 } 381 382 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 383 u32 output, u32 config) 384 { 385 struct adv7180_state *state = to_state(sd); 386 int ret = mutex_lock_interruptible(&state->mutex); 387 388 if (ret) 389 return ret; 390 391 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 392 ret = -EINVAL; 393 goto out; 394 } 395 396 ret = state->chip_info->select_input(state, input); 397 398 if (ret == 0) 399 state->input = input; 400 out: 401 mutex_unlock(&state->mutex); 402 return ret; 403 } 404 405 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 406 { 407 struct adv7180_state *state = to_state(sd); 408 int ret = mutex_lock_interruptible(&state->mutex); 409 if (ret) 410 return ret; 411 412 ret = __adv7180_status(state, status, NULL); 413 mutex_unlock(&state->mutex); 414 return ret; 415 } 416 417 static int adv7180_program_std(struct adv7180_state *state) 418 { 419 int ret; 420 421 ret = v4l2_std_to_adv7180(state->curr_norm); 422 if (ret < 0) 423 return ret; 424 425 ret = adv7180_set_video_standard(state, ret); 426 if (ret < 0) 427 return ret; 428 return 0; 429 } 430 431 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 432 { 433 struct adv7180_state *state = to_state(sd); 434 int ret = mutex_lock_interruptible(&state->mutex); 435 436 if (ret) 437 return ret; 438 439 /* Make sure we can support this std */ 440 ret = v4l2_std_to_adv7180(std); 441 if (ret < 0) 442 goto out; 443 444 state->curr_norm = std; 445 446 ret = adv7180_program_std(state); 447 out: 448 mutex_unlock(&state->mutex); 449 return ret; 450 } 451 452 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 453 { 454 struct adv7180_state *state = to_state(sd); 455 456 *norm = state->curr_norm; 457 458 return 0; 459 } 460 461 static int adv7180_g_frame_interval(struct v4l2_subdev *sd, 462 struct v4l2_subdev_frame_interval *fi) 463 { 464 struct adv7180_state *state = to_state(sd); 465 466 if (state->curr_norm & V4L2_STD_525_60) { 467 fi->interval.numerator = 1001; 468 fi->interval.denominator = 30000; 469 } else { 470 fi->interval.numerator = 1; 471 fi->interval.denominator = 25; 472 } 473 474 return 0; 475 } 476 477 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 478 { 479 if (!state->pwdn_gpio) 480 return; 481 482 if (on) { 483 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 484 usleep_range(5000, 10000); 485 } else { 486 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 487 } 488 } 489 490 static void adv7180_set_reset_pin(struct adv7180_state *state, bool on) 491 { 492 if (!state->rst_gpio) 493 return; 494 495 if (on) { 496 gpiod_set_value_cansleep(state->rst_gpio, 1); 497 } else { 498 gpiod_set_value_cansleep(state->rst_gpio, 0); 499 usleep_range(5000, 10000); 500 } 501 } 502 503 static int adv7180_set_power(struct adv7180_state *state, bool on) 504 { 505 u8 val; 506 int ret; 507 508 if (on) 509 val = ADV7180_PWR_MAN_ON; 510 else 511 val = ADV7180_PWR_MAN_OFF; 512 513 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 514 if (ret) 515 return ret; 516 517 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 518 if (on) { 519 adv7180_csi_write(state, 0xDE, 0x02); 520 adv7180_csi_write(state, 0xD2, 0xF7); 521 adv7180_csi_write(state, 0xD8, 0x65); 522 adv7180_csi_write(state, 0xE0, 0x09); 523 adv7180_csi_write(state, 0x2C, 0x00); 524 if (state->field == V4L2_FIELD_NONE) 525 adv7180_csi_write(state, 0x1D, 0x80); 526 adv7180_csi_write(state, 0x00, 0x00); 527 } else { 528 adv7180_csi_write(state, 0x00, 0x80); 529 } 530 } 531 532 return 0; 533 } 534 535 static int adv7180_s_power(struct v4l2_subdev *sd, int on) 536 { 537 struct adv7180_state *state = to_state(sd); 538 int ret; 539 540 ret = mutex_lock_interruptible(&state->mutex); 541 if (ret) 542 return ret; 543 544 ret = adv7180_set_power(state, on); 545 if (ret == 0) 546 state->powered = on; 547 548 mutex_unlock(&state->mutex); 549 return ret; 550 } 551 552 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 553 { 554 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 555 struct adv7180_state *state = to_state(sd); 556 int ret = mutex_lock_interruptible(&state->mutex); 557 int val; 558 559 if (ret) 560 return ret; 561 val = ctrl->val; 562 switch (ctrl->id) { 563 case V4L2_CID_BRIGHTNESS: 564 ret = adv7180_write(state, ADV7180_REG_BRI, val); 565 break; 566 case V4L2_CID_HUE: 567 /*Hue is inverted according to HSL chart */ 568 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 569 break; 570 case V4L2_CID_CONTRAST: 571 ret = adv7180_write(state, ADV7180_REG_CON, val); 572 break; 573 case V4L2_CID_SATURATION: 574 /* 575 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 576 *Let's not confuse the user, everybody understands saturation 577 */ 578 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 579 if (ret < 0) 580 break; 581 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 582 break; 583 case V4L2_CID_ADV_FAST_SWITCH: 584 if (ctrl->val) { 585 /* ADI required write */ 586 adv7180_write(state, 0x80d9, 0x44); 587 adv7180_write(state, ADV7180_REG_FLCONTROL, 588 ADV7180_FLCONTROL_FL_ENABLE); 589 } else { 590 /* ADI required write */ 591 adv7180_write(state, 0x80d9, 0xc4); 592 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 593 } 594 break; 595 default: 596 ret = -EINVAL; 597 } 598 599 mutex_unlock(&state->mutex); 600 return ret; 601 } 602 603 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 604 .s_ctrl = adv7180_s_ctrl, 605 }; 606 607 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 608 .ops = &adv7180_ctrl_ops, 609 .id = V4L2_CID_ADV_FAST_SWITCH, 610 .name = "Fast Switching", 611 .type = V4L2_CTRL_TYPE_BOOLEAN, 612 .min = 0, 613 .max = 1, 614 .step = 1, 615 }; 616 617 static int adv7180_init_controls(struct adv7180_state *state) 618 { 619 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 620 621 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 622 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 623 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 624 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 625 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 626 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 627 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 628 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 629 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 630 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 631 V4L2_CID_HUE, ADV7180_HUE_MIN, 632 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 633 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 634 635 state->sd.ctrl_handler = &state->ctrl_hdl; 636 if (state->ctrl_hdl.error) { 637 int err = state->ctrl_hdl.error; 638 639 v4l2_ctrl_handler_free(&state->ctrl_hdl); 640 return err; 641 } 642 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 643 644 return 0; 645 } 646 static void adv7180_exit_controls(struct adv7180_state *state) 647 { 648 v4l2_ctrl_handler_free(&state->ctrl_hdl); 649 } 650 651 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 652 struct v4l2_subdev_state *sd_state, 653 struct v4l2_subdev_mbus_code_enum *code) 654 { 655 if (code->index != 0) 656 return -EINVAL; 657 658 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 659 660 return 0; 661 } 662 663 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 664 struct v4l2_mbus_framefmt *fmt) 665 { 666 struct adv7180_state *state = to_state(sd); 667 668 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 669 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 670 fmt->width = 720; 671 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 672 673 if (state->field == V4L2_FIELD_ALTERNATE) 674 fmt->height /= 2; 675 676 return 0; 677 } 678 679 static int adv7180_set_field_mode(struct adv7180_state *state) 680 { 681 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 682 return 0; 683 684 if (state->field == V4L2_FIELD_NONE) { 685 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 686 adv7180_csi_write(state, 0x01, 0x20); 687 adv7180_csi_write(state, 0x02, 0x28); 688 adv7180_csi_write(state, 0x03, 0x38); 689 adv7180_csi_write(state, 0x04, 0x30); 690 adv7180_csi_write(state, 0x05, 0x30); 691 adv7180_csi_write(state, 0x06, 0x80); 692 adv7180_csi_write(state, 0x07, 0x70); 693 adv7180_csi_write(state, 0x08, 0x50); 694 } 695 adv7180_vpp_write(state, 0xa3, 0x00); 696 adv7180_vpp_write(state, 0x5b, 0x00); 697 adv7180_vpp_write(state, 0x55, 0x80); 698 } else { 699 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 700 adv7180_csi_write(state, 0x01, 0x18); 701 adv7180_csi_write(state, 0x02, 0x18); 702 adv7180_csi_write(state, 0x03, 0x30); 703 adv7180_csi_write(state, 0x04, 0x20); 704 adv7180_csi_write(state, 0x05, 0x28); 705 adv7180_csi_write(state, 0x06, 0x40); 706 adv7180_csi_write(state, 0x07, 0x58); 707 adv7180_csi_write(state, 0x08, 0x30); 708 } 709 adv7180_vpp_write(state, 0xa3, 0x70); 710 adv7180_vpp_write(state, 0x5b, 0x80); 711 adv7180_vpp_write(state, 0x55, 0x00); 712 } 713 714 return 0; 715 } 716 717 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 718 struct v4l2_subdev_state *sd_state, 719 struct v4l2_subdev_format *format) 720 { 721 struct adv7180_state *state = to_state(sd); 722 723 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 724 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0); 725 } else { 726 adv7180_mbus_fmt(sd, &format->format); 727 format->format.field = state->field; 728 } 729 730 return 0; 731 } 732 733 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 734 struct v4l2_subdev_state *sd_state, 735 struct v4l2_subdev_format *format) 736 { 737 struct adv7180_state *state = to_state(sd); 738 struct v4l2_mbus_framefmt *framefmt; 739 int ret; 740 741 switch (format->format.field) { 742 case V4L2_FIELD_NONE: 743 if (state->chip_info->flags & ADV7180_FLAG_I2P) 744 break; 745 fallthrough; 746 default: 747 format->format.field = V4L2_FIELD_ALTERNATE; 748 break; 749 } 750 751 ret = adv7180_mbus_fmt(sd, &format->format); 752 753 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 754 if (state->field != format->format.field) { 755 state->field = format->format.field; 756 adv7180_set_power(state, false); 757 adv7180_set_field_mode(state); 758 adv7180_set_power(state, true); 759 } 760 } else { 761 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0); 762 *framefmt = format->format; 763 } 764 765 return ret; 766 } 767 768 static int adv7180_init_cfg(struct v4l2_subdev *sd, 769 struct v4l2_subdev_state *sd_state) 770 { 771 struct v4l2_subdev_format fmt = { 772 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY 773 : V4L2_SUBDEV_FORMAT_ACTIVE, 774 }; 775 776 return adv7180_set_pad_format(sd, sd_state, &fmt); 777 } 778 779 static int adv7180_get_mbus_config(struct v4l2_subdev *sd, 780 unsigned int pad, 781 struct v4l2_mbus_config *cfg) 782 { 783 struct adv7180_state *state = to_state(sd); 784 785 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 786 cfg->type = V4L2_MBUS_CSI2_DPHY; 787 cfg->bus.mipi_csi2.num_data_lanes = 1; 788 cfg->bus.mipi_csi2.flags = 0; 789 } else { 790 /* 791 * The ADV7180 sensor supports BT.601/656 output modes. 792 * The BT.656 is default and not yet configurable by s/w. 793 */ 794 cfg->bus.parallel.flags = V4L2_MBUS_MASTER | 795 V4L2_MBUS_PCLK_SAMPLE_RISING | 796 V4L2_MBUS_DATA_ACTIVE_HIGH; 797 cfg->type = V4L2_MBUS_BT656; 798 } 799 800 return 0; 801 } 802 803 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames) 804 { 805 *frames = ADV7180_NUM_OF_SKIP_FRAMES; 806 807 return 0; 808 } 809 810 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) 811 { 812 struct adv7180_state *state = to_state(sd); 813 814 if (state->curr_norm & V4L2_STD_525_60) { 815 aspect->numerator = 11; 816 aspect->denominator = 10; 817 } else { 818 aspect->numerator = 54; 819 aspect->denominator = 59; 820 } 821 822 return 0; 823 } 824 825 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 826 { 827 *norm = V4L2_STD_ALL; 828 return 0; 829 } 830 831 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 832 { 833 struct adv7180_state *state = to_state(sd); 834 int ret; 835 836 /* It's always safe to stop streaming, no need to take the lock */ 837 if (!enable) { 838 state->streaming = enable; 839 return 0; 840 } 841 842 /* Must wait until querystd released the lock */ 843 ret = mutex_lock_interruptible(&state->mutex); 844 if (ret) 845 return ret; 846 state->streaming = enable; 847 mutex_unlock(&state->mutex); 848 return 0; 849 } 850 851 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 852 struct v4l2_fh *fh, 853 struct v4l2_event_subscription *sub) 854 { 855 switch (sub->type) { 856 case V4L2_EVENT_SOURCE_CHANGE: 857 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 858 case V4L2_EVENT_CTRL: 859 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 860 default: 861 return -EINVAL; 862 } 863 } 864 865 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 866 .s_std = adv7180_s_std, 867 .g_std = adv7180_g_std, 868 .g_frame_interval = adv7180_g_frame_interval, 869 .querystd = adv7180_querystd, 870 .g_input_status = adv7180_g_input_status, 871 .s_routing = adv7180_s_routing, 872 .g_pixelaspect = adv7180_g_pixelaspect, 873 .g_tvnorms = adv7180_g_tvnorms, 874 .s_stream = adv7180_s_stream, 875 }; 876 877 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 878 .s_power = adv7180_s_power, 879 .subscribe_event = adv7180_subscribe_event, 880 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 881 }; 882 883 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 884 .init_cfg = adv7180_init_cfg, 885 .enum_mbus_code = adv7180_enum_mbus_code, 886 .set_fmt = adv7180_set_pad_format, 887 .get_fmt = adv7180_get_pad_format, 888 .get_mbus_config = adv7180_get_mbus_config, 889 }; 890 891 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = { 892 .g_skip_frames = adv7180_get_skip_frames, 893 }; 894 895 static const struct v4l2_subdev_ops adv7180_ops = { 896 .core = &adv7180_core_ops, 897 .video = &adv7180_video_ops, 898 .pad = &adv7180_pad_ops, 899 .sensor = &adv7180_sensor_ops, 900 }; 901 902 static irqreturn_t adv7180_irq(int irq, void *devid) 903 { 904 struct adv7180_state *state = devid; 905 u8 isr3; 906 907 mutex_lock(&state->mutex); 908 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 909 /* clear */ 910 adv7180_write(state, ADV7180_REG_ICR3, isr3); 911 912 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 913 static const struct v4l2_event src_ch = { 914 .type = V4L2_EVENT_SOURCE_CHANGE, 915 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 916 }; 917 918 v4l2_subdev_notify_event(&state->sd, &src_ch); 919 } 920 mutex_unlock(&state->mutex); 921 922 return IRQ_HANDLED; 923 } 924 925 static int adv7180_init(struct adv7180_state *state) 926 { 927 int ret; 928 929 /* ITU-R BT.656-4 compatible */ 930 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 931 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 932 if (ret < 0) 933 return ret; 934 935 /* Manually set V bit end position in NTSC mode */ 936 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 937 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 938 } 939 940 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 941 { 942 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 943 (std << 4) | state->input); 944 } 945 946 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 947 { 948 int ret; 949 950 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 951 if (ret < 0) 952 return ret; 953 954 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 955 ret |= input; 956 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 957 } 958 959 static int adv7182_init(struct adv7180_state *state) 960 { 961 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 962 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 963 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 964 965 if (state->chip_info->flags & ADV7180_FLAG_I2P) 966 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 967 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 968 969 if (state->chip_info->flags & ADV7180_FLAG_V2) { 970 /* ADI recommended writes for improved video quality */ 971 adv7180_write(state, 0x0080, 0x51); 972 adv7180_write(state, 0x0081, 0x51); 973 adv7180_write(state, 0x0082, 0x68); 974 } 975 976 /* ADI required writes */ 977 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 978 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 979 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 980 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 981 } else { 982 if (state->chip_info->flags & ADV7180_FLAG_V2) { 983 if (state->force_bt656_4) { 984 /* ITU-R BT.656-4 compatible */ 985 adv7180_write(state, 986 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 987 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 988 /* Manually set NEWAVMODE */ 989 adv7180_write(state, 990 ADV7180_REG_VSYNC_FIELD_CTL_1, 991 ADV7180_VSYNC_FIELD_CTL_1_NEWAV); 992 /* Manually set V bit end position in NTSC mode */ 993 adv7180_write(state, 994 ADV7180_REG_NTSC_V_BIT_END, 995 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 996 } else { 997 adv7180_write(state, 998 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 999 0x17); 1000 } 1001 } 1002 else 1003 adv7180_write(state, 1004 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 1005 0x07); 1006 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 1007 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 1008 } 1009 1010 adv7180_write(state, 0x0013, 0x00); 1011 1012 return 0; 1013 } 1014 1015 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 1016 { 1017 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); 1018 } 1019 1020 enum adv7182_input_type { 1021 ADV7182_INPUT_TYPE_CVBS, 1022 ADV7182_INPUT_TYPE_DIFF_CVBS, 1023 ADV7182_INPUT_TYPE_SVIDEO, 1024 ADV7182_INPUT_TYPE_YPBPR, 1025 }; 1026 1027 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 1028 { 1029 switch (input) { 1030 case ADV7182_INPUT_CVBS_AIN1: 1031 case ADV7182_INPUT_CVBS_AIN2: 1032 case ADV7182_INPUT_CVBS_AIN3: 1033 case ADV7182_INPUT_CVBS_AIN4: 1034 case ADV7182_INPUT_CVBS_AIN5: 1035 case ADV7182_INPUT_CVBS_AIN6: 1036 case ADV7182_INPUT_CVBS_AIN7: 1037 case ADV7182_INPUT_CVBS_AIN8: 1038 return ADV7182_INPUT_TYPE_CVBS; 1039 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 1040 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 1041 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 1042 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 1043 return ADV7182_INPUT_TYPE_SVIDEO; 1044 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 1045 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 1046 return ADV7182_INPUT_TYPE_YPBPR; 1047 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 1048 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 1049 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 1050 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 1051 return ADV7182_INPUT_TYPE_DIFF_CVBS; 1052 default: /* Will never happen */ 1053 return 0; 1054 } 1055 } 1056 1057 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 1058 static unsigned int adv7182_lbias_settings[][3] = { 1059 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1060 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1061 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1062 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1063 }; 1064 1065 static unsigned int adv7280_lbias_settings[][3] = { 1066 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1067 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1068 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1069 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1070 }; 1071 1072 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1073 { 1074 enum adv7182_input_type input_type; 1075 unsigned int *lbias; 1076 unsigned int i; 1077 int ret; 1078 1079 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1080 if (ret) 1081 return ret; 1082 1083 /* Reset clamp circuitry - ADI recommended writes */ 1084 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1085 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1086 1087 input_type = adv7182_get_input_type(input); 1088 1089 switch (input_type) { 1090 case ADV7182_INPUT_TYPE_CVBS: 1091 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1092 /* ADI recommends to use the SH1 filter */ 1093 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1094 break; 1095 default: 1096 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1097 break; 1098 } 1099 1100 if (state->chip_info->flags & ADV7180_FLAG_V2) 1101 lbias = adv7280_lbias_settings[input_type]; 1102 else 1103 lbias = adv7182_lbias_settings[input_type]; 1104 1105 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1106 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1107 1108 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1109 /* ADI required writes to make differential CVBS work */ 1110 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1111 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1112 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1113 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1114 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1115 } else { 1116 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1117 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1118 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1119 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1120 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1121 } 1122 1123 return 0; 1124 } 1125 1126 static const struct adv7180_chip_info adv7180_info = { 1127 .flags = ADV7180_FLAG_RESET_POWERED, 1128 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1129 * all inputs and let the card driver take care of validation 1130 */ 1131 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1132 BIT(ADV7180_INPUT_CVBS_AIN2) | 1133 BIT(ADV7180_INPUT_CVBS_AIN3) | 1134 BIT(ADV7180_INPUT_CVBS_AIN4) | 1135 BIT(ADV7180_INPUT_CVBS_AIN5) | 1136 BIT(ADV7180_INPUT_CVBS_AIN6) | 1137 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1138 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1139 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1140 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1141 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1142 .init = adv7180_init, 1143 .set_std = adv7180_set_std, 1144 .select_input = adv7180_select_input, 1145 }; 1146 1147 static const struct adv7180_chip_info adv7182_info = { 1148 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1149 BIT(ADV7182_INPUT_CVBS_AIN2) | 1150 BIT(ADV7182_INPUT_CVBS_AIN3) | 1151 BIT(ADV7182_INPUT_CVBS_AIN4) | 1152 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1153 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1154 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1155 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1156 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1157 .init = adv7182_init, 1158 .set_std = adv7182_set_std, 1159 .select_input = adv7182_select_input, 1160 }; 1161 1162 static const struct adv7180_chip_info adv7280_info = { 1163 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1164 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1165 BIT(ADV7182_INPUT_CVBS_AIN2) | 1166 BIT(ADV7182_INPUT_CVBS_AIN3) | 1167 BIT(ADV7182_INPUT_CVBS_AIN4) | 1168 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1169 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1170 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1171 .init = adv7182_init, 1172 .set_std = adv7182_set_std, 1173 .select_input = adv7182_select_input, 1174 }; 1175 1176 static const struct adv7180_chip_info adv7280_m_info = { 1177 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1178 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1179 BIT(ADV7182_INPUT_CVBS_AIN2) | 1180 BIT(ADV7182_INPUT_CVBS_AIN3) | 1181 BIT(ADV7182_INPUT_CVBS_AIN4) | 1182 BIT(ADV7182_INPUT_CVBS_AIN5) | 1183 BIT(ADV7182_INPUT_CVBS_AIN6) | 1184 BIT(ADV7182_INPUT_CVBS_AIN7) | 1185 BIT(ADV7182_INPUT_CVBS_AIN8) | 1186 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1187 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1188 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1189 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1190 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1191 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1192 .init = adv7182_init, 1193 .set_std = adv7182_set_std, 1194 .select_input = adv7182_select_input, 1195 }; 1196 1197 static const struct adv7180_chip_info adv7281_info = { 1198 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1199 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1200 BIT(ADV7182_INPUT_CVBS_AIN2) | 1201 BIT(ADV7182_INPUT_CVBS_AIN7) | 1202 BIT(ADV7182_INPUT_CVBS_AIN8) | 1203 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1204 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1205 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1206 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1207 .init = adv7182_init, 1208 .set_std = adv7182_set_std, 1209 .select_input = adv7182_select_input, 1210 }; 1211 1212 static const struct adv7180_chip_info adv7281_m_info = { 1213 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1214 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1215 BIT(ADV7182_INPUT_CVBS_AIN2) | 1216 BIT(ADV7182_INPUT_CVBS_AIN3) | 1217 BIT(ADV7182_INPUT_CVBS_AIN4) | 1218 BIT(ADV7182_INPUT_CVBS_AIN7) | 1219 BIT(ADV7182_INPUT_CVBS_AIN8) | 1220 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1221 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1222 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1223 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1224 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1225 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1226 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1227 .init = adv7182_init, 1228 .set_std = adv7182_set_std, 1229 .select_input = adv7182_select_input, 1230 }; 1231 1232 static const struct adv7180_chip_info adv7281_ma_info = { 1233 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1234 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1235 BIT(ADV7182_INPUT_CVBS_AIN2) | 1236 BIT(ADV7182_INPUT_CVBS_AIN3) | 1237 BIT(ADV7182_INPUT_CVBS_AIN4) | 1238 BIT(ADV7182_INPUT_CVBS_AIN5) | 1239 BIT(ADV7182_INPUT_CVBS_AIN6) | 1240 BIT(ADV7182_INPUT_CVBS_AIN7) | 1241 BIT(ADV7182_INPUT_CVBS_AIN8) | 1242 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1243 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1244 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1245 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1246 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1247 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1248 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1249 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1250 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1251 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1252 .init = adv7182_init, 1253 .set_std = adv7182_set_std, 1254 .select_input = adv7182_select_input, 1255 }; 1256 1257 static const struct adv7180_chip_info adv7282_info = { 1258 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1259 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1260 BIT(ADV7182_INPUT_CVBS_AIN2) | 1261 BIT(ADV7182_INPUT_CVBS_AIN7) | 1262 BIT(ADV7182_INPUT_CVBS_AIN8) | 1263 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1264 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1265 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1266 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1267 .init = adv7182_init, 1268 .set_std = adv7182_set_std, 1269 .select_input = adv7182_select_input, 1270 }; 1271 1272 static const struct adv7180_chip_info adv7282_m_info = { 1273 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1274 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1275 BIT(ADV7182_INPUT_CVBS_AIN2) | 1276 BIT(ADV7182_INPUT_CVBS_AIN3) | 1277 BIT(ADV7182_INPUT_CVBS_AIN4) | 1278 BIT(ADV7182_INPUT_CVBS_AIN7) | 1279 BIT(ADV7182_INPUT_CVBS_AIN8) | 1280 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1281 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1282 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1283 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1284 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1285 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1286 .init = adv7182_init, 1287 .set_std = adv7182_set_std, 1288 .select_input = adv7182_select_input, 1289 }; 1290 1291 static int init_device(struct adv7180_state *state) 1292 { 1293 int ret; 1294 1295 mutex_lock(&state->mutex); 1296 1297 adv7180_set_power_pin(state, true); 1298 adv7180_set_reset_pin(state, false); 1299 1300 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1301 usleep_range(5000, 10000); 1302 1303 ret = state->chip_info->init(state); 1304 if (ret) 1305 goto out_unlock; 1306 1307 ret = adv7180_program_std(state); 1308 if (ret) 1309 goto out_unlock; 1310 1311 adv7180_set_field_mode(state); 1312 1313 /* register for interrupts */ 1314 if (state->irq > 0) { 1315 /* config the Interrupt pin to be active low */ 1316 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1317 ADV7180_ICONF1_ACTIVE_LOW | 1318 ADV7180_ICONF1_PSYNC_ONLY); 1319 if (ret < 0) 1320 goto out_unlock; 1321 1322 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1323 if (ret < 0) 1324 goto out_unlock; 1325 1326 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1327 if (ret < 0) 1328 goto out_unlock; 1329 1330 /* enable AD change interrupts interrupts */ 1331 ret = adv7180_write(state, ADV7180_REG_IMR3, 1332 ADV7180_IRQ3_AD_CHANGE); 1333 if (ret < 0) 1334 goto out_unlock; 1335 1336 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1337 if (ret < 0) 1338 goto out_unlock; 1339 } 1340 1341 out_unlock: 1342 mutex_unlock(&state->mutex); 1343 1344 return ret; 1345 } 1346 1347 static int adv7180_probe(struct i2c_client *client, 1348 const struct i2c_device_id *id) 1349 { 1350 struct device_node *np = client->dev.of_node; 1351 struct adv7180_state *state; 1352 struct v4l2_subdev *sd; 1353 int ret; 1354 1355 /* Check if the adapter supports the needed features */ 1356 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1357 return -EIO; 1358 1359 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1360 if (state == NULL) 1361 return -ENOMEM; 1362 1363 state->client = client; 1364 state->field = V4L2_FIELD_ALTERNATE; 1365 state->chip_info = (struct adv7180_chip_info *)id->driver_data; 1366 1367 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1368 GPIOD_OUT_HIGH); 1369 if (IS_ERR(state->pwdn_gpio)) { 1370 ret = PTR_ERR(state->pwdn_gpio); 1371 v4l_err(client, "request for power pin failed: %d\n", ret); 1372 return ret; 1373 } 1374 1375 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset", 1376 GPIOD_OUT_HIGH); 1377 if (IS_ERR(state->rst_gpio)) { 1378 ret = PTR_ERR(state->rst_gpio); 1379 v4l_err(client, "request for reset pin failed: %d\n", ret); 1380 return ret; 1381 } 1382 1383 if (of_property_read_bool(np, "adv,force-bt656-4")) 1384 state->force_bt656_4 = true; 1385 1386 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1387 state->csi_client = i2c_new_dummy_device(client->adapter, 1388 ADV7180_DEFAULT_CSI_I2C_ADDR); 1389 if (IS_ERR(state->csi_client)) 1390 return PTR_ERR(state->csi_client); 1391 } 1392 1393 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1394 state->vpp_client = i2c_new_dummy_device(client->adapter, 1395 ADV7180_DEFAULT_VPP_I2C_ADDR); 1396 if (IS_ERR(state->vpp_client)) { 1397 ret = PTR_ERR(state->vpp_client); 1398 goto err_unregister_csi_client; 1399 } 1400 } 1401 1402 state->irq = client->irq; 1403 mutex_init(&state->mutex); 1404 state->curr_norm = V4L2_STD_NTSC; 1405 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1406 state->powered = true; 1407 else 1408 state->powered = false; 1409 state->input = 0; 1410 sd = &state->sd; 1411 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1412 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1413 1414 ret = adv7180_init_controls(state); 1415 if (ret) 1416 goto err_unregister_vpp_client; 1417 1418 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1419 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1420 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1421 if (ret) 1422 goto err_free_ctrl; 1423 1424 ret = init_device(state); 1425 if (ret) 1426 goto err_media_entity_cleanup; 1427 1428 if (state->irq) { 1429 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1430 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1431 KBUILD_MODNAME, state); 1432 if (ret) 1433 goto err_media_entity_cleanup; 1434 } 1435 1436 ret = v4l2_async_register_subdev(sd); 1437 if (ret) 1438 goto err_free_irq; 1439 1440 mutex_lock(&state->mutex); 1441 ret = adv7180_read(state, ADV7180_REG_IDENT); 1442 mutex_unlock(&state->mutex); 1443 if (ret < 0) 1444 goto err_v4l2_async_unregister; 1445 1446 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n", 1447 ret, client->addr, client->adapter->name); 1448 1449 return 0; 1450 1451 err_v4l2_async_unregister: 1452 v4l2_async_unregister_subdev(sd); 1453 err_free_irq: 1454 if (state->irq > 0) 1455 free_irq(client->irq, state); 1456 err_media_entity_cleanup: 1457 media_entity_cleanup(&sd->entity); 1458 err_free_ctrl: 1459 adv7180_exit_controls(state); 1460 err_unregister_vpp_client: 1461 i2c_unregister_device(state->vpp_client); 1462 err_unregister_csi_client: 1463 i2c_unregister_device(state->csi_client); 1464 mutex_destroy(&state->mutex); 1465 return ret; 1466 } 1467 1468 static int adv7180_remove(struct i2c_client *client) 1469 { 1470 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1471 struct adv7180_state *state = to_state(sd); 1472 1473 v4l2_async_unregister_subdev(sd); 1474 1475 if (state->irq > 0) 1476 free_irq(client->irq, state); 1477 1478 media_entity_cleanup(&sd->entity); 1479 adv7180_exit_controls(state); 1480 1481 i2c_unregister_device(state->vpp_client); 1482 i2c_unregister_device(state->csi_client); 1483 1484 adv7180_set_reset_pin(state, true); 1485 adv7180_set_power_pin(state, false); 1486 1487 mutex_destroy(&state->mutex); 1488 1489 return 0; 1490 } 1491 1492 static const struct i2c_device_id adv7180_id[] = { 1493 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1494 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1495 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1496 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1497 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1498 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1499 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1500 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1501 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1502 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1503 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1504 {}, 1505 }; 1506 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1507 1508 #ifdef CONFIG_PM_SLEEP 1509 static int adv7180_suspend(struct device *dev) 1510 { 1511 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1512 struct adv7180_state *state = to_state(sd); 1513 1514 return adv7180_set_power(state, false); 1515 } 1516 1517 static int adv7180_resume(struct device *dev) 1518 { 1519 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1520 struct adv7180_state *state = to_state(sd); 1521 int ret; 1522 1523 ret = init_device(state); 1524 if (ret < 0) 1525 return ret; 1526 1527 ret = adv7180_set_power(state, state->powered); 1528 if (ret) 1529 return ret; 1530 1531 return 0; 1532 } 1533 1534 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1535 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1536 1537 #else 1538 #define ADV7180_PM_OPS NULL 1539 #endif 1540 1541 #ifdef CONFIG_OF 1542 static const struct of_device_id adv7180_of_id[] = { 1543 { .compatible = "adi,adv7180", }, 1544 { .compatible = "adi,adv7180cp", }, 1545 { .compatible = "adi,adv7180st", }, 1546 { .compatible = "adi,adv7182", }, 1547 { .compatible = "adi,adv7280", }, 1548 { .compatible = "adi,adv7280-m", }, 1549 { .compatible = "adi,adv7281", }, 1550 { .compatible = "adi,adv7281-m", }, 1551 { .compatible = "adi,adv7281-ma", }, 1552 { .compatible = "adi,adv7282", }, 1553 { .compatible = "adi,adv7282-m", }, 1554 { }, 1555 }; 1556 1557 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1558 #endif 1559 1560 static struct i2c_driver adv7180_driver = { 1561 .driver = { 1562 .name = KBUILD_MODNAME, 1563 .pm = ADV7180_PM_OPS, 1564 .of_match_table = of_match_ptr(adv7180_of_id), 1565 }, 1566 .probe = adv7180_probe, 1567 .remove = adv7180_remove, 1568 .id_table = adv7180_id, 1569 }; 1570 1571 module_i2c_driver(adv7180_driver); 1572 1573 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1574 MODULE_AUTHOR("Mocean Laboratories"); 1575 MODULE_LICENSE("GPL v2"); 1576