1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * adv7180.c Analog Devices ADV7180 video decoder driver 4 * Copyright (c) 2009 Intel Corporation 5 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Renesas Solutions Corp. 7 */ 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/interrupt.h> 13 #include <linux/i2c.h> 14 #include <linux/slab.h> 15 #include <linux/of.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/videodev2.h> 18 #include <media/v4l2-ioctl.h> 19 #include <media/v4l2-event.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ctrls.h> 22 #include <linux/mutex.h> 23 #include <linux/delay.h> 24 25 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0 26 #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1 27 #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2 28 #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3 29 #define ADV7180_STD_NTSC_J 0x4 30 #define ADV7180_STD_NTSC_M 0x5 31 #define ADV7180_STD_PAL60 0x6 32 #define ADV7180_STD_NTSC_443 0x7 33 #define ADV7180_STD_PAL_BG 0x8 34 #define ADV7180_STD_PAL_N 0x9 35 #define ADV7180_STD_PAL_M 0xa 36 #define ADV7180_STD_PAL_M_PED 0xb 37 #define ADV7180_STD_PAL_COMB_N 0xc 38 #define ADV7180_STD_PAL_COMB_N_PED 0xd 39 #define ADV7180_STD_PAL_SECAM 0xe 40 #define ADV7180_STD_PAL_SECAM_PED 0xf 41 42 #define ADV7180_REG_INPUT_CONTROL 0x0000 43 #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f 44 45 #define ADV7182_REG_INPUT_VIDSEL 0x0002 46 47 #define ADV7180_REG_OUTPUT_CONTROL 0x0003 48 #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004 49 #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 50 51 #define ADV7180_REG_AUTODETECT_ENABLE 0x0007 52 #define ADV7180_AUTODETECT_DEFAULT 0x7f 53 /* Contrast */ 54 #define ADV7180_REG_CON 0x0008 /*Unsigned */ 55 #define ADV7180_CON_MIN 0 56 #define ADV7180_CON_DEF 128 57 #define ADV7180_CON_MAX 255 58 /* Brightness*/ 59 #define ADV7180_REG_BRI 0x000a /*Signed */ 60 #define ADV7180_BRI_MIN -128 61 #define ADV7180_BRI_DEF 0 62 #define ADV7180_BRI_MAX 127 63 /* Hue */ 64 #define ADV7180_REG_HUE 0x000b /*Signed, inverted */ 65 #define ADV7180_HUE_MIN -127 66 #define ADV7180_HUE_DEF 0 67 #define ADV7180_HUE_MAX 128 68 69 #define ADV7180_REG_CTRL 0x000e 70 #define ADV7180_CTRL_IRQ_SPACE 0x20 71 72 #define ADV7180_REG_PWR_MAN 0x0f 73 #define ADV7180_PWR_MAN_ON 0x04 74 #define ADV7180_PWR_MAN_OFF 0x24 75 #define ADV7180_PWR_MAN_RES 0x80 76 77 #define ADV7180_REG_STATUS1 0x0010 78 #define ADV7180_STATUS1_IN_LOCK 0x01 79 #define ADV7180_STATUS1_AUTOD_MASK 0x70 80 #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00 81 #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10 82 #define ADV7180_STATUS1_AUTOD_PAL_M 0x20 83 #define ADV7180_STATUS1_AUTOD_PAL_60 0x30 84 #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40 85 #define ADV7180_STATUS1_AUTOD_SECAM 0x50 86 #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60 87 #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70 88 89 #define ADV7180_REG_IDENT 0x0011 90 #define ADV7180_ID_7180 0x18 91 92 #define ADV7180_REG_STATUS3 0x0013 93 #define ADV7180_REG_ANALOG_CLAMP_CTL 0x0014 94 #define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017 95 #define ADV7180_REG_CTRL_2 0x001d 96 #define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031 97 #define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d 98 #define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e 99 #define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f 100 #define ADV7180_REG_LOCK_CNT 0x0051 101 #define ADV7180_REG_CVBS_TRIM 0x0052 102 #define ADV7180_REG_CLAMP_ADJ 0x005a 103 #define ADV7180_REG_RES_CIR 0x005f 104 #define ADV7180_REG_DIFF_MODE 0x0060 105 106 #define ADV7180_REG_ICONF1 0x2040 107 #define ADV7180_ICONF1_ACTIVE_LOW 0x01 108 #define ADV7180_ICONF1_PSYNC_ONLY 0x10 109 #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0 110 /* Saturation */ 111 #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */ 112 #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */ 113 #define ADV7180_SAT_MIN 0 114 #define ADV7180_SAT_DEF 128 115 #define ADV7180_SAT_MAX 255 116 117 #define ADV7180_IRQ1_LOCK 0x01 118 #define ADV7180_IRQ1_UNLOCK 0x02 119 #define ADV7180_REG_ISR1 0x2042 120 #define ADV7180_REG_ICR1 0x2043 121 #define ADV7180_REG_IMR1 0x2044 122 #define ADV7180_REG_IMR2 0x2048 123 #define ADV7180_IRQ3_AD_CHANGE 0x08 124 #define ADV7180_REG_ISR3 0x204A 125 #define ADV7180_REG_ICR3 0x204B 126 #define ADV7180_REG_IMR3 0x204C 127 #define ADV7180_REG_IMR4 0x2050 128 129 #define ADV7180_REG_NTSC_V_BIT_END 0x00E6 130 #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F 131 132 #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD 133 #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE 134 135 #define ADV7180_REG_ACE_CTRL1 0x4080 136 #define ADV7180_REG_ACE_CTRL5 0x4084 137 #define ADV7180_REG_FLCONTROL 0x40e0 138 #define ADV7180_FLCONTROL_FL_ENABLE 0x1 139 140 #define ADV7180_REG_RST_CLAMP 0x809c 141 #define ADV7180_REG_AGC_ADJ1 0x80b6 142 #define ADV7180_REG_AGC_ADJ2 0x80c0 143 144 #define ADV7180_CSI_REG_PWRDN 0x00 145 #define ADV7180_CSI_PWRDN 0x80 146 147 #define ADV7180_INPUT_CVBS_AIN1 0x00 148 #define ADV7180_INPUT_CVBS_AIN2 0x01 149 #define ADV7180_INPUT_CVBS_AIN3 0x02 150 #define ADV7180_INPUT_CVBS_AIN4 0x03 151 #define ADV7180_INPUT_CVBS_AIN5 0x04 152 #define ADV7180_INPUT_CVBS_AIN6 0x05 153 #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06 154 #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07 155 #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08 156 #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09 157 #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a 158 159 #define ADV7182_INPUT_CVBS_AIN1 0x00 160 #define ADV7182_INPUT_CVBS_AIN2 0x01 161 #define ADV7182_INPUT_CVBS_AIN3 0x02 162 #define ADV7182_INPUT_CVBS_AIN4 0x03 163 #define ADV7182_INPUT_CVBS_AIN5 0x04 164 #define ADV7182_INPUT_CVBS_AIN6 0x05 165 #define ADV7182_INPUT_CVBS_AIN7 0x06 166 #define ADV7182_INPUT_CVBS_AIN8 0x07 167 #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08 168 #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09 169 #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a 170 #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b 171 #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c 172 #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d 173 #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e 174 #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f 175 #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10 176 #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11 177 178 #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44 179 #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42 180 181 #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00) 182 183 struct adv7180_state; 184 185 #define ADV7180_FLAG_RESET_POWERED BIT(0) 186 #define ADV7180_FLAG_V2 BIT(1) 187 #define ADV7180_FLAG_MIPI_CSI2 BIT(2) 188 #define ADV7180_FLAG_I2P BIT(3) 189 190 struct adv7180_chip_info { 191 unsigned int flags; 192 unsigned int valid_input_mask; 193 int (*set_std)(struct adv7180_state *st, unsigned int std); 194 int (*select_input)(struct adv7180_state *st, unsigned int input); 195 int (*init)(struct adv7180_state *state); 196 }; 197 198 struct adv7180_state { 199 struct v4l2_ctrl_handler ctrl_hdl; 200 struct v4l2_subdev sd; 201 struct media_pad pad; 202 struct mutex mutex; /* mutual excl. when accessing chip */ 203 int irq; 204 struct gpio_desc *pwdn_gpio; 205 v4l2_std_id curr_norm; 206 bool powered; 207 bool streaming; 208 u8 input; 209 210 struct i2c_client *client; 211 unsigned int register_page; 212 struct i2c_client *csi_client; 213 struct i2c_client *vpp_client; 214 const struct adv7180_chip_info *chip_info; 215 enum v4l2_field field; 216 }; 217 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \ 218 struct adv7180_state, \ 219 ctrl_hdl)->sd) 220 221 static int adv7180_select_page(struct adv7180_state *state, unsigned int page) 222 { 223 if (state->register_page != page) { 224 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL, 225 page); 226 state->register_page = page; 227 } 228 229 return 0; 230 } 231 232 static int adv7180_write(struct adv7180_state *state, unsigned int reg, 233 unsigned int value) 234 { 235 lockdep_assert_held(&state->mutex); 236 adv7180_select_page(state, reg >> 8); 237 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); 238 } 239 240 static int adv7180_read(struct adv7180_state *state, unsigned int reg) 241 { 242 lockdep_assert_held(&state->mutex); 243 adv7180_select_page(state, reg >> 8); 244 return i2c_smbus_read_byte_data(state->client, reg & 0xff); 245 } 246 247 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, 248 unsigned int value) 249 { 250 return i2c_smbus_write_byte_data(state->csi_client, reg, value); 251 } 252 253 static int adv7180_set_video_standard(struct adv7180_state *state, 254 unsigned int std) 255 { 256 return state->chip_info->set_std(state, std); 257 } 258 259 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, 260 unsigned int value) 261 { 262 return i2c_smbus_write_byte_data(state->vpp_client, reg, value); 263 } 264 265 static v4l2_std_id adv7180_std_to_v4l2(u8 status1) 266 { 267 /* in case V4L2_IN_ST_NO_SIGNAL */ 268 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 269 return V4L2_STD_UNKNOWN; 270 271 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) { 272 case ADV7180_STATUS1_AUTOD_NTSM_M_J: 273 return V4L2_STD_NTSC; 274 case ADV7180_STATUS1_AUTOD_NTSC_4_43: 275 return V4L2_STD_NTSC_443; 276 case ADV7180_STATUS1_AUTOD_PAL_M: 277 return V4L2_STD_PAL_M; 278 case ADV7180_STATUS1_AUTOD_PAL_60: 279 return V4L2_STD_PAL_60; 280 case ADV7180_STATUS1_AUTOD_PAL_B_G: 281 return V4L2_STD_PAL; 282 case ADV7180_STATUS1_AUTOD_SECAM: 283 return V4L2_STD_SECAM; 284 case ADV7180_STATUS1_AUTOD_PAL_COMB: 285 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N; 286 case ADV7180_STATUS1_AUTOD_SECAM_525: 287 return V4L2_STD_SECAM; 288 default: 289 return V4L2_STD_UNKNOWN; 290 } 291 } 292 293 static int v4l2_std_to_adv7180(v4l2_std_id std) 294 { 295 if (std == V4L2_STD_PAL_60) 296 return ADV7180_STD_PAL60; 297 if (std == V4L2_STD_NTSC_443) 298 return ADV7180_STD_NTSC_443; 299 if (std == V4L2_STD_PAL_N) 300 return ADV7180_STD_PAL_N; 301 if (std == V4L2_STD_PAL_M) 302 return ADV7180_STD_PAL_M; 303 if (std == V4L2_STD_PAL_Nc) 304 return ADV7180_STD_PAL_COMB_N; 305 306 if (std & V4L2_STD_PAL) 307 return ADV7180_STD_PAL_BG; 308 if (std & V4L2_STD_NTSC) 309 return ADV7180_STD_NTSC_M; 310 if (std & V4L2_STD_SECAM) 311 return ADV7180_STD_PAL_SECAM; 312 313 return -EINVAL; 314 } 315 316 static u32 adv7180_status_to_v4l2(u8 status1) 317 { 318 if (!(status1 & ADV7180_STATUS1_IN_LOCK)) 319 return V4L2_IN_ST_NO_SIGNAL; 320 321 return 0; 322 } 323 324 static int __adv7180_status(struct adv7180_state *state, u32 *status, 325 v4l2_std_id *std) 326 { 327 int status1 = adv7180_read(state, ADV7180_REG_STATUS1); 328 329 if (status1 < 0) 330 return status1; 331 332 if (status) 333 *status = adv7180_status_to_v4l2(status1); 334 if (std) 335 *std = adv7180_std_to_v4l2(status1); 336 337 return 0; 338 } 339 340 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd) 341 { 342 return container_of(sd, struct adv7180_state, sd); 343 } 344 345 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) 346 { 347 struct adv7180_state *state = to_state(sd); 348 int err = mutex_lock_interruptible(&state->mutex); 349 if (err) 350 return err; 351 352 if (state->streaming) { 353 err = -EBUSY; 354 goto unlock; 355 } 356 357 err = adv7180_set_video_standard(state, 358 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM); 359 if (err) 360 goto unlock; 361 362 msleep(100); 363 __adv7180_status(state, NULL, std); 364 365 err = v4l2_std_to_adv7180(state->curr_norm); 366 if (err < 0) 367 goto unlock; 368 369 err = adv7180_set_video_standard(state, err); 370 371 unlock: 372 mutex_unlock(&state->mutex); 373 return err; 374 } 375 376 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input, 377 u32 output, u32 config) 378 { 379 struct adv7180_state *state = to_state(sd); 380 int ret = mutex_lock_interruptible(&state->mutex); 381 382 if (ret) 383 return ret; 384 385 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { 386 ret = -EINVAL; 387 goto out; 388 } 389 390 ret = state->chip_info->select_input(state, input); 391 392 if (ret == 0) 393 state->input = input; 394 out: 395 mutex_unlock(&state->mutex); 396 return ret; 397 } 398 399 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status) 400 { 401 struct adv7180_state *state = to_state(sd); 402 int ret = mutex_lock_interruptible(&state->mutex); 403 if (ret) 404 return ret; 405 406 ret = __adv7180_status(state, status, NULL); 407 mutex_unlock(&state->mutex); 408 return ret; 409 } 410 411 static int adv7180_program_std(struct adv7180_state *state) 412 { 413 int ret; 414 415 ret = v4l2_std_to_adv7180(state->curr_norm); 416 if (ret < 0) 417 return ret; 418 419 ret = adv7180_set_video_standard(state, ret); 420 if (ret < 0) 421 return ret; 422 return 0; 423 } 424 425 static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std) 426 { 427 struct adv7180_state *state = to_state(sd); 428 int ret = mutex_lock_interruptible(&state->mutex); 429 430 if (ret) 431 return ret; 432 433 /* Make sure we can support this std */ 434 ret = v4l2_std_to_adv7180(std); 435 if (ret < 0) 436 goto out; 437 438 state->curr_norm = std; 439 440 ret = adv7180_program_std(state); 441 out: 442 mutex_unlock(&state->mutex); 443 return ret; 444 } 445 446 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm) 447 { 448 struct adv7180_state *state = to_state(sd); 449 450 *norm = state->curr_norm; 451 452 return 0; 453 } 454 455 static int adv7180_g_frame_interval(struct v4l2_subdev *sd, 456 struct v4l2_subdev_frame_interval *fi) 457 { 458 struct adv7180_state *state = to_state(sd); 459 460 if (state->curr_norm & V4L2_STD_525_60) { 461 fi->interval.numerator = 1001; 462 fi->interval.denominator = 30000; 463 } else { 464 fi->interval.numerator = 1; 465 fi->interval.denominator = 25; 466 } 467 468 return 0; 469 } 470 471 static void adv7180_set_power_pin(struct adv7180_state *state, bool on) 472 { 473 if (!state->pwdn_gpio) 474 return; 475 476 if (on) { 477 gpiod_set_value_cansleep(state->pwdn_gpio, 0); 478 usleep_range(5000, 10000); 479 } else { 480 gpiod_set_value_cansleep(state->pwdn_gpio, 1); 481 } 482 } 483 484 static int adv7180_set_power(struct adv7180_state *state, bool on) 485 { 486 u8 val; 487 int ret; 488 489 if (on) 490 val = ADV7180_PWR_MAN_ON; 491 else 492 val = ADV7180_PWR_MAN_OFF; 493 494 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val); 495 if (ret) 496 return ret; 497 498 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 499 if (on) { 500 adv7180_csi_write(state, 0xDE, 0x02); 501 adv7180_csi_write(state, 0xD2, 0xF7); 502 adv7180_csi_write(state, 0xD8, 0x65); 503 adv7180_csi_write(state, 0xE0, 0x09); 504 adv7180_csi_write(state, 0x2C, 0x00); 505 if (state->field == V4L2_FIELD_NONE) 506 adv7180_csi_write(state, 0x1D, 0x80); 507 adv7180_csi_write(state, 0x00, 0x00); 508 } else { 509 adv7180_csi_write(state, 0x00, 0x80); 510 } 511 } 512 513 return 0; 514 } 515 516 static int adv7180_s_power(struct v4l2_subdev *sd, int on) 517 { 518 struct adv7180_state *state = to_state(sd); 519 int ret; 520 521 ret = mutex_lock_interruptible(&state->mutex); 522 if (ret) 523 return ret; 524 525 ret = adv7180_set_power(state, on); 526 if (ret == 0) 527 state->powered = on; 528 529 mutex_unlock(&state->mutex); 530 return ret; 531 } 532 533 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl) 534 { 535 struct v4l2_subdev *sd = to_adv7180_sd(ctrl); 536 struct adv7180_state *state = to_state(sd); 537 int ret = mutex_lock_interruptible(&state->mutex); 538 int val; 539 540 if (ret) 541 return ret; 542 val = ctrl->val; 543 switch (ctrl->id) { 544 case V4L2_CID_BRIGHTNESS: 545 ret = adv7180_write(state, ADV7180_REG_BRI, val); 546 break; 547 case V4L2_CID_HUE: 548 /*Hue is inverted according to HSL chart */ 549 ret = adv7180_write(state, ADV7180_REG_HUE, -val); 550 break; 551 case V4L2_CID_CONTRAST: 552 ret = adv7180_write(state, ADV7180_REG_CON, val); 553 break; 554 case V4L2_CID_SATURATION: 555 /* 556 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE 557 *Let's not confuse the user, everybody understands saturation 558 */ 559 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val); 560 if (ret < 0) 561 break; 562 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val); 563 break; 564 case V4L2_CID_ADV_FAST_SWITCH: 565 if (ctrl->val) { 566 /* ADI required write */ 567 adv7180_write(state, 0x80d9, 0x44); 568 adv7180_write(state, ADV7180_REG_FLCONTROL, 569 ADV7180_FLCONTROL_FL_ENABLE); 570 } else { 571 /* ADI required write */ 572 adv7180_write(state, 0x80d9, 0xc4); 573 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00); 574 } 575 break; 576 default: 577 ret = -EINVAL; 578 } 579 580 mutex_unlock(&state->mutex); 581 return ret; 582 } 583 584 static const struct v4l2_ctrl_ops adv7180_ctrl_ops = { 585 .s_ctrl = adv7180_s_ctrl, 586 }; 587 588 static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = { 589 .ops = &adv7180_ctrl_ops, 590 .id = V4L2_CID_ADV_FAST_SWITCH, 591 .name = "Fast Switching", 592 .type = V4L2_CTRL_TYPE_BOOLEAN, 593 .min = 0, 594 .max = 1, 595 .step = 1, 596 }; 597 598 static int adv7180_init_controls(struct adv7180_state *state) 599 { 600 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4); 601 602 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 603 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN, 604 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF); 605 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 606 V4L2_CID_CONTRAST, ADV7180_CON_MIN, 607 ADV7180_CON_MAX, 1, ADV7180_CON_DEF); 608 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 609 V4L2_CID_SATURATION, ADV7180_SAT_MIN, 610 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF); 611 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops, 612 V4L2_CID_HUE, ADV7180_HUE_MIN, 613 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF); 614 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL); 615 616 state->sd.ctrl_handler = &state->ctrl_hdl; 617 if (state->ctrl_hdl.error) { 618 int err = state->ctrl_hdl.error; 619 620 v4l2_ctrl_handler_free(&state->ctrl_hdl); 621 return err; 622 } 623 v4l2_ctrl_handler_setup(&state->ctrl_hdl); 624 625 return 0; 626 } 627 static void adv7180_exit_controls(struct adv7180_state *state) 628 { 629 v4l2_ctrl_handler_free(&state->ctrl_hdl); 630 } 631 632 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd, 633 struct v4l2_subdev_pad_config *cfg, 634 struct v4l2_subdev_mbus_code_enum *code) 635 { 636 if (code->index != 0) 637 return -EINVAL; 638 639 code->code = MEDIA_BUS_FMT_UYVY8_2X8; 640 641 return 0; 642 } 643 644 static int adv7180_mbus_fmt(struct v4l2_subdev *sd, 645 struct v4l2_mbus_framefmt *fmt) 646 { 647 struct adv7180_state *state = to_state(sd); 648 649 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 650 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; 651 fmt->width = 720; 652 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576; 653 654 if (state->field == V4L2_FIELD_ALTERNATE) 655 fmt->height /= 2; 656 657 return 0; 658 } 659 660 static int adv7180_set_field_mode(struct adv7180_state *state) 661 { 662 if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) 663 return 0; 664 665 if (state->field == V4L2_FIELD_NONE) { 666 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 667 adv7180_csi_write(state, 0x01, 0x20); 668 adv7180_csi_write(state, 0x02, 0x28); 669 adv7180_csi_write(state, 0x03, 0x38); 670 adv7180_csi_write(state, 0x04, 0x30); 671 adv7180_csi_write(state, 0x05, 0x30); 672 adv7180_csi_write(state, 0x06, 0x80); 673 adv7180_csi_write(state, 0x07, 0x70); 674 adv7180_csi_write(state, 0x08, 0x50); 675 } 676 adv7180_vpp_write(state, 0xa3, 0x00); 677 adv7180_vpp_write(state, 0x5b, 0x00); 678 adv7180_vpp_write(state, 0x55, 0x80); 679 } else { 680 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 681 adv7180_csi_write(state, 0x01, 0x18); 682 adv7180_csi_write(state, 0x02, 0x18); 683 adv7180_csi_write(state, 0x03, 0x30); 684 adv7180_csi_write(state, 0x04, 0x20); 685 adv7180_csi_write(state, 0x05, 0x28); 686 adv7180_csi_write(state, 0x06, 0x40); 687 adv7180_csi_write(state, 0x07, 0x58); 688 adv7180_csi_write(state, 0x08, 0x30); 689 } 690 adv7180_vpp_write(state, 0xa3, 0x70); 691 adv7180_vpp_write(state, 0x5b, 0x80); 692 adv7180_vpp_write(state, 0x55, 0x00); 693 } 694 695 return 0; 696 } 697 698 static int adv7180_get_pad_format(struct v4l2_subdev *sd, 699 struct v4l2_subdev_pad_config *cfg, 700 struct v4l2_subdev_format *format) 701 { 702 struct adv7180_state *state = to_state(sd); 703 704 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 705 format->format = *v4l2_subdev_get_try_format(sd, cfg, 0); 706 } else { 707 adv7180_mbus_fmt(sd, &format->format); 708 format->format.field = state->field; 709 } 710 711 return 0; 712 } 713 714 static int adv7180_set_pad_format(struct v4l2_subdev *sd, 715 struct v4l2_subdev_pad_config *cfg, 716 struct v4l2_subdev_format *format) 717 { 718 struct adv7180_state *state = to_state(sd); 719 struct v4l2_mbus_framefmt *framefmt; 720 int ret; 721 722 switch (format->format.field) { 723 case V4L2_FIELD_NONE: 724 if (state->chip_info->flags & ADV7180_FLAG_I2P) 725 break; 726 /* fall through */ 727 default: 728 format->format.field = V4L2_FIELD_ALTERNATE; 729 break; 730 } 731 732 ret = adv7180_mbus_fmt(sd, &format->format); 733 734 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 735 if (state->field != format->format.field) { 736 state->field = format->format.field; 737 adv7180_set_power(state, false); 738 adv7180_set_field_mode(state); 739 adv7180_set_power(state, true); 740 } 741 } else { 742 framefmt = v4l2_subdev_get_try_format(sd, cfg, 0); 743 *framefmt = format->format; 744 } 745 746 return ret; 747 } 748 749 static int adv7180_g_mbus_config(struct v4l2_subdev *sd, 750 struct v4l2_mbus_config *cfg) 751 { 752 struct adv7180_state *state = to_state(sd); 753 754 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 755 cfg->type = V4L2_MBUS_CSI2_DPHY; 756 cfg->flags = V4L2_MBUS_CSI2_1_LANE | 757 V4L2_MBUS_CSI2_CHANNEL_0 | 758 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK; 759 } else { 760 /* 761 * The ADV7180 sensor supports BT.601/656 output modes. 762 * The BT.656 is default and not yet configurable by s/w. 763 */ 764 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING | 765 V4L2_MBUS_DATA_ACTIVE_HIGH; 766 cfg->type = V4L2_MBUS_BT656; 767 } 768 769 return 0; 770 } 771 772 static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect) 773 { 774 struct adv7180_state *state = to_state(sd); 775 776 if (state->curr_norm & V4L2_STD_525_60) { 777 aspect->numerator = 11; 778 aspect->denominator = 10; 779 } else { 780 aspect->numerator = 54; 781 aspect->denominator = 59; 782 } 783 784 return 0; 785 } 786 787 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm) 788 { 789 *norm = V4L2_STD_ALL; 790 return 0; 791 } 792 793 static int adv7180_s_stream(struct v4l2_subdev *sd, int enable) 794 { 795 struct adv7180_state *state = to_state(sd); 796 int ret; 797 798 /* It's always safe to stop streaming, no need to take the lock */ 799 if (!enable) { 800 state->streaming = enable; 801 return 0; 802 } 803 804 /* Must wait until querystd released the lock */ 805 ret = mutex_lock_interruptible(&state->mutex); 806 if (ret) 807 return ret; 808 state->streaming = enable; 809 mutex_unlock(&state->mutex); 810 return 0; 811 } 812 813 static int adv7180_subscribe_event(struct v4l2_subdev *sd, 814 struct v4l2_fh *fh, 815 struct v4l2_event_subscription *sub) 816 { 817 switch (sub->type) { 818 case V4L2_EVENT_SOURCE_CHANGE: 819 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); 820 case V4L2_EVENT_CTRL: 821 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); 822 default: 823 return -EINVAL; 824 } 825 } 826 827 static const struct v4l2_subdev_video_ops adv7180_video_ops = { 828 .s_std = adv7180_s_std, 829 .g_std = adv7180_g_std, 830 .g_frame_interval = adv7180_g_frame_interval, 831 .querystd = adv7180_querystd, 832 .g_input_status = adv7180_g_input_status, 833 .s_routing = adv7180_s_routing, 834 .g_mbus_config = adv7180_g_mbus_config, 835 .g_pixelaspect = adv7180_g_pixelaspect, 836 .g_tvnorms = adv7180_g_tvnorms, 837 .s_stream = adv7180_s_stream, 838 }; 839 840 static const struct v4l2_subdev_core_ops adv7180_core_ops = { 841 .s_power = adv7180_s_power, 842 .subscribe_event = adv7180_subscribe_event, 843 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 844 }; 845 846 static const struct v4l2_subdev_pad_ops adv7180_pad_ops = { 847 .enum_mbus_code = adv7180_enum_mbus_code, 848 .set_fmt = adv7180_set_pad_format, 849 .get_fmt = adv7180_get_pad_format, 850 }; 851 852 static const struct v4l2_subdev_ops adv7180_ops = { 853 .core = &adv7180_core_ops, 854 .video = &adv7180_video_ops, 855 .pad = &adv7180_pad_ops, 856 }; 857 858 static irqreturn_t adv7180_irq(int irq, void *devid) 859 { 860 struct adv7180_state *state = devid; 861 u8 isr3; 862 863 mutex_lock(&state->mutex); 864 isr3 = adv7180_read(state, ADV7180_REG_ISR3); 865 /* clear */ 866 adv7180_write(state, ADV7180_REG_ICR3, isr3); 867 868 if (isr3 & ADV7180_IRQ3_AD_CHANGE) { 869 static const struct v4l2_event src_ch = { 870 .type = V4L2_EVENT_SOURCE_CHANGE, 871 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, 872 }; 873 874 v4l2_subdev_notify_event(&state->sd, &src_ch); 875 } 876 mutex_unlock(&state->mutex); 877 878 return IRQ_HANDLED; 879 } 880 881 static int adv7180_init(struct adv7180_state *state) 882 { 883 int ret; 884 885 /* ITU-R BT.656-4 compatible */ 886 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 887 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS); 888 if (ret < 0) 889 return ret; 890 891 /* Manually set V bit end position in NTSC mode */ 892 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END, 893 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND); 894 } 895 896 static int adv7180_set_std(struct adv7180_state *state, unsigned int std) 897 { 898 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, 899 (std << 4) | state->input); 900 } 901 902 static int adv7180_select_input(struct adv7180_state *state, unsigned int input) 903 { 904 int ret; 905 906 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL); 907 if (ret < 0) 908 return ret; 909 910 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK; 911 ret |= input; 912 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret); 913 } 914 915 static int adv7182_init(struct adv7180_state *state) 916 { 917 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) 918 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR, 919 ADV7180_DEFAULT_CSI_I2C_ADDR << 1); 920 921 if (state->chip_info->flags & ADV7180_FLAG_I2P) 922 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR, 923 ADV7180_DEFAULT_VPP_I2C_ADDR << 1); 924 925 if (state->chip_info->flags & ADV7180_FLAG_V2) { 926 /* ADI recommended writes for improved video quality */ 927 adv7180_write(state, 0x0080, 0x51); 928 adv7180_write(state, 0x0081, 0x51); 929 adv7180_write(state, 0x0082, 0x68); 930 } 931 932 /* ADI required writes */ 933 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 934 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e); 935 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57); 936 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0); 937 } else { 938 if (state->chip_info->flags & ADV7180_FLAG_V2) 939 adv7180_write(state, 940 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 941 0x17); 942 else 943 adv7180_write(state, 944 ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 945 0x07); 946 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c); 947 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40); 948 } 949 950 adv7180_write(state, 0x0013, 0x00); 951 952 return 0; 953 } 954 955 static int adv7182_set_std(struct adv7180_state *state, unsigned int std) 956 { 957 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4); 958 } 959 960 enum adv7182_input_type { 961 ADV7182_INPUT_TYPE_CVBS, 962 ADV7182_INPUT_TYPE_DIFF_CVBS, 963 ADV7182_INPUT_TYPE_SVIDEO, 964 ADV7182_INPUT_TYPE_YPBPR, 965 }; 966 967 static enum adv7182_input_type adv7182_get_input_type(unsigned int input) 968 { 969 switch (input) { 970 case ADV7182_INPUT_CVBS_AIN1: 971 case ADV7182_INPUT_CVBS_AIN2: 972 case ADV7182_INPUT_CVBS_AIN3: 973 case ADV7182_INPUT_CVBS_AIN4: 974 case ADV7182_INPUT_CVBS_AIN5: 975 case ADV7182_INPUT_CVBS_AIN6: 976 case ADV7182_INPUT_CVBS_AIN7: 977 case ADV7182_INPUT_CVBS_AIN8: 978 return ADV7182_INPUT_TYPE_CVBS; 979 case ADV7182_INPUT_SVIDEO_AIN1_AIN2: 980 case ADV7182_INPUT_SVIDEO_AIN3_AIN4: 981 case ADV7182_INPUT_SVIDEO_AIN5_AIN6: 982 case ADV7182_INPUT_SVIDEO_AIN7_AIN8: 983 return ADV7182_INPUT_TYPE_SVIDEO; 984 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3: 985 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6: 986 return ADV7182_INPUT_TYPE_YPBPR; 987 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2: 988 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4: 989 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6: 990 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8: 991 return ADV7182_INPUT_TYPE_DIFF_CVBS; 992 default: /* Will never happen */ 993 return 0; 994 } 995 } 996 997 /* ADI recommended writes to registers 0x52, 0x53, 0x54 */ 998 static unsigned int adv7182_lbias_settings[][3] = { 999 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 }, 1000 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1001 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1002 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1003 }; 1004 1005 static unsigned int adv7280_lbias_settings[][3] = { 1006 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 }, 1007 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 }, 1008 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 }, 1009 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 }, 1010 }; 1011 1012 static int adv7182_select_input(struct adv7180_state *state, unsigned int input) 1013 { 1014 enum adv7182_input_type input_type; 1015 unsigned int *lbias; 1016 unsigned int i; 1017 int ret; 1018 1019 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input); 1020 if (ret) 1021 return ret; 1022 1023 /* Reset clamp circuitry - ADI recommended writes */ 1024 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00); 1025 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff); 1026 1027 input_type = adv7182_get_input_type(input); 1028 1029 switch (input_type) { 1030 case ADV7182_INPUT_TYPE_CVBS: 1031 case ADV7182_INPUT_TYPE_DIFF_CVBS: 1032 /* ADI recommends to use the SH1 filter */ 1033 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41); 1034 break; 1035 default: 1036 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01); 1037 break; 1038 } 1039 1040 if (state->chip_info->flags & ADV7180_FLAG_V2) 1041 lbias = adv7280_lbias_settings[input_type]; 1042 else 1043 lbias = adv7182_lbias_settings[input_type]; 1044 1045 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++) 1046 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]); 1047 1048 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) { 1049 /* ADI required writes to make differential CVBS work */ 1050 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8); 1051 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90); 1052 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0); 1053 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08); 1054 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0); 1055 } else { 1056 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0); 1057 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0); 1058 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10); 1059 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c); 1060 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00); 1061 } 1062 1063 return 0; 1064 } 1065 1066 static const struct adv7180_chip_info adv7180_info = { 1067 .flags = ADV7180_FLAG_RESET_POWERED, 1068 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept 1069 * all inputs and let the card driver take care of validation 1070 */ 1071 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) | 1072 BIT(ADV7180_INPUT_CVBS_AIN2) | 1073 BIT(ADV7180_INPUT_CVBS_AIN3) | 1074 BIT(ADV7180_INPUT_CVBS_AIN4) | 1075 BIT(ADV7180_INPUT_CVBS_AIN5) | 1076 BIT(ADV7180_INPUT_CVBS_AIN6) | 1077 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) | 1078 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) | 1079 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) | 1080 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1081 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6), 1082 .init = adv7180_init, 1083 .set_std = adv7180_set_std, 1084 .select_input = adv7180_select_input, 1085 }; 1086 1087 static const struct adv7180_chip_info adv7182_info = { 1088 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1089 BIT(ADV7182_INPUT_CVBS_AIN2) | 1090 BIT(ADV7182_INPUT_CVBS_AIN3) | 1091 BIT(ADV7182_INPUT_CVBS_AIN4) | 1092 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1093 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1094 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1095 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1096 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4), 1097 .init = adv7182_init, 1098 .set_std = adv7182_set_std, 1099 .select_input = adv7182_select_input, 1100 }; 1101 1102 static const struct adv7180_chip_info adv7280_info = { 1103 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1104 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1105 BIT(ADV7182_INPUT_CVBS_AIN2) | 1106 BIT(ADV7182_INPUT_CVBS_AIN3) | 1107 BIT(ADV7182_INPUT_CVBS_AIN4) | 1108 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1109 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1110 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3), 1111 .init = adv7182_init, 1112 .set_std = adv7182_set_std, 1113 .select_input = adv7182_select_input, 1114 }; 1115 1116 static const struct adv7180_chip_info adv7280_m_info = { 1117 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1118 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1119 BIT(ADV7182_INPUT_CVBS_AIN2) | 1120 BIT(ADV7182_INPUT_CVBS_AIN3) | 1121 BIT(ADV7182_INPUT_CVBS_AIN4) | 1122 BIT(ADV7182_INPUT_CVBS_AIN5) | 1123 BIT(ADV7182_INPUT_CVBS_AIN6) | 1124 BIT(ADV7182_INPUT_CVBS_AIN7) | 1125 BIT(ADV7182_INPUT_CVBS_AIN8) | 1126 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1127 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1128 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1129 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1130 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1131 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6), 1132 .init = adv7182_init, 1133 .set_std = adv7182_set_std, 1134 .select_input = adv7182_select_input, 1135 }; 1136 1137 static const struct adv7180_chip_info adv7281_info = { 1138 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1139 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1140 BIT(ADV7182_INPUT_CVBS_AIN2) | 1141 BIT(ADV7182_INPUT_CVBS_AIN7) | 1142 BIT(ADV7182_INPUT_CVBS_AIN8) | 1143 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1144 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1145 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1146 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1147 .init = adv7182_init, 1148 .set_std = adv7182_set_std, 1149 .select_input = adv7182_select_input, 1150 }; 1151 1152 static const struct adv7180_chip_info adv7281_m_info = { 1153 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1154 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1155 BIT(ADV7182_INPUT_CVBS_AIN2) | 1156 BIT(ADV7182_INPUT_CVBS_AIN3) | 1157 BIT(ADV7182_INPUT_CVBS_AIN4) | 1158 BIT(ADV7182_INPUT_CVBS_AIN7) | 1159 BIT(ADV7182_INPUT_CVBS_AIN8) | 1160 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1161 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1162 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1163 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1164 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1165 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1166 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1167 .init = adv7182_init, 1168 .set_std = adv7182_set_std, 1169 .select_input = adv7182_select_input, 1170 }; 1171 1172 static const struct adv7180_chip_info adv7281_ma_info = { 1173 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2, 1174 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1175 BIT(ADV7182_INPUT_CVBS_AIN2) | 1176 BIT(ADV7182_INPUT_CVBS_AIN3) | 1177 BIT(ADV7182_INPUT_CVBS_AIN4) | 1178 BIT(ADV7182_INPUT_CVBS_AIN5) | 1179 BIT(ADV7182_INPUT_CVBS_AIN6) | 1180 BIT(ADV7182_INPUT_CVBS_AIN7) | 1181 BIT(ADV7182_INPUT_CVBS_AIN8) | 1182 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1183 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1184 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) | 1185 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1186 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) | 1187 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) | 1188 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1189 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1190 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) | 1191 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1192 .init = adv7182_init, 1193 .set_std = adv7182_set_std, 1194 .select_input = adv7182_select_input, 1195 }; 1196 1197 static const struct adv7180_chip_info adv7282_info = { 1198 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P, 1199 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1200 BIT(ADV7182_INPUT_CVBS_AIN2) | 1201 BIT(ADV7182_INPUT_CVBS_AIN7) | 1202 BIT(ADV7182_INPUT_CVBS_AIN8) | 1203 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1204 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1205 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1206 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1207 .init = adv7182_init, 1208 .set_std = adv7182_set_std, 1209 .select_input = adv7182_select_input, 1210 }; 1211 1212 static const struct adv7180_chip_info adv7282_m_info = { 1213 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P, 1214 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) | 1215 BIT(ADV7182_INPUT_CVBS_AIN2) | 1216 BIT(ADV7182_INPUT_CVBS_AIN3) | 1217 BIT(ADV7182_INPUT_CVBS_AIN4) | 1218 BIT(ADV7182_INPUT_CVBS_AIN7) | 1219 BIT(ADV7182_INPUT_CVBS_AIN8) | 1220 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) | 1221 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) | 1222 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) | 1223 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) | 1224 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) | 1225 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8), 1226 .init = adv7182_init, 1227 .set_std = adv7182_set_std, 1228 .select_input = adv7182_select_input, 1229 }; 1230 1231 static int init_device(struct adv7180_state *state) 1232 { 1233 int ret; 1234 1235 mutex_lock(&state->mutex); 1236 1237 adv7180_set_power_pin(state, true); 1238 1239 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES); 1240 usleep_range(5000, 10000); 1241 1242 ret = state->chip_info->init(state); 1243 if (ret) 1244 goto out_unlock; 1245 1246 ret = adv7180_program_std(state); 1247 if (ret) 1248 goto out_unlock; 1249 1250 adv7180_set_field_mode(state); 1251 1252 /* register for interrupts */ 1253 if (state->irq > 0) { 1254 /* config the Interrupt pin to be active low */ 1255 ret = adv7180_write(state, ADV7180_REG_ICONF1, 1256 ADV7180_ICONF1_ACTIVE_LOW | 1257 ADV7180_ICONF1_PSYNC_ONLY); 1258 if (ret < 0) 1259 goto out_unlock; 1260 1261 ret = adv7180_write(state, ADV7180_REG_IMR1, 0); 1262 if (ret < 0) 1263 goto out_unlock; 1264 1265 ret = adv7180_write(state, ADV7180_REG_IMR2, 0); 1266 if (ret < 0) 1267 goto out_unlock; 1268 1269 /* enable AD change interrupts interrupts */ 1270 ret = adv7180_write(state, ADV7180_REG_IMR3, 1271 ADV7180_IRQ3_AD_CHANGE); 1272 if (ret < 0) 1273 goto out_unlock; 1274 1275 ret = adv7180_write(state, ADV7180_REG_IMR4, 0); 1276 if (ret < 0) 1277 goto out_unlock; 1278 } 1279 1280 out_unlock: 1281 mutex_unlock(&state->mutex); 1282 1283 return ret; 1284 } 1285 1286 static int adv7180_probe(struct i2c_client *client, 1287 const struct i2c_device_id *id) 1288 { 1289 struct adv7180_state *state; 1290 struct v4l2_subdev *sd; 1291 int ret; 1292 1293 /* Check if the adapter supports the needed features */ 1294 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1295 return -EIO; 1296 1297 v4l_info(client, "chip found @ 0x%02x (%s)\n", 1298 client->addr, client->adapter->name); 1299 1300 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 1301 if (state == NULL) 1302 return -ENOMEM; 1303 1304 state->client = client; 1305 state->field = V4L2_FIELD_ALTERNATE; 1306 state->chip_info = (struct adv7180_chip_info *)id->driver_data; 1307 1308 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown", 1309 GPIOD_OUT_HIGH); 1310 if (IS_ERR(state->pwdn_gpio)) { 1311 ret = PTR_ERR(state->pwdn_gpio); 1312 v4l_err(client, "request for power pin failed: %d\n", ret); 1313 return ret; 1314 } 1315 1316 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) { 1317 state->csi_client = i2c_new_dummy(client->adapter, 1318 ADV7180_DEFAULT_CSI_I2C_ADDR); 1319 if (!state->csi_client) 1320 return -ENOMEM; 1321 } 1322 1323 if (state->chip_info->flags & ADV7180_FLAG_I2P) { 1324 state->vpp_client = i2c_new_dummy(client->adapter, 1325 ADV7180_DEFAULT_VPP_I2C_ADDR); 1326 if (!state->vpp_client) { 1327 ret = -ENOMEM; 1328 goto err_unregister_csi_client; 1329 } 1330 } 1331 1332 state->irq = client->irq; 1333 mutex_init(&state->mutex); 1334 state->curr_norm = V4L2_STD_NTSC; 1335 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED) 1336 state->powered = true; 1337 else 1338 state->powered = false; 1339 state->input = 0; 1340 sd = &state->sd; 1341 v4l2_i2c_subdev_init(sd, client, &adv7180_ops); 1342 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1343 1344 ret = adv7180_init_controls(state); 1345 if (ret) 1346 goto err_unregister_vpp_client; 1347 1348 state->pad.flags = MEDIA_PAD_FL_SOURCE; 1349 sd->entity.function = MEDIA_ENT_F_ATV_DECODER; 1350 ret = media_entity_pads_init(&sd->entity, 1, &state->pad); 1351 if (ret) 1352 goto err_free_ctrl; 1353 1354 ret = init_device(state); 1355 if (ret) 1356 goto err_media_entity_cleanup; 1357 1358 if (state->irq) { 1359 ret = request_threaded_irq(client->irq, NULL, adv7180_irq, 1360 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1361 KBUILD_MODNAME, state); 1362 if (ret) 1363 goto err_media_entity_cleanup; 1364 } 1365 1366 ret = v4l2_async_register_subdev(sd); 1367 if (ret) 1368 goto err_free_irq; 1369 1370 return 0; 1371 1372 err_free_irq: 1373 if (state->irq > 0) 1374 free_irq(client->irq, state); 1375 err_media_entity_cleanup: 1376 media_entity_cleanup(&sd->entity); 1377 err_free_ctrl: 1378 adv7180_exit_controls(state); 1379 err_unregister_vpp_client: 1380 i2c_unregister_device(state->vpp_client); 1381 err_unregister_csi_client: 1382 i2c_unregister_device(state->csi_client); 1383 mutex_destroy(&state->mutex); 1384 return ret; 1385 } 1386 1387 static int adv7180_remove(struct i2c_client *client) 1388 { 1389 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1390 struct adv7180_state *state = to_state(sd); 1391 1392 v4l2_async_unregister_subdev(sd); 1393 1394 if (state->irq > 0) 1395 free_irq(client->irq, state); 1396 1397 media_entity_cleanup(&sd->entity); 1398 adv7180_exit_controls(state); 1399 1400 i2c_unregister_device(state->vpp_client); 1401 i2c_unregister_device(state->csi_client); 1402 1403 adv7180_set_power_pin(state, false); 1404 1405 mutex_destroy(&state->mutex); 1406 1407 return 0; 1408 } 1409 1410 static const struct i2c_device_id adv7180_id[] = { 1411 { "adv7180", (kernel_ulong_t)&adv7180_info }, 1412 { "adv7180cp", (kernel_ulong_t)&adv7180_info }, 1413 { "adv7180st", (kernel_ulong_t)&adv7180_info }, 1414 { "adv7182", (kernel_ulong_t)&adv7182_info }, 1415 { "adv7280", (kernel_ulong_t)&adv7280_info }, 1416 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info }, 1417 { "adv7281", (kernel_ulong_t)&adv7281_info }, 1418 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info }, 1419 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info }, 1420 { "adv7282", (kernel_ulong_t)&adv7282_info }, 1421 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info }, 1422 {}, 1423 }; 1424 MODULE_DEVICE_TABLE(i2c, adv7180_id); 1425 1426 #ifdef CONFIG_PM_SLEEP 1427 static int adv7180_suspend(struct device *dev) 1428 { 1429 struct i2c_client *client = to_i2c_client(dev); 1430 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1431 struct adv7180_state *state = to_state(sd); 1432 1433 return adv7180_set_power(state, false); 1434 } 1435 1436 static int adv7180_resume(struct device *dev) 1437 { 1438 struct i2c_client *client = to_i2c_client(dev); 1439 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1440 struct adv7180_state *state = to_state(sd); 1441 int ret; 1442 1443 ret = init_device(state); 1444 if (ret < 0) 1445 return ret; 1446 1447 ret = adv7180_set_power(state, state->powered); 1448 if (ret) 1449 return ret; 1450 1451 return 0; 1452 } 1453 1454 static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume); 1455 #define ADV7180_PM_OPS (&adv7180_pm_ops) 1456 1457 #else 1458 #define ADV7180_PM_OPS NULL 1459 #endif 1460 1461 #ifdef CONFIG_OF 1462 static const struct of_device_id adv7180_of_id[] = { 1463 { .compatible = "adi,adv7180", }, 1464 { .compatible = "adi,adv7180cp", }, 1465 { .compatible = "adi,adv7180st", }, 1466 { .compatible = "adi,adv7182", }, 1467 { .compatible = "adi,adv7280", }, 1468 { .compatible = "adi,adv7280-m", }, 1469 { .compatible = "adi,adv7281", }, 1470 { .compatible = "adi,adv7281-m", }, 1471 { .compatible = "adi,adv7281-ma", }, 1472 { .compatible = "adi,adv7282", }, 1473 { .compatible = "adi,adv7282-m", }, 1474 { }, 1475 }; 1476 1477 MODULE_DEVICE_TABLE(of, adv7180_of_id); 1478 #endif 1479 1480 static struct i2c_driver adv7180_driver = { 1481 .driver = { 1482 .name = KBUILD_MODNAME, 1483 .pm = ADV7180_PM_OPS, 1484 .of_match_table = of_match_ptr(adv7180_of_id), 1485 }, 1486 .probe = adv7180_probe, 1487 .remove = adv7180_remove, 1488 .id_table = adv7180_id, 1489 }; 1490 1491 module_i2c_driver(adv7180_driver); 1492 1493 MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver"); 1494 MODULE_AUTHOR("Mocean Laboratories"); 1495 MODULE_LICENSE("GPL v2"); 1496