1 /* 2 * Montage M88DS3103/M88RS6000 demodulator driver 3 * 4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "m88ds3103_priv.h" 18 19 static struct dvb_frontend_ops m88ds3103_ops; 20 21 /* write multiple registers */ 22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv, 23 u8 reg, const u8 *val, int len) 24 { 25 #define MAX_WR_LEN 32 26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1) 27 int ret; 28 u8 buf[MAX_WR_XFER_LEN]; 29 struct i2c_msg msg[1] = { 30 { 31 .addr = priv->cfg->i2c_addr, 32 .flags = 0, 33 .len = 1 + len, 34 .buf = buf, 35 } 36 }; 37 38 if (WARN_ON(len > MAX_WR_LEN)) 39 return -EINVAL; 40 41 buf[0] = reg; 42 memcpy(&buf[1], val, len); 43 44 mutex_lock(&priv->i2c_mutex); 45 ret = i2c_transfer(priv->i2c, msg, 1); 46 mutex_unlock(&priv->i2c_mutex); 47 if (ret == 1) { 48 ret = 0; 49 } else { 50 dev_warn(&priv->i2c->dev, 51 "%s: i2c wr failed=%d reg=%02x len=%d\n", 52 KBUILD_MODNAME, ret, reg, len); 53 ret = -EREMOTEIO; 54 } 55 56 return ret; 57 } 58 59 /* read multiple registers */ 60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv, 61 u8 reg, u8 *val, int len) 62 { 63 #define MAX_RD_LEN 3 64 #define MAX_RD_XFER_LEN (MAX_RD_LEN) 65 int ret; 66 u8 buf[MAX_RD_XFER_LEN]; 67 struct i2c_msg msg[2] = { 68 { 69 .addr = priv->cfg->i2c_addr, 70 .flags = 0, 71 .len = 1, 72 .buf = ®, 73 }, { 74 .addr = priv->cfg->i2c_addr, 75 .flags = I2C_M_RD, 76 .len = len, 77 .buf = buf, 78 } 79 }; 80 81 if (WARN_ON(len > MAX_RD_LEN)) 82 return -EINVAL; 83 84 mutex_lock(&priv->i2c_mutex); 85 ret = i2c_transfer(priv->i2c, msg, 2); 86 mutex_unlock(&priv->i2c_mutex); 87 if (ret == 2) { 88 memcpy(val, buf, len); 89 ret = 0; 90 } else { 91 dev_warn(&priv->i2c->dev, 92 "%s: i2c rd failed=%d reg=%02x len=%d\n", 93 KBUILD_MODNAME, ret, reg, len); 94 ret = -EREMOTEIO; 95 } 96 97 return ret; 98 } 99 100 /* write single register */ 101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val) 102 { 103 return m88ds3103_wr_regs(priv, reg, &val, 1); 104 } 105 106 /* read single register */ 107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val) 108 { 109 return m88ds3103_rd_regs(priv, reg, val, 1); 110 } 111 112 /* write single register with mask */ 113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv, 114 u8 reg, u8 val, u8 mask) 115 { 116 int ret; 117 u8 u8tmp; 118 119 /* no need for read if whole reg is written */ 120 if (mask != 0xff) { 121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 122 if (ret) 123 return ret; 124 125 val &= mask; 126 u8tmp &= ~mask; 127 val |= u8tmp; 128 } 129 130 return m88ds3103_wr_regs(priv, reg, &val, 1); 131 } 132 133 /* read single register with mask */ 134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv, 135 u8 reg, u8 *val, u8 mask) 136 { 137 int ret, i; 138 u8 u8tmp; 139 140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 141 if (ret) 142 return ret; 143 144 u8tmp &= mask; 145 146 /* find position of the first bit */ 147 for (i = 0; i < 8; i++) { 148 if ((mask >> i) & 0x01) 149 break; 150 } 151 *val = u8tmp >> i; 152 153 return 0; 154 } 155 156 /* write reg val table using reg addr auto increment */ 157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv, 158 const struct m88ds3103_reg_val *tab, int tab_len) 159 { 160 int ret, i, j; 161 u8 buf[83]; 162 163 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len); 164 165 if (tab_len > 86) { 166 ret = -EINVAL; 167 goto err; 168 } 169 170 for (i = 0, j = 0; i < tab_len; i++, j++) { 171 buf[j] = tab[i].val; 172 173 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || 174 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) { 175 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1); 176 if (ret) 177 goto err; 178 179 j = -1; 180 } 181 } 182 183 return 0; 184 err: 185 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 186 return ret; 187 } 188 189 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status) 190 { 191 struct m88ds3103_priv *priv = fe->demodulator_priv; 192 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 193 int ret; 194 u8 u8tmp; 195 196 *status = 0; 197 198 if (!priv->warm) { 199 ret = -EAGAIN; 200 goto err; 201 } 202 203 switch (c->delivery_system) { 204 case SYS_DVBS: 205 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07); 206 if (ret) 207 goto err; 208 209 if (u8tmp == 0x07) 210 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 211 FE_HAS_VITERBI | FE_HAS_SYNC | 212 FE_HAS_LOCK; 213 break; 214 case SYS_DVBS2: 215 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f); 216 if (ret) 217 goto err; 218 219 if (u8tmp == 0x8f) 220 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 221 FE_HAS_VITERBI | FE_HAS_SYNC | 222 FE_HAS_LOCK; 223 break; 224 default: 225 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 226 __func__); 227 ret = -EINVAL; 228 goto err; 229 } 230 231 priv->fe_status = *status; 232 233 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n", 234 __func__, u8tmp, *status); 235 236 return 0; 237 err: 238 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 239 return ret; 240 } 241 242 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 243 { 244 struct m88ds3103_priv *priv = fe->demodulator_priv; 245 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 246 int ret, len; 247 const struct m88ds3103_reg_val *init; 248 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ 249 u8 buf[3]; 250 u16 u16tmp, divide_ratio = 0; 251 u32 tuner_frequency, target_mclk; 252 s32 s32tmp; 253 254 dev_dbg(&priv->i2c->dev, 255 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 256 __func__, c->delivery_system, 257 c->modulation, c->frequency, c->symbol_rate, 258 c->inversion, c->pilot, c->rolloff); 259 260 if (!priv->warm) { 261 ret = -EAGAIN; 262 goto err; 263 } 264 265 /* reset */ 266 ret = m88ds3103_wr_reg(priv, 0x07, 0x80); 267 if (ret) 268 goto err; 269 270 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 271 if (ret) 272 goto err; 273 274 /* Disable demod clock path */ 275 if (priv->chip_id == M88RS6000_CHIP_ID) { 276 ret = m88ds3103_wr_reg(priv, 0x06, 0xe0); 277 if (ret) 278 goto err; 279 } 280 281 /* program tuner */ 282 if (fe->ops.tuner_ops.set_params) { 283 ret = fe->ops.tuner_ops.set_params(fe); 284 if (ret) 285 goto err; 286 } 287 288 if (fe->ops.tuner_ops.get_frequency) { 289 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); 290 if (ret) 291 goto err; 292 } else { 293 /* 294 * Use nominal target frequency as tuner driver does not provide 295 * actual frequency used. Carrier offset calculation is not 296 * valid. 297 */ 298 tuner_frequency = c->frequency; 299 } 300 301 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */ 302 if (priv->chip_id == M88RS6000_CHIP_ID) { 303 if (c->symbol_rate > 45010000) 304 priv->mclk_khz = 110250; 305 else 306 priv->mclk_khz = 96000; 307 308 if (c->delivery_system == SYS_DVBS) 309 target_mclk = 96000; 310 else 311 target_mclk = 144000; 312 313 /* Enable demod clock path */ 314 ret = m88ds3103_wr_reg(priv, 0x06, 0x00); 315 if (ret) 316 goto err; 317 usleep_range(10000, 20000); 318 } else { 319 /* set M88DS3103 mclk and ts mclk. */ 320 priv->mclk_khz = 96000; 321 322 switch (priv->cfg->ts_mode) { 323 case M88DS3103_TS_SERIAL: 324 case M88DS3103_TS_SERIAL_D7: 325 target_mclk = priv->cfg->ts_clk; 326 break; 327 case M88DS3103_TS_PARALLEL: 328 case M88DS3103_TS_CI: 329 if (c->delivery_system == SYS_DVBS) 330 target_mclk = 96000; 331 else { 332 if (c->symbol_rate < 18000000) 333 target_mclk = 96000; 334 else if (c->symbol_rate < 28000000) 335 target_mclk = 144000; 336 else 337 target_mclk = 192000; 338 } 339 break; 340 default: 341 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", 342 __func__); 343 ret = -EINVAL; 344 goto err; 345 } 346 347 switch (target_mclk) { 348 case 96000: 349 u8tmp1 = 0x02; /* 0b10 */ 350 u8tmp2 = 0x01; /* 0b01 */ 351 break; 352 case 144000: 353 u8tmp1 = 0x00; /* 0b00 */ 354 u8tmp2 = 0x01; /* 0b01 */ 355 break; 356 case 192000: 357 u8tmp1 = 0x03; /* 0b11 */ 358 u8tmp2 = 0x00; /* 0b00 */ 359 break; 360 } 361 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0); 362 if (ret) 363 goto err; 364 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0); 365 if (ret) 366 goto err; 367 } 368 369 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 370 if (ret) 371 goto err; 372 373 ret = m88ds3103_wr_reg(priv, 0x00, 0x01); 374 if (ret) 375 goto err; 376 377 switch (c->delivery_system) { 378 case SYS_DVBS: 379 if (priv->chip_id == M88RS6000_CHIP_ID) { 380 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); 381 init = m88rs6000_dvbs_init_reg_vals; 382 } else { 383 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 384 init = m88ds3103_dvbs_init_reg_vals; 385 } 386 break; 387 case SYS_DVBS2: 388 if (priv->chip_id == M88RS6000_CHIP_ID) { 389 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); 390 init = m88rs6000_dvbs2_init_reg_vals; 391 } else { 392 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 393 init = m88ds3103_dvbs2_init_reg_vals; 394 } 395 break; 396 default: 397 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 398 __func__); 399 ret = -EINVAL; 400 goto err; 401 } 402 403 /* program init table */ 404 if (c->delivery_system != priv->delivery_system) { 405 ret = m88ds3103_wr_reg_val_tab(priv, init, len); 406 if (ret) 407 goto err; 408 } 409 410 if (priv->chip_id == M88RS6000_CHIP_ID) { 411 if ((c->delivery_system == SYS_DVBS2) 412 && ((c->symbol_rate / 1000) <= 5000)) { 413 ret = m88ds3103_wr_reg(priv, 0xc0, 0x04); 414 if (ret) 415 goto err; 416 buf[0] = 0x09; 417 buf[1] = 0x22; 418 buf[2] = 0x88; 419 ret = m88ds3103_wr_regs(priv, 0x8a, buf, 3); 420 if (ret) 421 goto err; 422 } 423 ret = m88ds3103_wr_reg_mask(priv, 0x9d, 0x08, 0x08); 424 if (ret) 425 goto err; 426 ret = m88ds3103_wr_reg(priv, 0xf1, 0x01); 427 if (ret) 428 goto err; 429 ret = m88ds3103_wr_reg_mask(priv, 0x30, 0x80, 0x80); 430 if (ret) 431 goto err; 432 } 433 434 switch (priv->cfg->ts_mode) { 435 case M88DS3103_TS_SERIAL: 436 u8tmp1 = 0x00; 437 u8tmp = 0x06; 438 break; 439 case M88DS3103_TS_SERIAL_D7: 440 u8tmp1 = 0x20; 441 u8tmp = 0x06; 442 break; 443 case M88DS3103_TS_PARALLEL: 444 u8tmp = 0x02; 445 break; 446 case M88DS3103_TS_CI: 447 u8tmp = 0x03; 448 break; 449 default: 450 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__); 451 ret = -EINVAL; 452 goto err; 453 } 454 455 if (priv->cfg->ts_clk_pol) 456 u8tmp |= 0x40; 457 458 /* TS mode */ 459 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp); 460 if (ret) 461 goto err; 462 463 switch (priv->cfg->ts_mode) { 464 case M88DS3103_TS_SERIAL: 465 case M88DS3103_TS_SERIAL_D7: 466 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20); 467 if (ret) 468 goto err; 469 u8tmp1 = 0; 470 u8tmp2 = 0; 471 break; 472 default: 473 if (priv->cfg->ts_clk) { 474 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk); 475 u8tmp1 = divide_ratio / 2; 476 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2); 477 } 478 } 479 480 dev_dbg(&priv->i2c->dev, 481 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n", 482 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio); 483 484 u8tmp1--; 485 u8tmp2--; 486 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 487 u8tmp1 &= 0x3f; 488 /* u8tmp2[5:0] => ea[5:0] */ 489 u8tmp2 &= 0x3f; 490 491 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp); 492 if (ret) 493 goto err; 494 495 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2; 496 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp); 497 if (ret) 498 goto err; 499 500 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 501 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp); 502 if (ret) 503 goto err; 504 505 if (c->symbol_rate <= 3000000) 506 u8tmp = 0x20; 507 else if (c->symbol_rate <= 10000000) 508 u8tmp = 0x10; 509 else 510 u8tmp = 0x06; 511 512 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08); 513 if (ret) 514 goto err; 515 516 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp); 517 if (ret) 518 goto err; 519 520 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08); 521 if (ret) 522 goto err; 523 524 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00); 525 if (ret) 526 goto err; 527 528 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, priv->mclk_khz / 2); 529 buf[0] = (u16tmp >> 0) & 0xff; 530 buf[1] = (u16tmp >> 8) & 0xff; 531 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2); 532 if (ret) 533 goto err; 534 535 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02); 536 if (ret) 537 goto err; 538 539 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10); 540 if (ret) 541 goto err; 542 543 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc); 544 if (ret) 545 goto err; 546 547 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__, 548 (tuner_frequency - c->frequency)); 549 550 s32tmp = 0x10000 * (tuner_frequency - c->frequency); 551 s32tmp = DIV_ROUND_CLOSEST(s32tmp, priv->mclk_khz); 552 if (s32tmp < 0) 553 s32tmp += 0x10000; 554 555 buf[0] = (s32tmp >> 0) & 0xff; 556 buf[1] = (s32tmp >> 8) & 0xff; 557 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2); 558 if (ret) 559 goto err; 560 561 ret = m88ds3103_wr_reg(priv, 0x00, 0x00); 562 if (ret) 563 goto err; 564 565 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 566 if (ret) 567 goto err; 568 569 priv->delivery_system = c->delivery_system; 570 571 return 0; 572 err: 573 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 574 return ret; 575 } 576 577 static int m88ds3103_init(struct dvb_frontend *fe) 578 { 579 struct m88ds3103_priv *priv = fe->demodulator_priv; 580 int ret, len, remaining; 581 const struct firmware *fw = NULL; 582 u8 *fw_file; 583 u8 u8tmp; 584 585 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 586 587 /* set cold state by default */ 588 priv->warm = false; 589 590 /* wake up device from sleep */ 591 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01); 592 if (ret) 593 goto err; 594 595 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01); 596 if (ret) 597 goto err; 598 599 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10); 600 if (ret) 601 goto err; 602 603 /* firmware status */ 604 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 605 if (ret) 606 goto err; 607 608 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp); 609 610 if (u8tmp) 611 goto skip_fw_download; 612 613 /* global reset, global diseqc reset, golbal fec reset */ 614 ret = m88ds3103_wr_reg(priv, 0x07, 0xe0); 615 if (ret) 616 goto err; 617 618 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 619 if (ret) 620 goto err; 621 622 /* cold state - try to download firmware */ 623 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n", 624 KBUILD_MODNAME, m88ds3103_ops.info.name); 625 626 if (priv->chip_id == M88RS6000_CHIP_ID) 627 fw_file = M88RS6000_FIRMWARE; 628 else 629 fw_file = M88DS3103_FIRMWARE; 630 /* request the firmware, this will block and timeout */ 631 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); 632 if (ret) { 633 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n", 634 KBUILD_MODNAME, fw_file); 635 goto err; 636 } 637 638 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n", 639 KBUILD_MODNAME, fw_file); 640 641 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 642 if (ret) 643 goto error_fw_release; 644 645 for (remaining = fw->size; remaining > 0; 646 remaining -= (priv->cfg->i2c_wr_max - 1)) { 647 len = remaining; 648 if (len > (priv->cfg->i2c_wr_max - 1)) 649 len = (priv->cfg->i2c_wr_max - 1); 650 651 ret = m88ds3103_wr_regs(priv, 0xb0, 652 &fw->data[fw->size - remaining], len); 653 if (ret) { 654 dev_err(&priv->i2c->dev, 655 "%s: firmware download failed=%d\n", 656 KBUILD_MODNAME, ret); 657 goto error_fw_release; 658 } 659 } 660 661 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 662 if (ret) 663 goto error_fw_release; 664 665 release_firmware(fw); 666 fw = NULL; 667 668 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 669 if (ret) 670 goto err; 671 672 if (!u8tmp) { 673 dev_info(&priv->i2c->dev, "%s: firmware did not run\n", 674 KBUILD_MODNAME); 675 ret = -EFAULT; 676 goto err; 677 } 678 679 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n", 680 KBUILD_MODNAME, m88ds3103_ops.info.name); 681 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n", 682 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf)); 683 684 skip_fw_download: 685 /* warm state */ 686 priv->warm = true; 687 688 return 0; 689 690 error_fw_release: 691 release_firmware(fw); 692 err: 693 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 694 return ret; 695 } 696 697 static int m88ds3103_sleep(struct dvb_frontend *fe) 698 { 699 struct m88ds3103_priv *priv = fe->demodulator_priv; 700 int ret; 701 u8 u8tmp; 702 703 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 704 705 priv->delivery_system = SYS_UNDEFINED; 706 707 /* TS Hi-Z */ 708 if (priv->chip_id == M88RS6000_CHIP_ID) 709 u8tmp = 0x29; 710 else 711 u8tmp = 0x27; 712 ret = m88ds3103_wr_reg_mask(priv, u8tmp, 0x00, 0x01); 713 if (ret) 714 goto err; 715 716 /* sleep */ 717 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 718 if (ret) 719 goto err; 720 721 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 722 if (ret) 723 goto err; 724 725 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 726 if (ret) 727 goto err; 728 729 return 0; 730 err: 731 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 732 return ret; 733 } 734 735 static int m88ds3103_get_frontend(struct dvb_frontend *fe) 736 { 737 struct m88ds3103_priv *priv = fe->demodulator_priv; 738 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 739 int ret; 740 u8 buf[3]; 741 742 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 743 744 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) { 745 ret = -EAGAIN; 746 goto err; 747 } 748 749 switch (c->delivery_system) { 750 case SYS_DVBS: 751 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]); 752 if (ret) 753 goto err; 754 755 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]); 756 if (ret) 757 goto err; 758 759 switch ((buf[0] >> 2) & 0x01) { 760 case 0: 761 c->inversion = INVERSION_OFF; 762 break; 763 case 1: 764 c->inversion = INVERSION_ON; 765 break; 766 } 767 768 switch ((buf[1] >> 5) & 0x07) { 769 case 0: 770 c->fec_inner = FEC_7_8; 771 break; 772 case 1: 773 c->fec_inner = FEC_5_6; 774 break; 775 case 2: 776 c->fec_inner = FEC_3_4; 777 break; 778 case 3: 779 c->fec_inner = FEC_2_3; 780 break; 781 case 4: 782 c->fec_inner = FEC_1_2; 783 break; 784 default: 785 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 786 __func__); 787 } 788 789 c->modulation = QPSK; 790 791 break; 792 case SYS_DVBS2: 793 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]); 794 if (ret) 795 goto err; 796 797 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]); 798 if (ret) 799 goto err; 800 801 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]); 802 if (ret) 803 goto err; 804 805 switch ((buf[0] >> 0) & 0x0f) { 806 case 2: 807 c->fec_inner = FEC_2_5; 808 break; 809 case 3: 810 c->fec_inner = FEC_1_2; 811 break; 812 case 4: 813 c->fec_inner = FEC_3_5; 814 break; 815 case 5: 816 c->fec_inner = FEC_2_3; 817 break; 818 case 6: 819 c->fec_inner = FEC_3_4; 820 break; 821 case 7: 822 c->fec_inner = FEC_4_5; 823 break; 824 case 8: 825 c->fec_inner = FEC_5_6; 826 break; 827 case 9: 828 c->fec_inner = FEC_8_9; 829 break; 830 case 10: 831 c->fec_inner = FEC_9_10; 832 break; 833 default: 834 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 835 __func__); 836 } 837 838 switch ((buf[0] >> 5) & 0x01) { 839 case 0: 840 c->pilot = PILOT_OFF; 841 break; 842 case 1: 843 c->pilot = PILOT_ON; 844 break; 845 } 846 847 switch ((buf[0] >> 6) & 0x07) { 848 case 0: 849 c->modulation = QPSK; 850 break; 851 case 1: 852 c->modulation = PSK_8; 853 break; 854 case 2: 855 c->modulation = APSK_16; 856 break; 857 case 3: 858 c->modulation = APSK_32; 859 break; 860 default: 861 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n", 862 __func__); 863 } 864 865 switch ((buf[1] >> 7) & 0x01) { 866 case 0: 867 c->inversion = INVERSION_OFF; 868 break; 869 case 1: 870 c->inversion = INVERSION_ON; 871 break; 872 } 873 874 switch ((buf[2] >> 0) & 0x03) { 875 case 0: 876 c->rolloff = ROLLOFF_35; 877 break; 878 case 1: 879 c->rolloff = ROLLOFF_25; 880 break; 881 case 2: 882 c->rolloff = ROLLOFF_20; 883 break; 884 default: 885 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n", 886 __func__); 887 } 888 break; 889 default: 890 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 891 __func__); 892 ret = -EINVAL; 893 goto err; 894 } 895 896 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2); 897 if (ret) 898 goto err; 899 900 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) * 901 priv->mclk_khz * 1000 / 0x10000; 902 903 return 0; 904 err: 905 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 906 return ret; 907 } 908 909 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) 910 { 911 struct m88ds3103_priv *priv = fe->demodulator_priv; 912 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 913 int ret, i, tmp; 914 u8 buf[3]; 915 u16 noise, signal; 916 u32 noise_tot, signal_tot; 917 918 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 919 /* reports SNR in resolution of 0.1 dB */ 920 921 /* more iterations for more accurate estimation */ 922 #define M88DS3103_SNR_ITERATIONS 3 923 924 switch (c->delivery_system) { 925 case SYS_DVBS: 926 tmp = 0; 927 928 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 929 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]); 930 if (ret) 931 goto err; 932 933 tmp += buf[0]; 934 } 935 936 /* use of one register limits max value to 15 dB */ 937 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ 938 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS); 939 if (tmp) 940 *snr = div_u64((u64) 100 * intlog2(tmp), intlog2(10)); 941 else 942 *snr = 0; 943 break; 944 case SYS_DVBS2: 945 noise_tot = 0; 946 signal_tot = 0; 947 948 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 949 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3); 950 if (ret) 951 goto err; 952 953 noise = buf[1] << 6; /* [13:6] */ 954 noise |= buf[0] & 0x3f; /* [5:0] */ 955 noise >>= 2; 956 signal = buf[2] * buf[2]; 957 signal >>= 1; 958 959 noise_tot += noise; 960 signal_tot += signal; 961 } 962 963 noise = noise_tot / M88DS3103_SNR_ITERATIONS; 964 signal = signal_tot / M88DS3103_SNR_ITERATIONS; 965 966 /* SNR(X) dB = 10 * log10(X) dB */ 967 if (signal > noise) { 968 tmp = signal / noise; 969 *snr = div_u64((u64) 100 * intlog10(tmp), (1 << 24)); 970 } else { 971 *snr = 0; 972 } 973 break; 974 default: 975 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 976 __func__); 977 ret = -EINVAL; 978 goto err; 979 } 980 981 return 0; 982 err: 983 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 984 return ret; 985 } 986 987 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber) 988 { 989 struct m88ds3103_priv *priv = fe->demodulator_priv; 990 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 991 int ret; 992 unsigned int utmp; 993 u8 buf[3], u8tmp; 994 995 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 996 997 switch (c->delivery_system) { 998 case SYS_DVBS: 999 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04); 1000 if (ret) 1001 goto err; 1002 1003 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp); 1004 if (ret) 1005 goto err; 1006 1007 if (!(u8tmp & 0x10)) { 1008 u8tmp |= 0x10; 1009 1010 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2); 1011 if (ret) 1012 goto err; 1013 1014 priv->ber = (buf[1] << 8) | (buf[0] << 0); 1015 1016 /* restart counters */ 1017 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp); 1018 if (ret) 1019 goto err; 1020 } 1021 break; 1022 case SYS_DVBS2: 1023 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3); 1024 if (ret) 1025 goto err; 1026 1027 utmp = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0); 1028 1029 if (utmp > 3000) { 1030 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2); 1031 if (ret) 1032 goto err; 1033 1034 priv->ber = (buf[1] << 8) | (buf[0] << 0); 1035 1036 /* restart counters */ 1037 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01); 1038 if (ret) 1039 goto err; 1040 1041 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01); 1042 if (ret) 1043 goto err; 1044 1045 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00); 1046 if (ret) 1047 goto err; 1048 1049 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00); 1050 if (ret) 1051 goto err; 1052 } 1053 break; 1054 default: 1055 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 1056 __func__); 1057 ret = -EINVAL; 1058 goto err; 1059 } 1060 1061 *ber = priv->ber; 1062 1063 return 0; 1064 err: 1065 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1066 return ret; 1067 } 1068 1069 static int m88ds3103_set_tone(struct dvb_frontend *fe, 1070 fe_sec_tone_mode_t fe_sec_tone_mode) 1071 { 1072 struct m88ds3103_priv *priv = fe->demodulator_priv; 1073 int ret; 1074 u8 u8tmp, tone, reg_a1_mask; 1075 1076 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__, 1077 fe_sec_tone_mode); 1078 1079 if (!priv->warm) { 1080 ret = -EAGAIN; 1081 goto err; 1082 } 1083 1084 switch (fe_sec_tone_mode) { 1085 case SEC_TONE_ON: 1086 tone = 0; 1087 reg_a1_mask = 0x47; 1088 break; 1089 case SEC_TONE_OFF: 1090 tone = 1; 1091 reg_a1_mask = 0x00; 1092 break; 1093 default: 1094 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n", 1095 __func__); 1096 ret = -EINVAL; 1097 goto err; 1098 } 1099 1100 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5; 1101 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1102 if (ret) 1103 goto err; 1104 1105 u8tmp = 1 << 2; 1106 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask); 1107 if (ret) 1108 goto err; 1109 1110 return 0; 1111 err: 1112 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1113 return ret; 1114 } 1115 1116 static int m88ds3103_set_voltage(struct dvb_frontend *fe, 1117 fe_sec_voltage_t fe_sec_voltage) 1118 { 1119 struct m88ds3103_priv *priv = fe->demodulator_priv; 1120 int ret; 1121 u8 u8tmp; 1122 bool voltage_sel, voltage_dis; 1123 1124 dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__, 1125 fe_sec_voltage); 1126 1127 if (!priv->warm) { 1128 ret = -EAGAIN; 1129 goto err; 1130 } 1131 1132 switch (fe_sec_voltage) { 1133 case SEC_VOLTAGE_18: 1134 voltage_sel = true; 1135 voltage_dis = false; 1136 break; 1137 case SEC_VOLTAGE_13: 1138 voltage_sel = false; 1139 voltage_dis = false; 1140 break; 1141 case SEC_VOLTAGE_OFF: 1142 voltage_sel = false; 1143 voltage_dis = true; 1144 break; 1145 default: 1146 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n", 1147 __func__); 1148 ret = -EINVAL; 1149 goto err; 1150 } 1151 1152 /* output pin polarity */ 1153 voltage_sel ^= priv->cfg->lnb_hv_pol; 1154 voltage_dis ^= priv->cfg->lnb_en_pol; 1155 1156 u8tmp = voltage_dis << 1 | voltage_sel << 0; 1157 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03); 1158 if (ret) 1159 goto err; 1160 1161 return 0; 1162 err: 1163 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1164 return ret; 1165 } 1166 1167 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, 1168 struct dvb_diseqc_master_cmd *diseqc_cmd) 1169 { 1170 struct m88ds3103_priv *priv = fe->demodulator_priv; 1171 int ret, i; 1172 u8 u8tmp; 1173 1174 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__, 1175 diseqc_cmd->msg_len, diseqc_cmd->msg); 1176 1177 if (!priv->warm) { 1178 ret = -EAGAIN; 1179 goto err; 1180 } 1181 1182 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { 1183 ret = -EINVAL; 1184 goto err; 1185 } 1186 1187 u8tmp = priv->cfg->envelope_mode << 5; 1188 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1189 if (ret) 1190 goto err; 1191 1192 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg, 1193 diseqc_cmd->msg_len); 1194 if (ret) 1195 goto err; 1196 1197 ret = m88ds3103_wr_reg(priv, 0xa1, 1198 (diseqc_cmd->msg_len - 1) << 3 | 0x07); 1199 if (ret) 1200 goto err; 1201 1202 /* DiSEqC message typical period is 54 ms */ 1203 usleep_range(40000, 60000); 1204 1205 /* wait DiSEqC TX ready */ 1206 for (i = 20, u8tmp = 1; i && u8tmp; i--) { 1207 usleep_range(5000, 10000); 1208 1209 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1210 if (ret) 1211 goto err; 1212 } 1213 1214 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1215 1216 if (i == 0) { 1217 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1218 1219 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0); 1220 if (ret) 1221 goto err; 1222 } 1223 1224 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1225 if (ret) 1226 goto err; 1227 1228 if (i == 0) { 1229 ret = -ETIMEDOUT; 1230 goto err; 1231 } 1232 1233 return 0; 1234 err: 1235 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1236 return ret; 1237 } 1238 1239 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, 1240 fe_sec_mini_cmd_t fe_sec_mini_cmd) 1241 { 1242 struct m88ds3103_priv *priv = fe->demodulator_priv; 1243 int ret, i; 1244 u8 u8tmp, burst; 1245 1246 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__, 1247 fe_sec_mini_cmd); 1248 1249 if (!priv->warm) { 1250 ret = -EAGAIN; 1251 goto err; 1252 } 1253 1254 u8tmp = priv->cfg->envelope_mode << 5; 1255 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1256 if (ret) 1257 goto err; 1258 1259 switch (fe_sec_mini_cmd) { 1260 case SEC_MINI_A: 1261 burst = 0x02; 1262 break; 1263 case SEC_MINI_B: 1264 burst = 0x01; 1265 break; 1266 default: 1267 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n", 1268 __func__); 1269 ret = -EINVAL; 1270 goto err; 1271 } 1272 1273 ret = m88ds3103_wr_reg(priv, 0xa1, burst); 1274 if (ret) 1275 goto err; 1276 1277 /* DiSEqC ToneBurst period is 12.5 ms */ 1278 usleep_range(11000, 20000); 1279 1280 /* wait DiSEqC TX ready */ 1281 for (i = 5, u8tmp = 1; i && u8tmp; i--) { 1282 usleep_range(800, 2000); 1283 1284 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1285 if (ret) 1286 goto err; 1287 } 1288 1289 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1290 1291 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1292 if (ret) 1293 goto err; 1294 1295 if (i == 0) { 1296 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1297 ret = -ETIMEDOUT; 1298 goto err; 1299 } 1300 1301 return 0; 1302 err: 1303 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1304 return ret; 1305 } 1306 1307 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, 1308 struct dvb_frontend_tune_settings *s) 1309 { 1310 s->min_delay_ms = 3000; 1311 1312 return 0; 1313 } 1314 1315 static void m88ds3103_release(struct dvb_frontend *fe) 1316 { 1317 struct m88ds3103_priv *priv = fe->demodulator_priv; 1318 1319 i2c_del_mux_adapter(priv->i2c_adapter); 1320 kfree(priv); 1321 } 1322 1323 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) 1324 { 1325 struct m88ds3103_priv *priv = mux_priv; 1326 int ret; 1327 struct i2c_msg gate_open_msg[1] = { 1328 { 1329 .addr = priv->cfg->i2c_addr, 1330 .flags = 0, 1331 .len = 2, 1332 .buf = "\x03\x11", 1333 } 1334 }; 1335 1336 mutex_lock(&priv->i2c_mutex); 1337 1338 /* open tuner I2C repeater for 1 xfer, closes automatically */ 1339 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1); 1340 if (ret != 1) { 1341 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n", 1342 KBUILD_MODNAME, ret); 1343 if (ret >= 0) 1344 ret = -EREMOTEIO; 1345 1346 return ret; 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv, 1353 u32 chan) 1354 { 1355 struct m88ds3103_priv *priv = mux_priv; 1356 1357 mutex_unlock(&priv->i2c_mutex); 1358 1359 return 0; 1360 } 1361 1362 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, 1363 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) 1364 { 1365 int ret; 1366 struct m88ds3103_priv *priv; 1367 u8 chip_id, u8tmp; 1368 1369 /* allocate memory for the internal priv */ 1370 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1371 if (!priv) { 1372 ret = -ENOMEM; 1373 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 1374 goto err; 1375 } 1376 1377 priv->cfg = cfg; 1378 priv->i2c = i2c; 1379 mutex_init(&priv->i2c_mutex); 1380 1381 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */ 1382 ret = m88ds3103_rd_reg(priv, 0x00, &chip_id); 1383 if (ret) 1384 goto err; 1385 1386 chip_id >>= 1; 1387 dev_info(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 1388 1389 switch (chip_id) { 1390 case M88RS6000_CHIP_ID: 1391 case M88DS3103_CHIP_ID: 1392 break; 1393 default: 1394 goto err; 1395 } 1396 priv->chip_id = chip_id; 1397 1398 switch (priv->cfg->clock_out) { 1399 case M88DS3103_CLOCK_OUT_DISABLED: 1400 u8tmp = 0x80; 1401 break; 1402 case M88DS3103_CLOCK_OUT_ENABLED: 1403 u8tmp = 0x00; 1404 break; 1405 case M88DS3103_CLOCK_OUT_ENABLED_DIV2: 1406 u8tmp = 0x10; 1407 break; 1408 default: 1409 goto err; 1410 } 1411 1412 /* 0x29 register is defined differently for m88rs6000. */ 1413 /* set internal tuner address to 0x21 */ 1414 if (chip_id == M88RS6000_CHIP_ID) 1415 u8tmp = 0x00; 1416 1417 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp); 1418 if (ret) 1419 goto err; 1420 1421 /* sleep */ 1422 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 1423 if (ret) 1424 goto err; 1425 1426 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 1427 if (ret) 1428 goto err; 1429 1430 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 1431 if (ret) 1432 goto err; 1433 1434 /* create mux i2c adapter for tuner */ 1435 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, 1436 m88ds3103_select, m88ds3103_deselect); 1437 if (priv->i2c_adapter == NULL) 1438 goto err; 1439 1440 *tuner_i2c_adapter = priv->i2c_adapter; 1441 1442 /* create dvb_frontend */ 1443 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); 1444 if (priv->chip_id == M88RS6000_CHIP_ID) 1445 strncpy(priv->fe.ops.info.name, 1446 "Montage M88RS6000", sizeof(priv->fe.ops.info.name)); 1447 priv->fe.demodulator_priv = priv; 1448 1449 return &priv->fe; 1450 err: 1451 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); 1452 kfree(priv); 1453 return NULL; 1454 } 1455 EXPORT_SYMBOL(m88ds3103_attach); 1456 1457 static struct dvb_frontend_ops m88ds3103_ops = { 1458 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1459 .info = { 1460 .name = "Montage M88DS3103", 1461 .frequency_min = 950000, 1462 .frequency_max = 2150000, 1463 .frequency_tolerance = 5000, 1464 .symbol_rate_min = 1000000, 1465 .symbol_rate_max = 45000000, 1466 .caps = FE_CAN_INVERSION_AUTO | 1467 FE_CAN_FEC_1_2 | 1468 FE_CAN_FEC_2_3 | 1469 FE_CAN_FEC_3_4 | 1470 FE_CAN_FEC_4_5 | 1471 FE_CAN_FEC_5_6 | 1472 FE_CAN_FEC_6_7 | 1473 FE_CAN_FEC_7_8 | 1474 FE_CAN_FEC_8_9 | 1475 FE_CAN_FEC_AUTO | 1476 FE_CAN_QPSK | 1477 FE_CAN_RECOVER | 1478 FE_CAN_2G_MODULATION 1479 }, 1480 1481 .release = m88ds3103_release, 1482 1483 .get_tune_settings = m88ds3103_get_tune_settings, 1484 1485 .init = m88ds3103_init, 1486 .sleep = m88ds3103_sleep, 1487 1488 .set_frontend = m88ds3103_set_frontend, 1489 .get_frontend = m88ds3103_get_frontend, 1490 1491 .read_status = m88ds3103_read_status, 1492 .read_snr = m88ds3103_read_snr, 1493 .read_ber = m88ds3103_read_ber, 1494 1495 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, 1496 .diseqc_send_burst = m88ds3103_diseqc_send_burst, 1497 1498 .set_tone = m88ds3103_set_tone, 1499 .set_voltage = m88ds3103_set_voltage, 1500 }; 1501 1502 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1503 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver"); 1504 MODULE_LICENSE("GPL"); 1505 MODULE_FIRMWARE(M88DS3103_FIRMWARE); 1506 MODULE_FIRMWARE(M88RS6000_FIRMWARE); 1507