1 /* 2 * Montage M88DS3103 demodulator driver 3 * 4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "m88ds3103_priv.h" 18 19 static struct dvb_frontend_ops m88ds3103_ops; 20 21 /* write multiple registers */ 22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv, 23 u8 reg, const u8 *val, int len) 24 { 25 #define MAX_WR_LEN 32 26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1) 27 int ret; 28 u8 buf[MAX_WR_XFER_LEN]; 29 struct i2c_msg msg[1] = { 30 { 31 .addr = priv->cfg->i2c_addr, 32 .flags = 0, 33 .len = 1 + len, 34 .buf = buf, 35 } 36 }; 37 38 if (WARN_ON(len > MAX_WR_LEN)) 39 return -EINVAL; 40 41 buf[0] = reg; 42 memcpy(&buf[1], val, len); 43 44 mutex_lock(&priv->i2c_mutex); 45 ret = i2c_transfer(priv->i2c, msg, 1); 46 mutex_unlock(&priv->i2c_mutex); 47 if (ret == 1) { 48 ret = 0; 49 } else { 50 dev_warn(&priv->i2c->dev, 51 "%s: i2c wr failed=%d reg=%02x len=%d\n", 52 KBUILD_MODNAME, ret, reg, len); 53 ret = -EREMOTEIO; 54 } 55 56 return ret; 57 } 58 59 /* read multiple registers */ 60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv, 61 u8 reg, u8 *val, int len) 62 { 63 #define MAX_RD_LEN 3 64 #define MAX_RD_XFER_LEN (MAX_RD_LEN) 65 int ret; 66 u8 buf[MAX_RD_XFER_LEN]; 67 struct i2c_msg msg[2] = { 68 { 69 .addr = priv->cfg->i2c_addr, 70 .flags = 0, 71 .len = 1, 72 .buf = ®, 73 }, { 74 .addr = priv->cfg->i2c_addr, 75 .flags = I2C_M_RD, 76 .len = len, 77 .buf = buf, 78 } 79 }; 80 81 if (WARN_ON(len > MAX_RD_LEN)) 82 return -EINVAL; 83 84 mutex_lock(&priv->i2c_mutex); 85 ret = i2c_transfer(priv->i2c, msg, 2); 86 mutex_unlock(&priv->i2c_mutex); 87 if (ret == 2) { 88 memcpy(val, buf, len); 89 ret = 0; 90 } else { 91 dev_warn(&priv->i2c->dev, 92 "%s: i2c rd failed=%d reg=%02x len=%d\n", 93 KBUILD_MODNAME, ret, reg, len); 94 ret = -EREMOTEIO; 95 } 96 97 return ret; 98 } 99 100 /* write single register */ 101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val) 102 { 103 return m88ds3103_wr_regs(priv, reg, &val, 1); 104 } 105 106 /* read single register */ 107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val) 108 { 109 return m88ds3103_rd_regs(priv, reg, val, 1); 110 } 111 112 /* write single register with mask */ 113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv, 114 u8 reg, u8 val, u8 mask) 115 { 116 int ret; 117 u8 u8tmp; 118 119 /* no need for read if whole reg is written */ 120 if (mask != 0xff) { 121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 122 if (ret) 123 return ret; 124 125 val &= mask; 126 u8tmp &= ~mask; 127 val |= u8tmp; 128 } 129 130 return m88ds3103_wr_regs(priv, reg, &val, 1); 131 } 132 133 /* read single register with mask */ 134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv, 135 u8 reg, u8 *val, u8 mask) 136 { 137 int ret, i; 138 u8 u8tmp; 139 140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1); 141 if (ret) 142 return ret; 143 144 u8tmp &= mask; 145 146 /* find position of the first bit */ 147 for (i = 0; i < 8; i++) { 148 if ((mask >> i) & 0x01) 149 break; 150 } 151 *val = u8tmp >> i; 152 153 return 0; 154 } 155 156 /* write reg val table using reg addr auto increment */ 157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv, 158 const struct m88ds3103_reg_val *tab, int tab_len) 159 { 160 int ret, i, j; 161 u8 buf[83]; 162 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len); 163 164 if (tab_len > 83) { 165 ret = -EINVAL; 166 goto err; 167 } 168 169 for (i = 0, j = 0; i < tab_len; i++, j++) { 170 buf[j] = tab[i].val; 171 172 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || 173 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) { 174 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1); 175 if (ret) 176 goto err; 177 178 j = -1; 179 } 180 } 181 182 return 0; 183 err: 184 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 185 return ret; 186 } 187 188 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status) 189 { 190 struct m88ds3103_priv *priv = fe->demodulator_priv; 191 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 192 int ret; 193 u8 u8tmp; 194 195 *status = 0; 196 197 if (!priv->warm) { 198 ret = -EAGAIN; 199 goto err; 200 } 201 202 switch (c->delivery_system) { 203 case SYS_DVBS: 204 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07); 205 if (ret) 206 goto err; 207 208 if (u8tmp == 0x07) 209 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 210 FE_HAS_VITERBI | FE_HAS_SYNC | 211 FE_HAS_LOCK; 212 break; 213 case SYS_DVBS2: 214 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f); 215 if (ret) 216 goto err; 217 218 if (u8tmp == 0x8f) 219 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 220 FE_HAS_VITERBI | FE_HAS_SYNC | 221 FE_HAS_LOCK; 222 break; 223 default: 224 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 225 __func__); 226 ret = -EINVAL; 227 goto err; 228 } 229 230 priv->fe_status = *status; 231 232 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n", 233 __func__, u8tmp, *status); 234 235 return 0; 236 err: 237 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 238 return ret; 239 } 240 241 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 242 { 243 struct m88ds3103_priv *priv = fe->demodulator_priv; 244 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 245 int ret, len; 246 const struct m88ds3103_reg_val *init; 247 u8 u8tmp, u8tmp1, u8tmp2; 248 u8 buf[2]; 249 u16 u16tmp, divide_ratio; 250 u32 tuner_frequency, target_mclk, ts_clk; 251 s32 s32tmp; 252 dev_dbg(&priv->i2c->dev, 253 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 254 __func__, c->delivery_system, 255 c->modulation, c->frequency, c->symbol_rate, 256 c->inversion, c->pilot, c->rolloff); 257 258 if (!priv->warm) { 259 ret = -EAGAIN; 260 goto err; 261 } 262 263 /* program tuner */ 264 if (fe->ops.tuner_ops.set_params) { 265 ret = fe->ops.tuner_ops.set_params(fe); 266 if (ret) 267 goto err; 268 } 269 270 if (fe->ops.tuner_ops.get_frequency) { 271 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); 272 if (ret) 273 goto err; 274 } else { 275 /* 276 * Use nominal target frequency as tuner driver does not provide 277 * actual frequency used. Carrier offset calculation is not 278 * valid. 279 */ 280 tuner_frequency = c->frequency; 281 } 282 283 /* reset */ 284 ret = m88ds3103_wr_reg(priv, 0x07, 0x80); 285 if (ret) 286 goto err; 287 288 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 289 if (ret) 290 goto err; 291 292 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 293 if (ret) 294 goto err; 295 296 ret = m88ds3103_wr_reg(priv, 0x00, 0x01); 297 if (ret) 298 goto err; 299 300 switch (c->delivery_system) { 301 case SYS_DVBS: 302 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 303 init = m88ds3103_dvbs_init_reg_vals; 304 target_mclk = 96000; 305 break; 306 case SYS_DVBS2: 307 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 308 init = m88ds3103_dvbs2_init_reg_vals; 309 310 switch (priv->cfg->ts_mode) { 311 case M88DS3103_TS_SERIAL: 312 case M88DS3103_TS_SERIAL_D7: 313 if (c->symbol_rate < 18000000) 314 target_mclk = 96000; 315 else 316 target_mclk = 144000; 317 break; 318 case M88DS3103_TS_PARALLEL: 319 case M88DS3103_TS_PARALLEL_12: 320 case M88DS3103_TS_PARALLEL_16: 321 case M88DS3103_TS_PARALLEL_19_2: 322 case M88DS3103_TS_CI: 323 if (c->symbol_rate < 18000000) 324 target_mclk = 96000; 325 else if (c->symbol_rate < 28000000) 326 target_mclk = 144000; 327 else 328 target_mclk = 192000; 329 break; 330 default: 331 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", 332 __func__); 333 ret = -EINVAL; 334 goto err; 335 } 336 break; 337 default: 338 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 339 __func__); 340 ret = -EINVAL; 341 goto err; 342 } 343 344 /* program init table */ 345 if (c->delivery_system != priv->delivery_system) { 346 ret = m88ds3103_wr_reg_val_tab(priv, init, len); 347 if (ret) 348 goto err; 349 } 350 351 u8tmp1 = 0; /* silence compiler warning */ 352 switch (priv->cfg->ts_mode) { 353 case M88DS3103_TS_SERIAL: 354 u8tmp1 = 0x00; 355 ts_clk = 0; 356 u8tmp = 0x46; 357 break; 358 case M88DS3103_TS_SERIAL_D7: 359 u8tmp1 = 0x20; 360 ts_clk = 0; 361 u8tmp = 0x46; 362 break; 363 case M88DS3103_TS_PARALLEL: 364 ts_clk = 24000; 365 u8tmp = 0x42; 366 break; 367 case M88DS3103_TS_PARALLEL_12: 368 ts_clk = 12000; 369 u8tmp = 0x42; 370 break; 371 case M88DS3103_TS_PARALLEL_16: 372 ts_clk = 16000; 373 u8tmp = 0x42; 374 break; 375 case M88DS3103_TS_PARALLEL_19_2: 376 ts_clk = 19200; 377 u8tmp = 0x42; 378 break; 379 case M88DS3103_TS_CI: 380 ts_clk = 6000; 381 u8tmp = 0x43; 382 break; 383 default: 384 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__); 385 ret = -EINVAL; 386 goto err; 387 } 388 389 /* TS mode */ 390 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp); 391 if (ret) 392 goto err; 393 394 switch (priv->cfg->ts_mode) { 395 case M88DS3103_TS_SERIAL: 396 case M88DS3103_TS_SERIAL_D7: 397 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20); 398 if (ret) 399 goto err; 400 } 401 402 if (ts_clk) { 403 divide_ratio = DIV_ROUND_UP(target_mclk, ts_clk); 404 u8tmp1 = divide_ratio / 2; 405 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2); 406 } else { 407 divide_ratio = 0; 408 u8tmp1 = 0; 409 u8tmp2 = 0; 410 } 411 412 dev_dbg(&priv->i2c->dev, 413 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n", 414 __func__, target_mclk, ts_clk, divide_ratio); 415 416 u8tmp1--; 417 u8tmp2--; 418 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 419 u8tmp1 &= 0x3f; 420 /* u8tmp2[5:0] => ea[5:0] */ 421 u8tmp2 &= 0x3f; 422 423 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp); 424 if (ret) 425 goto err; 426 427 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2; 428 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp); 429 if (ret) 430 goto err; 431 432 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 433 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp); 434 if (ret) 435 goto err; 436 437 switch (target_mclk) { 438 case 96000: 439 u8tmp1 = 0x02; /* 0b10 */ 440 u8tmp2 = 0x01; /* 0b01 */ 441 break; 442 case 144000: 443 u8tmp1 = 0x00; /* 0b00 */ 444 u8tmp2 = 0x01; /* 0b01 */ 445 break; 446 case 192000: 447 u8tmp1 = 0x03; /* 0b11 */ 448 u8tmp2 = 0x00; /* 0b00 */ 449 break; 450 } 451 452 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0); 453 if (ret) 454 goto err; 455 456 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0); 457 if (ret) 458 goto err; 459 460 if (c->symbol_rate <= 3000000) 461 u8tmp = 0x20; 462 else if (c->symbol_rate <= 10000000) 463 u8tmp = 0x10; 464 else 465 u8tmp = 0x06; 466 467 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08); 468 if (ret) 469 goto err; 470 471 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp); 472 if (ret) 473 goto err; 474 475 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08); 476 if (ret) 477 goto err; 478 479 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00); 480 if (ret) 481 goto err; 482 483 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2); 484 buf[0] = (u16tmp >> 0) & 0xff; 485 buf[1] = (u16tmp >> 8) & 0xff; 486 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2); 487 if (ret) 488 goto err; 489 490 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02); 491 if (ret) 492 goto err; 493 494 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10); 495 if (ret) 496 goto err; 497 498 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc); 499 if (ret) 500 goto err; 501 502 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__, 503 (tuner_frequency - c->frequency)); 504 505 s32tmp = 0x10000 * (tuner_frequency - c->frequency); 506 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ); 507 if (s32tmp < 0) 508 s32tmp += 0x10000; 509 510 buf[0] = (s32tmp >> 0) & 0xff; 511 buf[1] = (s32tmp >> 8) & 0xff; 512 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2); 513 if (ret) 514 goto err; 515 516 ret = m88ds3103_wr_reg(priv, 0x00, 0x00); 517 if (ret) 518 goto err; 519 520 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 521 if (ret) 522 goto err; 523 524 priv->delivery_system = c->delivery_system; 525 526 return 0; 527 err: 528 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 529 return ret; 530 } 531 532 static int m88ds3103_init(struct dvb_frontend *fe) 533 { 534 struct m88ds3103_priv *priv = fe->demodulator_priv; 535 int ret, len, remaining; 536 const struct firmware *fw = NULL; 537 u8 *fw_file = M88DS3103_FIRMWARE; 538 u8 u8tmp; 539 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 540 541 /* set cold state by default */ 542 priv->warm = false; 543 544 /* wake up device from sleep */ 545 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01); 546 if (ret) 547 goto err; 548 549 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01); 550 if (ret) 551 goto err; 552 553 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10); 554 if (ret) 555 goto err; 556 557 /* reset */ 558 ret = m88ds3103_wr_reg(priv, 0x07, 0x60); 559 if (ret) 560 goto err; 561 562 ret = m88ds3103_wr_reg(priv, 0x07, 0x00); 563 if (ret) 564 goto err; 565 566 /* firmware status */ 567 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 568 if (ret) 569 goto err; 570 571 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp); 572 573 if (u8tmp) 574 goto skip_fw_download; 575 576 /* cold state - try to download firmware */ 577 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n", 578 KBUILD_MODNAME, m88ds3103_ops.info.name); 579 580 /* request the firmware, this will block and timeout */ 581 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); 582 if (ret) { 583 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n", 584 KBUILD_MODNAME, fw_file); 585 goto err; 586 } 587 588 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n", 589 KBUILD_MODNAME, fw_file); 590 591 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01); 592 if (ret) 593 goto err; 594 595 for (remaining = fw->size; remaining > 0; 596 remaining -= (priv->cfg->i2c_wr_max - 1)) { 597 len = remaining; 598 if (len > (priv->cfg->i2c_wr_max - 1)) 599 len = (priv->cfg->i2c_wr_max - 1); 600 601 ret = m88ds3103_wr_regs(priv, 0xb0, 602 &fw->data[fw->size - remaining], len); 603 if (ret) { 604 dev_err(&priv->i2c->dev, 605 "%s: firmware download failed=%d\n", 606 KBUILD_MODNAME, ret); 607 goto err; 608 } 609 } 610 611 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00); 612 if (ret) 613 goto err; 614 615 release_firmware(fw); 616 fw = NULL; 617 618 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp); 619 if (ret) 620 goto err; 621 622 if (!u8tmp) { 623 dev_info(&priv->i2c->dev, "%s: firmware did not run\n", 624 KBUILD_MODNAME); 625 ret = -EFAULT; 626 goto err; 627 } 628 629 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n", 630 KBUILD_MODNAME, m88ds3103_ops.info.name); 631 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n", 632 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf)); 633 634 skip_fw_download: 635 /* warm state */ 636 priv->warm = true; 637 638 return 0; 639 err: 640 if (fw) 641 release_firmware(fw); 642 643 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 644 return ret; 645 } 646 647 static int m88ds3103_sleep(struct dvb_frontend *fe) 648 { 649 struct m88ds3103_priv *priv = fe->demodulator_priv; 650 int ret; 651 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 652 653 priv->delivery_system = SYS_UNDEFINED; 654 655 /* TS Hi-Z */ 656 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01); 657 if (ret) 658 goto err; 659 660 /* sleep */ 661 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 662 if (ret) 663 goto err; 664 665 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 666 if (ret) 667 goto err; 668 669 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 670 if (ret) 671 goto err; 672 673 return 0; 674 err: 675 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 676 return ret; 677 } 678 679 static int m88ds3103_get_frontend(struct dvb_frontend *fe) 680 { 681 struct m88ds3103_priv *priv = fe->demodulator_priv; 682 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 683 int ret; 684 u8 buf[3]; 685 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 686 687 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) { 688 ret = -EAGAIN; 689 goto err; 690 } 691 692 switch (c->delivery_system) { 693 case SYS_DVBS: 694 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]); 695 if (ret) 696 goto err; 697 698 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]); 699 if (ret) 700 goto err; 701 702 switch ((buf[0] >> 2) & 0x01) { 703 case 0: 704 c->inversion = INVERSION_OFF; 705 break; 706 case 1: 707 c->inversion = INVERSION_ON; 708 break; 709 } 710 711 switch ((buf[1] >> 5) & 0x07) { 712 case 0: 713 c->fec_inner = FEC_7_8; 714 break; 715 case 1: 716 c->fec_inner = FEC_5_6; 717 break; 718 case 2: 719 c->fec_inner = FEC_3_4; 720 break; 721 case 3: 722 c->fec_inner = FEC_2_3; 723 break; 724 case 4: 725 c->fec_inner = FEC_1_2; 726 break; 727 default: 728 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 729 __func__); 730 } 731 732 c->modulation = QPSK; 733 734 break; 735 case SYS_DVBS2: 736 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]); 737 if (ret) 738 goto err; 739 740 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]); 741 if (ret) 742 goto err; 743 744 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]); 745 if (ret) 746 goto err; 747 748 switch ((buf[0] >> 0) & 0x0f) { 749 case 2: 750 c->fec_inner = FEC_2_5; 751 break; 752 case 3: 753 c->fec_inner = FEC_1_2; 754 break; 755 case 4: 756 c->fec_inner = FEC_3_5; 757 break; 758 case 5: 759 c->fec_inner = FEC_2_3; 760 break; 761 case 6: 762 c->fec_inner = FEC_3_4; 763 break; 764 case 7: 765 c->fec_inner = FEC_4_5; 766 break; 767 case 8: 768 c->fec_inner = FEC_5_6; 769 break; 770 case 9: 771 c->fec_inner = FEC_8_9; 772 break; 773 case 10: 774 c->fec_inner = FEC_9_10; 775 break; 776 default: 777 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n", 778 __func__); 779 } 780 781 switch ((buf[0] >> 5) & 0x01) { 782 case 0: 783 c->pilot = PILOT_OFF; 784 break; 785 case 1: 786 c->pilot = PILOT_ON; 787 break; 788 } 789 790 switch ((buf[0] >> 6) & 0x07) { 791 case 0: 792 c->modulation = QPSK; 793 break; 794 case 1: 795 c->modulation = PSK_8; 796 break; 797 case 2: 798 c->modulation = APSK_16; 799 break; 800 case 3: 801 c->modulation = APSK_32; 802 break; 803 default: 804 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n", 805 __func__); 806 } 807 808 switch ((buf[1] >> 7) & 0x01) { 809 case 0: 810 c->inversion = INVERSION_OFF; 811 break; 812 case 1: 813 c->inversion = INVERSION_ON; 814 break; 815 } 816 817 switch ((buf[2] >> 0) & 0x03) { 818 case 0: 819 c->rolloff = ROLLOFF_35; 820 break; 821 case 1: 822 c->rolloff = ROLLOFF_25; 823 break; 824 case 2: 825 c->rolloff = ROLLOFF_20; 826 break; 827 default: 828 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n", 829 __func__); 830 } 831 break; 832 default: 833 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 834 __func__); 835 ret = -EINVAL; 836 goto err; 837 } 838 839 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2); 840 if (ret) 841 goto err; 842 843 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) * 844 M88DS3103_MCLK_KHZ * 1000 / 0x10000; 845 846 return 0; 847 err: 848 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 849 return ret; 850 } 851 852 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) 853 { 854 struct m88ds3103_priv *priv = fe->demodulator_priv; 855 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 856 int ret, i, tmp; 857 u8 buf[3]; 858 u16 noise, signal; 859 u32 noise_tot, signal_tot; 860 dev_dbg(&priv->i2c->dev, "%s:\n", __func__); 861 /* reports SNR in resolution of 0.1 dB */ 862 863 /* more iterations for more accurate estimation */ 864 #define M88DS3103_SNR_ITERATIONS 3 865 866 switch (c->delivery_system) { 867 case SYS_DVBS: 868 tmp = 0; 869 870 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 871 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]); 872 if (ret) 873 goto err; 874 875 tmp += buf[0]; 876 } 877 878 /* use of one register limits max value to 15 dB */ 879 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ 880 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS); 881 if (tmp) 882 *snr = 100ul * intlog2(tmp) / intlog2(10); 883 else 884 *snr = 0; 885 break; 886 case SYS_DVBS2: 887 noise_tot = 0; 888 signal_tot = 0; 889 890 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 891 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3); 892 if (ret) 893 goto err; 894 895 noise = buf[1] << 6; /* [13:6] */ 896 noise |= buf[0] & 0x3f; /* [5:0] */ 897 noise >>= 2; 898 signal = buf[2] * buf[2]; 899 signal >>= 1; 900 901 noise_tot += noise; 902 signal_tot += signal; 903 } 904 905 noise = noise_tot / M88DS3103_SNR_ITERATIONS; 906 signal = signal_tot / M88DS3103_SNR_ITERATIONS; 907 908 /* SNR(X) dB = 10 * log10(X) dB */ 909 if (signal > noise) { 910 tmp = signal / noise; 911 *snr = 100ul * intlog10(tmp) / (1 << 24); 912 } else { 913 *snr = 0; 914 } 915 break; 916 default: 917 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n", 918 __func__); 919 ret = -EINVAL; 920 goto err; 921 } 922 923 return 0; 924 err: 925 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 926 return ret; 927 } 928 929 930 static int m88ds3103_set_tone(struct dvb_frontend *fe, 931 fe_sec_tone_mode_t fe_sec_tone_mode) 932 { 933 struct m88ds3103_priv *priv = fe->demodulator_priv; 934 int ret; 935 u8 u8tmp, tone, reg_a1_mask; 936 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__, 937 fe_sec_tone_mode); 938 939 if (!priv->warm) { 940 ret = -EAGAIN; 941 goto err; 942 } 943 944 switch (fe_sec_tone_mode) { 945 case SEC_TONE_ON: 946 tone = 0; 947 reg_a1_mask = 0x47; 948 break; 949 case SEC_TONE_OFF: 950 tone = 1; 951 reg_a1_mask = 0x00; 952 break; 953 default: 954 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n", 955 __func__); 956 ret = -EINVAL; 957 goto err; 958 } 959 960 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5; 961 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 962 if (ret) 963 goto err; 964 965 u8tmp = 1 << 2; 966 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask); 967 if (ret) 968 goto err; 969 970 return 0; 971 err: 972 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 973 return ret; 974 } 975 976 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, 977 struct dvb_diseqc_master_cmd *diseqc_cmd) 978 { 979 struct m88ds3103_priv *priv = fe->demodulator_priv; 980 int ret, i; 981 u8 u8tmp; 982 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__, 983 diseqc_cmd->msg_len, diseqc_cmd->msg); 984 985 if (!priv->warm) { 986 ret = -EAGAIN; 987 goto err; 988 } 989 990 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { 991 ret = -EINVAL; 992 goto err; 993 } 994 995 u8tmp = priv->cfg->envelope_mode << 5; 996 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 997 if (ret) 998 goto err; 999 1000 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg, 1001 diseqc_cmd->msg_len); 1002 if (ret) 1003 goto err; 1004 1005 ret = m88ds3103_wr_reg(priv, 0xa1, 1006 (diseqc_cmd->msg_len - 1) << 3 | 0x07); 1007 if (ret) 1008 goto err; 1009 1010 /* DiSEqC message typical period is 54 ms */ 1011 usleep_range(40000, 60000); 1012 1013 /* wait DiSEqC TX ready */ 1014 for (i = 20, u8tmp = 1; i && u8tmp; i--) { 1015 usleep_range(5000, 10000); 1016 1017 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1018 if (ret) 1019 goto err; 1020 } 1021 1022 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1023 1024 if (i == 0) { 1025 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1026 1027 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0); 1028 if (ret) 1029 goto err; 1030 } 1031 1032 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1033 if (ret) 1034 goto err; 1035 1036 if (i == 0) { 1037 ret = -ETIMEDOUT; 1038 goto err; 1039 } 1040 1041 return 0; 1042 err: 1043 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1044 return ret; 1045 } 1046 1047 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, 1048 fe_sec_mini_cmd_t fe_sec_mini_cmd) 1049 { 1050 struct m88ds3103_priv *priv = fe->demodulator_priv; 1051 int ret, i; 1052 u8 u8tmp, burst; 1053 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__, 1054 fe_sec_mini_cmd); 1055 1056 if (!priv->warm) { 1057 ret = -EAGAIN; 1058 goto err; 1059 } 1060 1061 u8tmp = priv->cfg->envelope_mode << 5; 1062 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0); 1063 if (ret) 1064 goto err; 1065 1066 switch (fe_sec_mini_cmd) { 1067 case SEC_MINI_A: 1068 burst = 0x02; 1069 break; 1070 case SEC_MINI_B: 1071 burst = 0x01; 1072 break; 1073 default: 1074 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n", 1075 __func__); 1076 ret = -EINVAL; 1077 goto err; 1078 } 1079 1080 ret = m88ds3103_wr_reg(priv, 0xa1, burst); 1081 if (ret) 1082 goto err; 1083 1084 /* DiSEqC ToneBurst period is 12.5 ms */ 1085 usleep_range(11000, 20000); 1086 1087 /* wait DiSEqC TX ready */ 1088 for (i = 5, u8tmp = 1; i && u8tmp; i--) { 1089 usleep_range(800, 2000); 1090 1091 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40); 1092 if (ret) 1093 goto err; 1094 } 1095 1096 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i); 1097 1098 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0); 1099 if (ret) 1100 goto err; 1101 1102 if (i == 0) { 1103 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__); 1104 ret = -ETIMEDOUT; 1105 goto err; 1106 } 1107 1108 return 0; 1109 err: 1110 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret); 1111 return ret; 1112 } 1113 1114 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, 1115 struct dvb_frontend_tune_settings *s) 1116 { 1117 s->min_delay_ms = 3000; 1118 1119 return 0; 1120 } 1121 1122 static void m88ds3103_release(struct dvb_frontend *fe) 1123 { 1124 struct m88ds3103_priv *priv = fe->demodulator_priv; 1125 i2c_del_mux_adapter(priv->i2c_adapter); 1126 kfree(priv); 1127 } 1128 1129 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) 1130 { 1131 struct m88ds3103_priv *priv = mux_priv; 1132 int ret; 1133 struct i2c_msg gate_open_msg[1] = { 1134 { 1135 .addr = priv->cfg->i2c_addr, 1136 .flags = 0, 1137 .len = 2, 1138 .buf = "\x03\x11", 1139 } 1140 }; 1141 1142 mutex_lock(&priv->i2c_mutex); 1143 1144 /* open tuner I2C repeater for 1 xfer, closes automatically */ 1145 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1); 1146 if (ret != 1) { 1147 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n", 1148 KBUILD_MODNAME, ret); 1149 if (ret >= 0) 1150 ret = -EREMOTEIO; 1151 1152 return ret; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv, 1159 u32 chan) 1160 { 1161 struct m88ds3103_priv *priv = mux_priv; 1162 1163 mutex_unlock(&priv->i2c_mutex); 1164 1165 return 0; 1166 } 1167 1168 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, 1169 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) 1170 { 1171 int ret; 1172 struct m88ds3103_priv *priv; 1173 u8 chip_id, u8tmp; 1174 1175 /* allocate memory for the internal priv */ 1176 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1177 if (!priv) { 1178 ret = -ENOMEM; 1179 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); 1180 goto err; 1181 } 1182 1183 priv->cfg = cfg; 1184 priv->i2c = i2c; 1185 mutex_init(&priv->i2c_mutex); 1186 1187 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id); 1188 if (ret) 1189 goto err; 1190 1191 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); 1192 1193 switch (chip_id) { 1194 case 0xd0: 1195 break; 1196 default: 1197 goto err; 1198 } 1199 1200 switch (priv->cfg->clock_out) { 1201 case M88DS3103_CLOCK_OUT_DISABLED: 1202 u8tmp = 0x80; 1203 break; 1204 case M88DS3103_CLOCK_OUT_ENABLED: 1205 u8tmp = 0x00; 1206 break; 1207 case M88DS3103_CLOCK_OUT_ENABLED_DIV2: 1208 u8tmp = 0x10; 1209 break; 1210 default: 1211 goto err; 1212 } 1213 1214 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp); 1215 if (ret) 1216 goto err; 1217 1218 /* sleep */ 1219 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01); 1220 if (ret) 1221 goto err; 1222 1223 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01); 1224 if (ret) 1225 goto err; 1226 1227 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10); 1228 if (ret) 1229 goto err; 1230 1231 /* create mux i2c adapter for tuner */ 1232 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0, 1233 m88ds3103_select, m88ds3103_deselect); 1234 if (priv->i2c_adapter == NULL) 1235 goto err; 1236 1237 *tuner_i2c_adapter = priv->i2c_adapter; 1238 1239 /* create dvb_frontend */ 1240 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); 1241 priv->fe.demodulator_priv = priv; 1242 1243 return &priv->fe; 1244 err: 1245 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret); 1246 kfree(priv); 1247 return NULL; 1248 } 1249 EXPORT_SYMBOL(m88ds3103_attach); 1250 1251 static struct dvb_frontend_ops m88ds3103_ops = { 1252 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1253 .info = { 1254 .name = "Montage M88DS3103", 1255 .frequency_min = 950000, 1256 .frequency_max = 2150000, 1257 .frequency_tolerance = 5000, 1258 .symbol_rate_min = 1000000, 1259 .symbol_rate_max = 45000000, 1260 .caps = FE_CAN_INVERSION_AUTO | 1261 FE_CAN_FEC_1_2 | 1262 FE_CAN_FEC_2_3 | 1263 FE_CAN_FEC_3_4 | 1264 FE_CAN_FEC_4_5 | 1265 FE_CAN_FEC_5_6 | 1266 FE_CAN_FEC_6_7 | 1267 FE_CAN_FEC_7_8 | 1268 FE_CAN_FEC_8_9 | 1269 FE_CAN_FEC_AUTO | 1270 FE_CAN_QPSK | 1271 FE_CAN_RECOVER | 1272 FE_CAN_2G_MODULATION 1273 }, 1274 1275 .release = m88ds3103_release, 1276 1277 .get_tune_settings = m88ds3103_get_tune_settings, 1278 1279 .init = m88ds3103_init, 1280 .sleep = m88ds3103_sleep, 1281 1282 .set_frontend = m88ds3103_set_frontend, 1283 .get_frontend = m88ds3103_get_frontend, 1284 1285 .read_status = m88ds3103_read_status, 1286 .read_snr = m88ds3103_read_snr, 1287 1288 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, 1289 .diseqc_send_burst = m88ds3103_diseqc_send_burst, 1290 1291 .set_tone = m88ds3103_set_tone, 1292 }; 1293 1294 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1295 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver"); 1296 MODULE_LICENSE("GPL"); 1297 MODULE_FIRMWARE(M88DS3103_FIRMWARE); 1298