1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Montage Technology M88DS3103/M88RS6000 demodulator driver
4  *
5  * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6  */
7 
8 #include "m88ds3103_priv.h"
9 
10 static const struct dvb_frontend_ops m88ds3103_ops;
11 
12 /* write single register with mask */
13 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
14 				u8 reg, u8 mask, u8 val)
15 {
16 	int ret;
17 	u8 tmp;
18 
19 	/* no need for read if whole reg is written */
20 	if (mask != 0xff) {
21 		ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
22 		if (ret)
23 			return ret;
24 
25 		val &= mask;
26 		tmp &= ~mask;
27 		val |= tmp;
28 	}
29 
30 	return regmap_bulk_write(dev->regmap, reg, &val, 1);
31 }
32 
33 /* write reg val table using reg addr auto increment */
34 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
35 		const struct m88ds3103_reg_val *tab, int tab_len)
36 {
37 	struct i2c_client *client = dev->client;
38 	int ret, i, j;
39 	u8 buf[83];
40 
41 	dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
42 
43 	if (tab_len > 86) {
44 		ret = -EINVAL;
45 		goto err;
46 	}
47 
48 	for (i = 0, j = 0; i < tab_len; i++, j++) {
49 		buf[j] = tab[i].val;
50 
51 		if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
52 				!((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
53 			ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
54 			if (ret)
55 				goto err;
56 
57 			j = -1;
58 		}
59 	}
60 
61 	return 0;
62 err:
63 	dev_dbg(&client->dev, "failed=%d\n", ret);
64 	return ret;
65 }
66 
67 /*
68  * m88ds3103b demod has an internal device related to clocking. First the i2c
69  * gate must be opened, for one transaction, then writes will be allowed.
70  */
71 static int m88ds3103b_dt_write(struct m88ds3103_dev *dev, int reg, int data)
72 {
73 	struct i2c_client *client = dev->client;
74 	u8 buf[] = {reg, data};
75 	u8 val;
76 	int ret;
77 	struct i2c_msg msg = {
78 		.addr = dev->dt_addr, .flags = 0, .buf = buf, .len = 2
79 	};
80 
81 	m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
82 
83 	val = 0x11;
84 	ret = regmap_write(dev->regmap, 0x03, val);
85 	if (ret)
86 		dev_dbg(&client->dev, "fail=%d\n", ret);
87 
88 	ret = i2c_transfer(dev->dt_client->adapter, &msg, 1);
89 	if (ret != 1) {
90 		dev_err(&client->dev, "0x%02x (ret=%i, reg=0x%02x, value=0x%02x)\n",
91 			dev->dt_addr, ret, reg, data);
92 
93 		m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
94 		return -EREMOTEIO;
95 	}
96 	m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
97 
98 	dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
99 		dev->dt_addr, reg, data);
100 
101 	return 0;
102 }
103 
104 /*
105  * m88ds3103b demod has an internal device related to clocking. First the i2c
106  * gate must be opened, for two transactions, then reads will be allowed.
107  */
108 static int m88ds3103b_dt_read(struct m88ds3103_dev *dev, u8 reg)
109 {
110 	struct i2c_client *client = dev->client;
111 	int ret;
112 	u8 val;
113 	u8 b0[] = { reg };
114 	u8 b1[] = { 0 };
115 	struct i2c_msg msg[] = {
116 		{
117 			.addr = dev->dt_addr,
118 			.flags = 0,
119 			.buf = b0,
120 			.len = 1
121 		},
122 		{
123 			.addr = dev->dt_addr,
124 			.flags = I2C_M_RD,
125 			.buf = b1,
126 			.len = 1
127 		}
128 	};
129 
130 	m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
131 
132 	val = 0x12;
133 	ret = regmap_write(dev->regmap, 0x03, val);
134 	if (ret)
135 		dev_dbg(&client->dev, "fail=%d\n", ret);
136 
137 	ret = i2c_transfer(dev->dt_client->adapter, msg, 2);
138 	if (ret != 2) {
139 		dev_err(&client->dev, "0x%02x (ret=%d, reg=0x%02x)\n",
140 			dev->dt_addr, ret, reg);
141 
142 		m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
143 		return -EREMOTEIO;
144 	}
145 	m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
146 
147 	dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
148 		dev->dt_addr, reg, b1[0]);
149 
150 	return b1[0];
151 }
152 
153 /*
154  * Get the demodulator AGC PWM voltage setting supplied to the tuner.
155  */
156 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
157 {
158 	struct m88ds3103_dev *dev = fe->demodulator_priv;
159 	unsigned tmp;
160 	int ret;
161 
162 	ret = regmap_read(dev->regmap, 0x3f, &tmp);
163 	if (ret == 0)
164 		*_agc_pwm = tmp;
165 	return ret;
166 }
167 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
168 
169 static int m88ds3103_read_status(struct dvb_frontend *fe,
170 				 enum fe_status *status)
171 {
172 	struct m88ds3103_dev *dev = fe->demodulator_priv;
173 	struct i2c_client *client = dev->client;
174 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
175 	int ret, i, itmp;
176 	unsigned int utmp;
177 	u8 buf[3];
178 
179 	*status = 0;
180 
181 	if (!dev->warm) {
182 		ret = -EAGAIN;
183 		goto err;
184 	}
185 
186 	switch (c->delivery_system) {
187 	case SYS_DVBS:
188 		ret = regmap_read(dev->regmap, 0xd1, &utmp);
189 		if (ret)
190 			goto err;
191 
192 		if ((utmp & 0x07) == 0x07)
193 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
194 					FE_HAS_VITERBI | FE_HAS_SYNC |
195 					FE_HAS_LOCK;
196 		break;
197 	case SYS_DVBS2:
198 		ret = regmap_read(dev->regmap, 0x0d, &utmp);
199 		if (ret)
200 			goto err;
201 
202 		if ((utmp & 0x8f) == 0x8f)
203 			*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
204 					FE_HAS_VITERBI | FE_HAS_SYNC |
205 					FE_HAS_LOCK;
206 		break;
207 	default:
208 		dev_dbg(&client->dev, "invalid delivery_system\n");
209 		ret = -EINVAL;
210 		goto err;
211 	}
212 
213 	dev->fe_status = *status;
214 	dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
215 
216 	/* CNR */
217 	if (dev->fe_status & FE_HAS_VITERBI) {
218 		unsigned int cnr, noise, signal, noise_tot, signal_tot;
219 
220 		cnr = 0;
221 		/* more iterations for more accurate estimation */
222 		#define M88DS3103_SNR_ITERATIONS 3
223 
224 		switch (c->delivery_system) {
225 		case SYS_DVBS:
226 			itmp = 0;
227 
228 			for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
229 				ret = regmap_read(dev->regmap, 0xff, &utmp);
230 				if (ret)
231 					goto err;
232 
233 				itmp += utmp;
234 			}
235 
236 			/* use of single register limits max value to 15 dB */
237 			/* SNR(X) dB = 10 * ln(X) / ln(10) dB */
238 			itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
239 			if (itmp)
240 				cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
241 			break;
242 		case SYS_DVBS2:
243 			noise_tot = 0;
244 			signal_tot = 0;
245 
246 			for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
247 				ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
248 				if (ret)
249 					goto err;
250 
251 				noise = buf[1] << 6;    /* [13:6] */
252 				noise |= buf[0] & 0x3f; /*  [5:0] */
253 				noise >>= 2;
254 				signal = buf[2] * buf[2];
255 				signal >>= 1;
256 
257 				noise_tot += noise;
258 				signal_tot += signal;
259 			}
260 
261 			noise = noise_tot / M88DS3103_SNR_ITERATIONS;
262 			signal = signal_tot / M88DS3103_SNR_ITERATIONS;
263 
264 			/* SNR(X) dB = 10 * log10(X) dB */
265 			if (signal > noise) {
266 				itmp = signal / noise;
267 				cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
268 			}
269 			break;
270 		default:
271 			dev_dbg(&client->dev, "invalid delivery_system\n");
272 			ret = -EINVAL;
273 			goto err;
274 		}
275 
276 		if (cnr) {
277 			c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
278 			c->cnr.stat[0].svalue = cnr;
279 		} else {
280 			c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
281 		}
282 	} else {
283 		c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
284 	}
285 
286 	/* BER */
287 	if (dev->fe_status & FE_HAS_LOCK) {
288 		unsigned int utmp, post_bit_error, post_bit_count;
289 
290 		switch (c->delivery_system) {
291 		case SYS_DVBS:
292 			ret = regmap_write(dev->regmap, 0xf9, 0x04);
293 			if (ret)
294 				goto err;
295 
296 			ret = regmap_read(dev->regmap, 0xf8, &utmp);
297 			if (ret)
298 				goto err;
299 
300 			/* measurement ready? */
301 			if (!(utmp & 0x10)) {
302 				ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
303 				if (ret)
304 					goto err;
305 
306 				post_bit_error = buf[1] << 8 | buf[0] << 0;
307 				post_bit_count = 0x800000;
308 				dev->post_bit_error += post_bit_error;
309 				dev->post_bit_count += post_bit_count;
310 				dev->dvbv3_ber = post_bit_error;
311 
312 				/* restart measurement */
313 				utmp |= 0x10;
314 				ret = regmap_write(dev->regmap, 0xf8, utmp);
315 				if (ret)
316 					goto err;
317 			}
318 			break;
319 		case SYS_DVBS2:
320 			ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
321 			if (ret)
322 				goto err;
323 
324 			utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
325 
326 			/* enough data? */
327 			if (utmp > 4000) {
328 				ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
329 				if (ret)
330 					goto err;
331 
332 				post_bit_error = buf[1] << 8 | buf[0] << 0;
333 				post_bit_count = 32 * utmp; /* TODO: FEC */
334 				dev->post_bit_error += post_bit_error;
335 				dev->post_bit_count += post_bit_count;
336 				dev->dvbv3_ber = post_bit_error;
337 
338 				/* restart measurement */
339 				ret = regmap_write(dev->regmap, 0xd1, 0x01);
340 				if (ret)
341 					goto err;
342 
343 				ret = regmap_write(dev->regmap, 0xf9, 0x01);
344 				if (ret)
345 					goto err;
346 
347 				ret = regmap_write(dev->regmap, 0xf9, 0x00);
348 				if (ret)
349 					goto err;
350 
351 				ret = regmap_write(dev->regmap, 0xd1, 0x00);
352 				if (ret)
353 					goto err;
354 			}
355 			break;
356 		default:
357 			dev_dbg(&client->dev, "invalid delivery_system\n");
358 			ret = -EINVAL;
359 			goto err;
360 		}
361 
362 		c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
363 		c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
364 		c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
365 		c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
366 	} else {
367 		c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
368 		c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
369 	}
370 
371 	return 0;
372 err:
373 	dev_dbg(&client->dev, "failed=%d\n", ret);
374 	return ret;
375 }
376 
377 static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev)
378 {
379 	struct i2c_client *client = dev->client;
380 	struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
381 	u32 adc_Freq_MHz[3] = {96, 93, 99};
382 	u8  reg16_list[3] = {96, 92, 100}, reg16, reg15;
383 	u32 offset_MHz[3];
384 	u32 max_offset = 0;
385 	u32 old_setting = dev->mclk;
386 	u32 tuner_freq_MHz = c->frequency / 1000;
387 	u8 i;
388 	char big_symbol = 0;
389 
390 	big_symbol = (c->symbol_rate > 45010000) ? 1 : 0;
391 
392 	if (big_symbol) {
393 		reg16 = 115;
394 	} else {
395 		reg16 = 96;
396 
397 		/* TODO: IS THIS NECESSARY ? */
398 		for (i = 0; i < 3; i++) {
399 			offset_MHz[i] = tuner_freq_MHz % adc_Freq_MHz[i];
400 
401 			if (offset_MHz[i] > (adc_Freq_MHz[i] / 2))
402 				offset_MHz[i] = adc_Freq_MHz[i] - offset_MHz[i];
403 
404 			if (offset_MHz[i] > max_offset) {
405 				max_offset = offset_MHz[i];
406 				reg16 = reg16_list[i];
407 				dev->mclk = adc_Freq_MHz[i] * 1000 * 1000;
408 
409 				if (big_symbol)
410 					dev->mclk /= 2;
411 
412 				dev_dbg(&client->dev, "modifying mclk %u -> %u\n",
413 					old_setting, dev->mclk);
414 			}
415 		}
416 	}
417 
418 	if (dev->mclk == 93000000)
419 		regmap_write(dev->regmap, 0xA0, 0x42);
420 	else if (dev->mclk == 96000000)
421 		regmap_write(dev->regmap, 0xA0, 0x44);
422 	else if (dev->mclk == 99000000)
423 		regmap_write(dev->regmap, 0xA0, 0x46);
424 	else if (dev->mclk == 110250000)
425 		regmap_write(dev->regmap, 0xA0, 0x4E);
426 	else
427 		regmap_write(dev->regmap, 0xA0, 0x44);
428 
429 	reg15 = m88ds3103b_dt_read(dev, 0x15);
430 
431 	m88ds3103b_dt_write(dev, 0x05, 0x40);
432 	m88ds3103b_dt_write(dev, 0x11, 0x08);
433 
434 	if (big_symbol)
435 		reg15 |= 0x02;
436 	else
437 		reg15 &= ~0x02;
438 
439 	m88ds3103b_dt_write(dev, 0x15, reg15);
440 	m88ds3103b_dt_write(dev, 0x16, reg16);
441 
442 	usleep_range(5000, 5500);
443 
444 	m88ds3103b_dt_write(dev, 0x05, 0x00);
445 	m88ds3103b_dt_write(dev, 0x11, (u8)(big_symbol ? 0x0E : 0x0A));
446 
447 	usleep_range(5000, 5500);
448 
449 	return 0;
450 }
451 
452 static int m88ds3103b_set_mclk(struct m88ds3103_dev *dev, u32 mclk_khz)
453 {
454 	u8 reg11 = 0x0A, reg15, reg16, reg1D, reg1E, reg1F, tmp;
455 	u8 sm, f0 = 0, f1 = 0, f2 = 0, f3 = 0;
456 	u16 pll_div_fb, N;
457 	u32 div;
458 
459 	reg15 = m88ds3103b_dt_read(dev, 0x15);
460 	reg16 = m88ds3103b_dt_read(dev, 0x16);
461 	reg1D = m88ds3103b_dt_read(dev, 0x1D);
462 
463 	if (dev->cfg->ts_mode != M88DS3103_TS_SERIAL) {
464 		if (reg16 == 92)
465 			tmp = 93;
466 		else if (reg16 == 100)
467 			tmp = 99;
468 		else
469 			tmp = 96;
470 
471 		mclk_khz *= tmp;
472 		mclk_khz /= 96;
473 	}
474 
475 	pll_div_fb = (reg15 & 0x01) << 8;
476 	pll_div_fb += reg16;
477 	pll_div_fb += 32;
478 
479 	div = 9000 * pll_div_fb * 4;
480 	div /= mclk_khz;
481 
482 	if (dev->cfg->ts_mode == M88DS3103_TS_SERIAL) {
483 		reg11 |= 0x02;
484 
485 		if (div <= 32) {
486 			N = 2;
487 
488 			f0 = 0;
489 			f1 = div / N;
490 			f2 = div - f1;
491 			f3 = 0;
492 		} else if (div <= 34) {
493 			N = 3;
494 
495 			f0 = div / N;
496 			f1 = (div - f0) / (N - 1);
497 			f2 = div - f0 - f1;
498 			f3 = 0;
499 		} else if (div <= 64) {
500 			N = 4;
501 
502 			f0 = div / N;
503 			f1 = (div - f0) / (N - 1);
504 			f2 = (div - f0 - f1) / (N - 2);
505 			f3 = div - f0 - f1 - f2;
506 		} else {
507 			N = 4;
508 
509 			f0 = 16;
510 			f1 = 16;
511 			f2 = 16;
512 			f3 = 16;
513 		}
514 
515 		if (f0 == 16)
516 			f0 = 0;
517 		else if ((f0 < 8) && (f0 != 0))
518 			f0 = 8;
519 
520 		if (f1 == 16)
521 			f1 = 0;
522 		else if ((f1 < 8) && (f1 != 0))
523 			f1 = 8;
524 
525 		if (f2 == 16)
526 			f2 = 0;
527 		else if ((f2 < 8) && (f2 != 0))
528 			f2 = 8;
529 
530 		if (f3 == 16)
531 			f3 = 0;
532 		else if ((f3 < 8) && (f3 != 0))
533 			f3 = 8;
534 	} else {
535 		reg11 &= ~0x02;
536 
537 		if (div <= 32) {
538 			N = 2;
539 
540 			f0 = 0;
541 			f1 = div / N;
542 			f2 = div - f1;
543 			f3 = 0;
544 		} else if (div <= 48) {
545 			N = 3;
546 
547 			f0 = div / N;
548 			f1 = (div - f0) / (N - 1);
549 			f2 = div - f0 - f1;
550 			f3 = 0;
551 		} else if (div <= 64) {
552 			N = 4;
553 
554 			f0 = div / N;
555 			f1 = (div - f0) / (N - 1);
556 			f2 = (div - f0 - f1) / (N - 2);
557 			f3 = div - f0 - f1 - f2;
558 		} else {
559 			N = 4;
560 
561 			f0 = 16;
562 			f1 = 16;
563 			f2 = 16;
564 			f3 = 16;
565 		}
566 
567 		if (f0 == 16)
568 			f0 = 0;
569 		else if ((f0 < 9) && (f0 != 0))
570 			f0 = 9;
571 
572 		if (f1 == 16)
573 			f1 = 0;
574 		else if ((f1 < 9) && (f1 != 0))
575 			f1 = 9;
576 
577 		if (f2 == 16)
578 			f2 = 0;
579 		else if ((f2 < 9) && (f2 != 0))
580 			f2 = 9;
581 
582 		if (f3 == 16)
583 			f3 = 0;
584 		else if ((f3 < 9) && (f3 != 0))
585 			f3 = 9;
586 	}
587 
588 	sm = N - 1;
589 
590 	/* Write to registers */
591 	//reg15 &= 0x01;
592 	//reg15 |= (pll_div_fb >> 8) & 0x01;
593 
594 	//reg16 = pll_div_fb & 0xFF;
595 
596 	reg1D &= ~0x03;
597 	reg1D |= sm;
598 	reg1D |= 0x80;
599 
600 	reg1E = ((f3 << 4) + f2) & 0xFF;
601 	reg1F = ((f1 << 4) + f0) & 0xFF;
602 
603 	m88ds3103b_dt_write(dev, 0x05, 0x40);
604 	m88ds3103b_dt_write(dev, 0x11, 0x08);
605 	m88ds3103b_dt_write(dev, 0x1D, reg1D);
606 	m88ds3103b_dt_write(dev, 0x1E, reg1E);
607 	m88ds3103b_dt_write(dev, 0x1F, reg1F);
608 
609 	m88ds3103b_dt_write(dev, 0x17, 0xc1);
610 	m88ds3103b_dt_write(dev, 0x17, 0x81);
611 
612 	usleep_range(5000, 5500);
613 
614 	m88ds3103b_dt_write(dev, 0x05, 0x00);
615 	m88ds3103b_dt_write(dev, 0x11, 0x0A);
616 
617 	usleep_range(5000, 5500);
618 
619 	return 0;
620 }
621 
622 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
623 {
624 	struct m88ds3103_dev *dev = fe->demodulator_priv;
625 	struct i2c_client *client = dev->client;
626 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
627 	int ret, len;
628 	const struct m88ds3103_reg_val *init;
629 	u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
630 	u8 buf[3];
631 	u16 u16tmp;
632 	u32 tuner_frequency_khz, target_mclk, u32tmp;
633 	s32 s32tmp;
634 	static const struct reg_sequence reset_buf[] = {
635 		{0x07, 0x80}, {0x07, 0x00}
636 	};
637 
638 	dev_dbg(&client->dev,
639 		"delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
640 		c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
641 		c->inversion, c->pilot, c->rolloff);
642 
643 	if (!dev->warm) {
644 		ret = -EAGAIN;
645 		goto err;
646 	}
647 
648 	/* reset */
649 	ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2);
650 	if (ret)
651 		goto err;
652 
653 	/* Disable demod clock path */
654 	if (dev->chip_id == M88RS6000_CHIP_ID) {
655 		if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
656 			ret = regmap_read(dev->regmap, 0xb2, &u32tmp);
657 			if (ret)
658 				goto err;
659 			if (u32tmp == 0x01) {
660 				ret = regmap_write(dev->regmap, 0x00, 0x00);
661 				if (ret)
662 					goto err;
663 				ret = regmap_write(dev->regmap, 0xb2, 0x00);
664 				if (ret)
665 					goto err;
666 			}
667 		}
668 
669 		ret = regmap_write(dev->regmap, 0x06, 0xe0);
670 		if (ret)
671 			goto err;
672 	}
673 
674 	/* program tuner */
675 	if (fe->ops.tuner_ops.set_params) {
676 		ret = fe->ops.tuner_ops.set_params(fe);
677 		if (ret)
678 			goto err;
679 	}
680 
681 	if (fe->ops.tuner_ops.get_frequency) {
682 		ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz);
683 		if (ret)
684 			goto err;
685 	} else {
686 		/*
687 		 * Use nominal target frequency as tuner driver does not provide
688 		 * actual frequency used. Carrier offset calculation is not
689 		 * valid.
690 		 */
691 		tuner_frequency_khz = c->frequency;
692 	}
693 
694 	/* set M88RS6000/DS3103B demod main mclk and ts mclk from tuner die */
695 	if (dev->chip_id == M88RS6000_CHIP_ID) {
696 		if (c->symbol_rate > 45010000)
697 			dev->mclk = 110250000;
698 		else
699 			dev->mclk = 96000000;
700 
701 		if (c->delivery_system == SYS_DVBS)
702 			target_mclk = 96000000;
703 		else
704 			target_mclk = 144000000;
705 
706 		if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
707 			m88ds3103b_select_mclk(dev);
708 			m88ds3103b_set_mclk(dev, target_mclk / 1000);
709 		}
710 
711 		/* Enable demod clock path */
712 		ret = regmap_write(dev->regmap, 0x06, 0x00);
713 		if (ret)
714 			goto err;
715 		usleep_range(10000, 20000);
716 	} else {
717 	/* set M88DS3103 mclk and ts mclk. */
718 		dev->mclk = 96000000;
719 
720 		switch (dev->cfg->ts_mode) {
721 		case M88DS3103_TS_SERIAL:
722 		case M88DS3103_TS_SERIAL_D7:
723 			target_mclk = dev->cfg->ts_clk;
724 			break;
725 		case M88DS3103_TS_PARALLEL:
726 		case M88DS3103_TS_CI:
727 			if (c->delivery_system == SYS_DVBS)
728 				target_mclk = 96000000;
729 			else {
730 				if (c->symbol_rate < 18000000)
731 					target_mclk = 96000000;
732 				else if (c->symbol_rate < 28000000)
733 					target_mclk = 144000000;
734 				else
735 					target_mclk = 192000000;
736 			}
737 			break;
738 		default:
739 			dev_dbg(&client->dev, "invalid ts_mode\n");
740 			ret = -EINVAL;
741 			goto err;
742 		}
743 
744 		switch (target_mclk) {
745 		case 96000000:
746 			u8tmp1 = 0x02; /* 0b10 */
747 			u8tmp2 = 0x01; /* 0b01 */
748 			break;
749 		case 144000000:
750 			u8tmp1 = 0x00; /* 0b00 */
751 			u8tmp2 = 0x01; /* 0b01 */
752 			break;
753 		case 192000000:
754 			u8tmp1 = 0x03; /* 0b11 */
755 			u8tmp2 = 0x00; /* 0b00 */
756 			break;
757 		}
758 		ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
759 		if (ret)
760 			goto err;
761 		ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
762 		if (ret)
763 			goto err;
764 	}
765 
766 	ret = regmap_write(dev->regmap, 0xb2, 0x01);
767 	if (ret)
768 		goto err;
769 
770 	ret = regmap_write(dev->regmap, 0x00, 0x01);
771 	if (ret)
772 		goto err;
773 
774 	switch (c->delivery_system) {
775 	case SYS_DVBS:
776 		if (dev->chip_id == M88RS6000_CHIP_ID) {
777 			len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
778 			init = m88rs6000_dvbs_init_reg_vals;
779 		} else {
780 			len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
781 			init = m88ds3103_dvbs_init_reg_vals;
782 		}
783 		break;
784 	case SYS_DVBS2:
785 		if (dev->chip_id == M88RS6000_CHIP_ID) {
786 			len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
787 			init = m88rs6000_dvbs2_init_reg_vals;
788 		} else {
789 			len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
790 			init = m88ds3103_dvbs2_init_reg_vals;
791 		}
792 		break;
793 	default:
794 		dev_dbg(&client->dev, "invalid delivery_system\n");
795 		ret = -EINVAL;
796 		goto err;
797 	}
798 
799 	/* program init table */
800 	if (c->delivery_system != dev->delivery_system) {
801 		ret = m88ds3103_wr_reg_val_tab(dev, init, len);
802 		if (ret)
803 			goto err;
804 	}
805 
806 	if (dev->chip_id == M88RS6000_CHIP_ID) {
807 		if (c->delivery_system == SYS_DVBS2 &&
808 		    c->symbol_rate <= 5000000) {
809 			ret = regmap_write(dev->regmap, 0xc0, 0x04);
810 			if (ret)
811 				goto err;
812 			buf[0] = 0x09;
813 			buf[1] = 0x22;
814 			buf[2] = 0x88;
815 			ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
816 			if (ret)
817 				goto err;
818 		}
819 		ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
820 		if (ret)
821 			goto err;
822 
823 		if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
824 			buf[0] = m88ds3103b_dt_read(dev, 0x15);
825 			buf[1] = m88ds3103b_dt_read(dev, 0x16);
826 
827 			if (c->symbol_rate > 45010000) {
828 				buf[0] &= ~0x03;
829 				buf[0] |= 0x02;
830 				buf[0] |= ((147 - 32) >> 8) & 0x01;
831 				buf[1] = (147 - 32) & 0xFF;
832 
833 				dev->mclk = 110250 * 1000;
834 			} else {
835 				buf[0] &= ~0x03;
836 				buf[0] |= ((128 - 32) >> 8) & 0x01;
837 				buf[1] = (128 - 32) & 0xFF;
838 
839 				dev->mclk = 96000 * 1000;
840 			}
841 			m88ds3103b_dt_write(dev, 0x15, buf[0]);
842 			m88ds3103b_dt_write(dev, 0x16, buf[1]);
843 
844 			regmap_read(dev->regmap, 0x30, &u32tmp);
845 			u32tmp &= ~0x80;
846 			regmap_write(dev->regmap, 0x30, u32tmp & 0xff);
847 		}
848 
849 		ret = regmap_write(dev->regmap, 0xf1, 0x01);
850 		if (ret)
851 			goto err;
852 
853 		if (dev->chiptype != M88DS3103_CHIPTYPE_3103B) {
854 			ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
855 			if (ret)
856 				goto err;
857 		}
858 	}
859 
860 	switch (dev->cfg->ts_mode) {
861 	case M88DS3103_TS_SERIAL:
862 		u8tmp1 = 0x00;
863 		u8tmp = 0x06;
864 		break;
865 	case M88DS3103_TS_SERIAL_D7:
866 		u8tmp1 = 0x20;
867 		u8tmp = 0x06;
868 		break;
869 	case M88DS3103_TS_PARALLEL:
870 		u8tmp = 0x02;
871 		if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
872 			u8tmp = 0x01;
873 			u8tmp1 = 0x01;
874 		}
875 		break;
876 	case M88DS3103_TS_CI:
877 		u8tmp = 0x03;
878 		break;
879 	default:
880 		dev_dbg(&client->dev, "invalid ts_mode\n");
881 		ret = -EINVAL;
882 		goto err;
883 	}
884 
885 	if (dev->cfg->ts_clk_pol)
886 		u8tmp |= 0x40;
887 
888 	/* TS mode */
889 	ret = regmap_write(dev->regmap, 0xfd, u8tmp);
890 	if (ret)
891 		goto err;
892 
893 	switch (dev->cfg->ts_mode) {
894 	case M88DS3103_TS_SERIAL:
895 	case M88DS3103_TS_SERIAL_D7:
896 		ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
897 		if (ret)
898 			goto err;
899 		u16tmp = 0;
900 		u8tmp1 = 0x3f;
901 		u8tmp2 = 0x3f;
902 		break;
903 	case M88DS3103_TS_PARALLEL:
904 		if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
905 			ret = m88ds3103_update_bits(dev, 0x29, 0x01, u8tmp1);
906 			if (ret)
907 				goto err;
908 		}
909 		/* fall through */
910 	default:
911 		u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
912 		u8tmp1 = u16tmp / 2 - 1;
913 		u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
914 	}
915 
916 	dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
917 		target_mclk, dev->cfg->ts_clk, u16tmp);
918 
919 	/* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
920 	/* u8tmp2[5:0] => ea[5:0] */
921 	u8tmp = (u8tmp1 >> 2) & 0x0f;
922 	ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
923 	if (ret)
924 		goto err;
925 	u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
926 	ret = regmap_write(dev->regmap, 0xea, u8tmp);
927 	if (ret)
928 		goto err;
929 
930 	if (c->symbol_rate <= 3000000)
931 		u8tmp = 0x20;
932 	else if (c->symbol_rate <= 10000000)
933 		u8tmp = 0x10;
934 	else
935 		u8tmp = 0x06;
936 
937 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
938 		m88ds3103b_set_mclk(dev, target_mclk / 1000);
939 
940 	ret = regmap_write(dev->regmap, 0xc3, 0x08);
941 	if (ret)
942 		goto err;
943 
944 	ret = regmap_write(dev->regmap, 0xc8, u8tmp);
945 	if (ret)
946 		goto err;
947 
948 	ret = regmap_write(dev->regmap, 0xc4, 0x08);
949 	if (ret)
950 		goto err;
951 
952 	ret = regmap_write(dev->regmap, 0xc7, 0x00);
953 	if (ret)
954 		goto err;
955 
956 	u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk);
957 	buf[0] = (u16tmp >> 0) & 0xff;
958 	buf[1] = (u16tmp >> 8) & 0xff;
959 	ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
960 	if (ret)
961 		goto err;
962 
963 	ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
964 	if (ret)
965 		goto err;
966 
967 	ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
968 	if (ret)
969 		goto err;
970 
971 	ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
972 	if (ret)
973 		goto err;
974 
975 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
976 		/* enable/disable 192M LDPC clock */
977 		ret = m88ds3103_update_bits(dev, 0x29, 0x10,
978 				(c->delivery_system == SYS_DVBS) ? 0x10 : 0x0);
979 		if (ret)
980 			goto err;
981 
982 		ret = m88ds3103_update_bits(dev, 0xc9, 0x08, 0x08);
983 		if (ret)
984 			goto err;
985 	}
986 
987 	dev_dbg(&client->dev, "carrier offset=%d\n",
988 		(tuner_frequency_khz - c->frequency));
989 
990 	/* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */
991 	s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency);
992 	s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000);
993 	buf[0] = (s32tmp >> 0) & 0xff;
994 	buf[1] = (s32tmp >> 8) & 0xff;
995 	ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
996 	if (ret)
997 		goto err;
998 
999 	ret = regmap_write(dev->regmap, 0x00, 0x00);
1000 	if (ret)
1001 		goto err;
1002 
1003 	ret = regmap_write(dev->regmap, 0xb2, 0x00);
1004 	if (ret)
1005 		goto err;
1006 
1007 	dev->delivery_system = c->delivery_system;
1008 
1009 	return 0;
1010 err:
1011 	dev_dbg(&client->dev, "failed=%d\n", ret);
1012 	return ret;
1013 }
1014 
1015 static int m88ds3103_init(struct dvb_frontend *fe)
1016 {
1017 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1018 	struct i2c_client *client = dev->client;
1019 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1020 	int ret, len, rem;
1021 	unsigned int utmp;
1022 	const struct firmware *firmware;
1023 	const char *name;
1024 
1025 	dev_dbg(&client->dev, "\n");
1026 
1027 	/* set cold state by default */
1028 	dev->warm = false;
1029 
1030 	/* wake up device from sleep */
1031 	ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
1032 	if (ret)
1033 		goto err;
1034 	ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
1035 	if (ret)
1036 		goto err;
1037 	ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
1038 	if (ret)
1039 		goto err;
1040 
1041 	/* firmware status */
1042 	ret = regmap_read(dev->regmap, 0xb9, &utmp);
1043 	if (ret)
1044 		goto err;
1045 
1046 	dev_dbg(&client->dev, "firmware=%02x\n", utmp);
1047 
1048 	if (utmp)
1049 		goto warm;
1050 
1051 	/* global reset, global diseqc reset, global fec reset */
1052 	ret = regmap_write(dev->regmap, 0x07, 0xe0);
1053 	if (ret)
1054 		goto err;
1055 	ret = regmap_write(dev->regmap, 0x07, 0x00);
1056 	if (ret)
1057 		goto err;
1058 
1059 	/* cold state - try to download firmware */
1060 	dev_info(&client->dev, "found a '%s' in cold state\n",
1061 		 dev->fe.ops.info.name);
1062 
1063 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
1064 		name = M88DS3103B_FIRMWARE;
1065 	else if (dev->chip_id == M88RS6000_CHIP_ID)
1066 		name = M88RS6000_FIRMWARE;
1067 	else
1068 		name = M88DS3103_FIRMWARE;
1069 
1070 	/* request the firmware, this will block and timeout */
1071 	ret = request_firmware(&firmware, name, &client->dev);
1072 	if (ret) {
1073 		dev_err(&client->dev, "firmware file '%s' not found\n", name);
1074 		goto err;
1075 	}
1076 
1077 	dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
1078 
1079 	ret = regmap_write(dev->regmap, 0xb2, 0x01);
1080 	if (ret)
1081 		goto err_release_firmware;
1082 
1083 	for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) {
1084 		len = min(dev->cfg->i2c_wr_max - 1, rem);
1085 		ret = regmap_bulk_write(dev->regmap, 0xb0,
1086 					&firmware->data[firmware->size - rem],
1087 					len);
1088 		if (ret) {
1089 			dev_err(&client->dev, "firmware download failed %d\n",
1090 				ret);
1091 			goto err_release_firmware;
1092 		}
1093 	}
1094 
1095 	ret = regmap_write(dev->regmap, 0xb2, 0x00);
1096 	if (ret)
1097 		goto err_release_firmware;
1098 
1099 	release_firmware(firmware);
1100 
1101 	ret = regmap_read(dev->regmap, 0xb9, &utmp);
1102 	if (ret)
1103 		goto err;
1104 
1105 	if (!utmp) {
1106 		ret = -EINVAL;
1107 		dev_info(&client->dev, "firmware did not run\n");
1108 		goto err;
1109 	}
1110 
1111 	dev_info(&client->dev, "found a '%s' in warm state\n",
1112 		 dev->fe.ops.info.name);
1113 	dev_info(&client->dev, "firmware version: %X.%X\n",
1114 		 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
1115 
1116 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
1117 		m88ds3103b_dt_write(dev, 0x21, 0x92);
1118 		m88ds3103b_dt_write(dev, 0x15, 0x6C);
1119 		m88ds3103b_dt_write(dev, 0x17, 0xC1);
1120 		m88ds3103b_dt_write(dev, 0x17, 0x81);
1121 	}
1122 warm:
1123 	/* warm state */
1124 	dev->warm = true;
1125 
1126 	/* init stats here in order signal app which stats are supported */
1127 	c->cnr.len = 1;
1128 	c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1129 	c->post_bit_error.len = 1;
1130 	c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1131 	c->post_bit_count.len = 1;
1132 	c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1133 
1134 	return 0;
1135 err_release_firmware:
1136 	release_firmware(firmware);
1137 err:
1138 	dev_dbg(&client->dev, "failed=%d\n", ret);
1139 	return ret;
1140 }
1141 
1142 static int m88ds3103_sleep(struct dvb_frontend *fe)
1143 {
1144 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1145 	struct i2c_client *client = dev->client;
1146 	int ret;
1147 	unsigned int utmp;
1148 
1149 	dev_dbg(&client->dev, "\n");
1150 
1151 	dev->fe_status = 0;
1152 	dev->delivery_system = SYS_UNDEFINED;
1153 
1154 	/* TS Hi-Z */
1155 	if (dev->chip_id == M88RS6000_CHIP_ID)
1156 		utmp = 0x29;
1157 	else
1158 		utmp = 0x27;
1159 	ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
1160 	if (ret)
1161 		goto err;
1162 
1163 	/* sleep */
1164 	ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1165 	if (ret)
1166 		goto err;
1167 	ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1168 	if (ret)
1169 		goto err;
1170 	ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1171 	if (ret)
1172 		goto err;
1173 
1174 	return 0;
1175 err:
1176 	dev_dbg(&client->dev, "failed=%d\n", ret);
1177 	return ret;
1178 }
1179 
1180 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
1181 				  struct dtv_frontend_properties *c)
1182 {
1183 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1184 	struct i2c_client *client = dev->client;
1185 	int ret;
1186 	u8 buf[3];
1187 
1188 	dev_dbg(&client->dev, "\n");
1189 
1190 	if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
1191 		ret = 0;
1192 		goto err;
1193 	}
1194 
1195 	switch (c->delivery_system) {
1196 	case SYS_DVBS:
1197 		ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
1198 		if (ret)
1199 			goto err;
1200 
1201 		ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
1202 		if (ret)
1203 			goto err;
1204 
1205 		switch ((buf[0] >> 2) & 0x01) {
1206 		case 0:
1207 			c->inversion = INVERSION_OFF;
1208 			break;
1209 		case 1:
1210 			c->inversion = INVERSION_ON;
1211 			break;
1212 		}
1213 
1214 		switch ((buf[1] >> 5) & 0x07) {
1215 		case 0:
1216 			c->fec_inner = FEC_7_8;
1217 			break;
1218 		case 1:
1219 			c->fec_inner = FEC_5_6;
1220 			break;
1221 		case 2:
1222 			c->fec_inner = FEC_3_4;
1223 			break;
1224 		case 3:
1225 			c->fec_inner = FEC_2_3;
1226 			break;
1227 		case 4:
1228 			c->fec_inner = FEC_1_2;
1229 			break;
1230 		default:
1231 			dev_dbg(&client->dev, "invalid fec_inner\n");
1232 		}
1233 
1234 		c->modulation = QPSK;
1235 
1236 		break;
1237 	case SYS_DVBS2:
1238 		ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
1239 		if (ret)
1240 			goto err;
1241 
1242 		ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
1243 		if (ret)
1244 			goto err;
1245 
1246 		ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
1247 		if (ret)
1248 			goto err;
1249 
1250 		switch ((buf[0] >> 0) & 0x0f) {
1251 		case 2:
1252 			c->fec_inner = FEC_2_5;
1253 			break;
1254 		case 3:
1255 			c->fec_inner = FEC_1_2;
1256 			break;
1257 		case 4:
1258 			c->fec_inner = FEC_3_5;
1259 			break;
1260 		case 5:
1261 			c->fec_inner = FEC_2_3;
1262 			break;
1263 		case 6:
1264 			c->fec_inner = FEC_3_4;
1265 			break;
1266 		case 7:
1267 			c->fec_inner = FEC_4_5;
1268 			break;
1269 		case 8:
1270 			c->fec_inner = FEC_5_6;
1271 			break;
1272 		case 9:
1273 			c->fec_inner = FEC_8_9;
1274 			break;
1275 		case 10:
1276 			c->fec_inner = FEC_9_10;
1277 			break;
1278 		default:
1279 			dev_dbg(&client->dev, "invalid fec_inner\n");
1280 		}
1281 
1282 		switch ((buf[0] >> 5) & 0x01) {
1283 		case 0:
1284 			c->pilot = PILOT_OFF;
1285 			break;
1286 		case 1:
1287 			c->pilot = PILOT_ON;
1288 			break;
1289 		}
1290 
1291 		switch ((buf[0] >> 6) & 0x07) {
1292 		case 0:
1293 			c->modulation = QPSK;
1294 			break;
1295 		case 1:
1296 			c->modulation = PSK_8;
1297 			break;
1298 		case 2:
1299 			c->modulation = APSK_16;
1300 			break;
1301 		case 3:
1302 			c->modulation = APSK_32;
1303 			break;
1304 		default:
1305 			dev_dbg(&client->dev, "invalid modulation\n");
1306 		}
1307 
1308 		switch ((buf[1] >> 7) & 0x01) {
1309 		case 0:
1310 			c->inversion = INVERSION_OFF;
1311 			break;
1312 		case 1:
1313 			c->inversion = INVERSION_ON;
1314 			break;
1315 		}
1316 
1317 		switch ((buf[2] >> 0) & 0x03) {
1318 		case 0:
1319 			c->rolloff = ROLLOFF_35;
1320 			break;
1321 		case 1:
1322 			c->rolloff = ROLLOFF_25;
1323 			break;
1324 		case 2:
1325 			c->rolloff = ROLLOFF_20;
1326 			break;
1327 		default:
1328 			dev_dbg(&client->dev, "invalid rolloff\n");
1329 		}
1330 		break;
1331 	default:
1332 		dev_dbg(&client->dev, "invalid delivery_system\n");
1333 		ret = -EINVAL;
1334 		goto err;
1335 	}
1336 
1337 	ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
1338 	if (ret)
1339 		goto err;
1340 
1341 	c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000);
1342 
1343 	return 0;
1344 err:
1345 	dev_dbg(&client->dev, "failed=%d\n", ret);
1346 	return ret;
1347 }
1348 
1349 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
1350 {
1351 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1352 
1353 	if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
1354 		*snr = div_s64(c->cnr.stat[0].svalue, 100);
1355 	else
1356 		*snr = 0;
1357 
1358 	return 0;
1359 }
1360 
1361 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
1362 {
1363 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1364 
1365 	*ber = dev->dvbv3_ber;
1366 
1367 	return 0;
1368 }
1369 
1370 static int m88ds3103_set_tone(struct dvb_frontend *fe,
1371 	enum fe_sec_tone_mode fe_sec_tone_mode)
1372 {
1373 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1374 	struct i2c_client *client = dev->client;
1375 	int ret;
1376 	unsigned int utmp, tone, reg_a1_mask;
1377 
1378 	dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
1379 
1380 	if (!dev->warm) {
1381 		ret = -EAGAIN;
1382 		goto err;
1383 	}
1384 
1385 	switch (fe_sec_tone_mode) {
1386 	case SEC_TONE_ON:
1387 		tone = 0;
1388 		reg_a1_mask = 0x47;
1389 		break;
1390 	case SEC_TONE_OFF:
1391 		tone = 1;
1392 		reg_a1_mask = 0x00;
1393 		break;
1394 	default:
1395 		dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
1396 		ret = -EINVAL;
1397 		goto err;
1398 	}
1399 
1400 	utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1401 	ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1402 	if (ret)
1403 		goto err;
1404 
1405 	utmp = 1 << 2;
1406 	ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1407 	if (ret)
1408 		goto err;
1409 
1410 	return 0;
1411 err:
1412 	dev_dbg(&client->dev, "failed=%d\n", ret);
1413 	return ret;
1414 }
1415 
1416 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1417 	enum fe_sec_voltage fe_sec_voltage)
1418 {
1419 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1420 	struct i2c_client *client = dev->client;
1421 	int ret;
1422 	unsigned int utmp;
1423 	bool voltage_sel, voltage_dis;
1424 
1425 	dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1426 
1427 	if (!dev->warm) {
1428 		ret = -EAGAIN;
1429 		goto err;
1430 	}
1431 
1432 	switch (fe_sec_voltage) {
1433 	case SEC_VOLTAGE_18:
1434 		voltage_sel = true;
1435 		voltage_dis = false;
1436 		break;
1437 	case SEC_VOLTAGE_13:
1438 		voltage_sel = false;
1439 		voltage_dis = false;
1440 		break;
1441 	case SEC_VOLTAGE_OFF:
1442 		voltage_sel = false;
1443 		voltage_dis = true;
1444 		break;
1445 	default:
1446 		dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1447 		ret = -EINVAL;
1448 		goto err;
1449 	}
1450 
1451 	/* output pin polarity */
1452 	voltage_sel ^= dev->cfg->lnb_hv_pol;
1453 	voltage_dis ^= dev->cfg->lnb_en_pol;
1454 
1455 	utmp = voltage_dis << 1 | voltage_sel << 0;
1456 	ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1457 	if (ret)
1458 		goto err;
1459 
1460 	return 0;
1461 err:
1462 	dev_dbg(&client->dev, "failed=%d\n", ret);
1463 	return ret;
1464 }
1465 
1466 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1467 		struct dvb_diseqc_master_cmd *diseqc_cmd)
1468 {
1469 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1470 	struct i2c_client *client = dev->client;
1471 	int ret;
1472 	unsigned int utmp;
1473 	unsigned long timeout;
1474 
1475 	dev_dbg(&client->dev, "msg=%*ph\n",
1476 		diseqc_cmd->msg_len, diseqc_cmd->msg);
1477 
1478 	if (!dev->warm) {
1479 		ret = -EAGAIN;
1480 		goto err;
1481 	}
1482 
1483 	if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1484 		ret = -EINVAL;
1485 		goto err;
1486 	}
1487 
1488 	utmp = dev->cfg->envelope_mode << 5;
1489 	ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1490 	if (ret)
1491 		goto err;
1492 
1493 	ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1494 			diseqc_cmd->msg_len);
1495 	if (ret)
1496 		goto err;
1497 
1498 	ret = regmap_write(dev->regmap, 0xa1,
1499 			(diseqc_cmd->msg_len - 1) << 3 | 0x07);
1500 	if (ret)
1501 		goto err;
1502 
1503 	/* wait DiSEqC TX ready */
1504 	#define SEND_MASTER_CMD_TIMEOUT 120
1505 	timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1506 
1507 	/* DiSEqC message period is 13.5 ms per byte */
1508 	utmp = diseqc_cmd->msg_len * 13500;
1509 	usleep_range(utmp - 4000, utmp);
1510 
1511 	for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1512 		ret = regmap_read(dev->regmap, 0xa1, &utmp);
1513 		if (ret)
1514 			goto err;
1515 		utmp = (utmp >> 6) & 0x1;
1516 	}
1517 
1518 	if (utmp == 0) {
1519 		dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1520 			jiffies_to_msecs(jiffies) -
1521 			(jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1522 	} else {
1523 		dev_dbg(&client->dev, "diseqc tx timeout\n");
1524 
1525 		ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1526 		if (ret)
1527 			goto err;
1528 	}
1529 
1530 	ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1531 	if (ret)
1532 		goto err;
1533 
1534 	if (utmp == 1) {
1535 		ret = -ETIMEDOUT;
1536 		goto err;
1537 	}
1538 
1539 	return 0;
1540 err:
1541 	dev_dbg(&client->dev, "failed=%d\n", ret);
1542 	return ret;
1543 }
1544 
1545 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1546 	enum fe_sec_mini_cmd fe_sec_mini_cmd)
1547 {
1548 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1549 	struct i2c_client *client = dev->client;
1550 	int ret;
1551 	unsigned int utmp, burst;
1552 	unsigned long timeout;
1553 
1554 	dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1555 
1556 	if (!dev->warm) {
1557 		ret = -EAGAIN;
1558 		goto err;
1559 	}
1560 
1561 	utmp = dev->cfg->envelope_mode << 5;
1562 	ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1563 	if (ret)
1564 		goto err;
1565 
1566 	switch (fe_sec_mini_cmd) {
1567 	case SEC_MINI_A:
1568 		burst = 0x02;
1569 		break;
1570 	case SEC_MINI_B:
1571 		burst = 0x01;
1572 		break;
1573 	default:
1574 		dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1575 		ret = -EINVAL;
1576 		goto err;
1577 	}
1578 
1579 	ret = regmap_write(dev->regmap, 0xa1, burst);
1580 	if (ret)
1581 		goto err;
1582 
1583 	/* wait DiSEqC TX ready */
1584 	#define SEND_BURST_TIMEOUT 40
1585 	timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1586 
1587 	/* DiSEqC ToneBurst period is 12.5 ms */
1588 	usleep_range(8500, 12500);
1589 
1590 	for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1591 		ret = regmap_read(dev->regmap, 0xa1, &utmp);
1592 		if (ret)
1593 			goto err;
1594 		utmp = (utmp >> 6) & 0x1;
1595 	}
1596 
1597 	if (utmp == 0) {
1598 		dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1599 			jiffies_to_msecs(jiffies) -
1600 			(jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1601 	} else {
1602 		dev_dbg(&client->dev, "diseqc tx timeout\n");
1603 
1604 		ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1605 		if (ret)
1606 			goto err;
1607 	}
1608 
1609 	ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1610 	if (ret)
1611 		goto err;
1612 
1613 	if (utmp == 1) {
1614 		ret = -ETIMEDOUT;
1615 		goto err;
1616 	}
1617 
1618 	return 0;
1619 err:
1620 	dev_dbg(&client->dev, "failed=%d\n", ret);
1621 	return ret;
1622 }
1623 
1624 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1625 	struct dvb_frontend_tune_settings *s)
1626 {
1627 	s->min_delay_ms = 3000;
1628 
1629 	return 0;
1630 }
1631 
1632 static void m88ds3103_release(struct dvb_frontend *fe)
1633 {
1634 	struct m88ds3103_dev *dev = fe->demodulator_priv;
1635 	struct i2c_client *client = dev->client;
1636 
1637 	i2c_unregister_device(client);
1638 }
1639 
1640 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1641 {
1642 	struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1643 	struct i2c_client *client = dev->client;
1644 	int ret;
1645 	struct i2c_msg msg = {
1646 		.addr = client->addr,
1647 		.flags = 0,
1648 		.len = 2,
1649 		.buf = "\x03\x11",
1650 	};
1651 
1652 	/* Open tuner I2C repeater for 1 xfer, closes automatically */
1653 	ret = __i2c_transfer(client->adapter, &msg, 1);
1654 	if (ret != 1) {
1655 		dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1656 		if (ret >= 0)
1657 			ret = -EREMOTEIO;
1658 		return ret;
1659 	}
1660 
1661 	return 0;
1662 }
1663 
1664 /*
1665  * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1666  * proper I2C client for legacy media attach binding.
1667  * New users must use I2C client binding directly!
1668  */
1669 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1670 				      struct i2c_adapter *i2c,
1671 				      struct i2c_adapter **tuner_i2c_adapter)
1672 {
1673 	struct i2c_client *client;
1674 	struct i2c_board_info board_info;
1675 	struct m88ds3103_platform_data pdata = {};
1676 
1677 	pdata.clk = cfg->clock;
1678 	pdata.i2c_wr_max = cfg->i2c_wr_max;
1679 	pdata.ts_mode = cfg->ts_mode;
1680 	pdata.ts_clk = cfg->ts_clk;
1681 	pdata.ts_clk_pol = cfg->ts_clk_pol;
1682 	pdata.spec_inv = cfg->spec_inv;
1683 	pdata.agc = cfg->agc;
1684 	pdata.agc_inv = cfg->agc_inv;
1685 	pdata.clk_out = cfg->clock_out;
1686 	pdata.envelope_mode = cfg->envelope_mode;
1687 	pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1688 	pdata.lnb_en_pol = cfg->lnb_en_pol;
1689 	pdata.attach_in_use = true;
1690 
1691 	memset(&board_info, 0, sizeof(board_info));
1692 	strscpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1693 	board_info.addr = cfg->i2c_addr;
1694 	board_info.platform_data = &pdata;
1695 	client = i2c_new_client_device(i2c, &board_info);
1696 	if (!i2c_client_has_driver(client))
1697 		return NULL;
1698 
1699 	*tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1700 	return pdata.get_dvb_frontend(client);
1701 }
1702 EXPORT_SYMBOL(m88ds3103_attach);
1703 
1704 static const struct dvb_frontend_ops m88ds3103_ops = {
1705 	.delsys = {SYS_DVBS, SYS_DVBS2},
1706 	.info = {
1707 		.name = "Montage Technology M88DS3103",
1708 		.frequency_min_hz =  950 * MHz,
1709 		.frequency_max_hz = 2150 * MHz,
1710 		.frequency_tolerance_hz = 5 * MHz,
1711 		.symbol_rate_min =  1000000,
1712 		.symbol_rate_max = 45000000,
1713 		.caps = FE_CAN_INVERSION_AUTO |
1714 			FE_CAN_FEC_1_2 |
1715 			FE_CAN_FEC_2_3 |
1716 			FE_CAN_FEC_3_4 |
1717 			FE_CAN_FEC_4_5 |
1718 			FE_CAN_FEC_5_6 |
1719 			FE_CAN_FEC_6_7 |
1720 			FE_CAN_FEC_7_8 |
1721 			FE_CAN_FEC_8_9 |
1722 			FE_CAN_FEC_AUTO |
1723 			FE_CAN_QPSK |
1724 			FE_CAN_RECOVER |
1725 			FE_CAN_2G_MODULATION
1726 	},
1727 
1728 	.release = m88ds3103_release,
1729 
1730 	.get_tune_settings = m88ds3103_get_tune_settings,
1731 
1732 	.init = m88ds3103_init,
1733 	.sleep = m88ds3103_sleep,
1734 
1735 	.set_frontend = m88ds3103_set_frontend,
1736 	.get_frontend = m88ds3103_get_frontend,
1737 
1738 	.read_status = m88ds3103_read_status,
1739 	.read_snr = m88ds3103_read_snr,
1740 	.read_ber = m88ds3103_read_ber,
1741 
1742 	.diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1743 	.diseqc_send_burst = m88ds3103_diseqc_send_burst,
1744 
1745 	.set_tone = m88ds3103_set_tone,
1746 	.set_voltage = m88ds3103_set_voltage,
1747 };
1748 
1749 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1750 {
1751 	struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1752 
1753 	dev_dbg(&client->dev, "\n");
1754 
1755 	return &dev->fe;
1756 }
1757 
1758 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1759 {
1760 	struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1761 
1762 	dev_dbg(&client->dev, "\n");
1763 
1764 	return dev->muxc->adapter[0];
1765 }
1766 
1767 static int m88ds3103_probe(struct i2c_client *client,
1768 			const struct i2c_device_id *id)
1769 {
1770 	struct m88ds3103_dev *dev;
1771 	struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1772 	int ret;
1773 	unsigned int utmp;
1774 
1775 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1776 	if (!dev) {
1777 		ret = -ENOMEM;
1778 		goto err;
1779 	}
1780 
1781 	dev->client = client;
1782 	dev->config.clock = pdata->clk;
1783 	dev->config.i2c_wr_max = pdata->i2c_wr_max;
1784 	dev->config.ts_mode = pdata->ts_mode;
1785 	dev->config.ts_clk = pdata->ts_clk * 1000;
1786 	dev->config.ts_clk_pol = pdata->ts_clk_pol;
1787 	dev->config.spec_inv = pdata->spec_inv;
1788 	dev->config.agc_inv = pdata->agc_inv;
1789 	dev->config.clock_out = pdata->clk_out;
1790 	dev->config.envelope_mode = pdata->envelope_mode;
1791 	dev->config.agc = pdata->agc;
1792 	dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1793 	dev->config.lnb_en_pol = pdata->lnb_en_pol;
1794 	dev->cfg = &dev->config;
1795 	/* create regmap */
1796 	dev->regmap_config.reg_bits = 8,
1797 	dev->regmap_config.val_bits = 8,
1798 	dev->regmap_config.lock_arg = dev,
1799 	dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1800 	if (IS_ERR(dev->regmap)) {
1801 		ret = PTR_ERR(dev->regmap);
1802 		goto err_kfree;
1803 	}
1804 
1805 	/* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1806 	ret = regmap_read(dev->regmap, 0x00, &utmp);
1807 	if (ret)
1808 		goto err_kfree;
1809 
1810 	dev->chip_id = utmp >> 1;
1811 	dev->chiptype = (u8)id->driver_data;
1812 
1813 	dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1814 
1815 	switch (dev->chip_id) {
1816 	case M88RS6000_CHIP_ID:
1817 	case M88DS3103_CHIP_ID:
1818 		break;
1819 	default:
1820 		ret = -ENODEV;
1821 		dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id);
1822 		goto err_kfree;
1823 	}
1824 
1825 	switch (dev->cfg->clock_out) {
1826 	case M88DS3103_CLOCK_OUT_DISABLED:
1827 		utmp = 0x80;
1828 		break;
1829 	case M88DS3103_CLOCK_OUT_ENABLED:
1830 		utmp = 0x00;
1831 		break;
1832 	case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1833 		utmp = 0x10;
1834 		break;
1835 	default:
1836 		ret = -EINVAL;
1837 		goto err_kfree;
1838 	}
1839 
1840 	if (!pdata->ts_clk) {
1841 		ret = -EINVAL;
1842 		goto err_kfree;
1843 	}
1844 
1845 	/* 0x29 register is defined differently for m88rs6000. */
1846 	/* set internal tuner address to 0x21 */
1847 	if (dev->chip_id == M88RS6000_CHIP_ID)
1848 		utmp = 0x00;
1849 
1850 	ret = regmap_write(dev->regmap, 0x29, utmp);
1851 	if (ret)
1852 		goto err_kfree;
1853 
1854 	/* sleep */
1855 	ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1856 	if (ret)
1857 		goto err_kfree;
1858 	ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1859 	if (ret)
1860 		goto err_kfree;
1861 	ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1862 	if (ret)
1863 		goto err_kfree;
1864 
1865 	/* create mux i2c adapter for tuner */
1866 	dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1867 				  m88ds3103_select, NULL);
1868 	if (!dev->muxc) {
1869 		ret = -ENOMEM;
1870 		goto err_kfree;
1871 	}
1872 	dev->muxc->priv = dev;
1873 	ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1874 	if (ret)
1875 		goto err_kfree;
1876 
1877 	/* create dvb_frontend */
1878 	memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1879 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
1880 		strscpy(dev->fe.ops.info.name, "Montage Technology M88DS3103B",
1881 			sizeof(dev->fe.ops.info.name));
1882 	else if (dev->chip_id == M88RS6000_CHIP_ID)
1883 		strscpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1884 			sizeof(dev->fe.ops.info.name));
1885 	if (!pdata->attach_in_use)
1886 		dev->fe.ops.release = NULL;
1887 	dev->fe.demodulator_priv = dev;
1888 	i2c_set_clientdata(client, dev);
1889 
1890 	/* setup callbacks */
1891 	pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1892 	pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1893 
1894 	if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
1895 		/* enable i2c repeater for tuner */
1896 		m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
1897 
1898 		/* get frontend address */
1899 		ret = regmap_read(dev->regmap, 0x29, &utmp);
1900 		if (ret)
1901 			goto err_kfree;
1902 		dev->dt_addr = ((utmp & 0x80) == 0) ? 0x42 >> 1 : 0x40 >> 1;
1903 		dev_dbg(&client->dev, "dt addr is 0x%02x\n", dev->dt_addr);
1904 
1905 		dev->dt_client = i2c_new_dummy_device(client->adapter,
1906 						      dev->dt_addr);
1907 		if (!dev->dt_client) {
1908 			ret = -ENODEV;
1909 			goto err_kfree;
1910 		}
1911 	}
1912 
1913 	return 0;
1914 err_kfree:
1915 	kfree(dev);
1916 err:
1917 	dev_dbg(&client->dev, "failed=%d\n", ret);
1918 	return ret;
1919 }
1920 
1921 static int m88ds3103_remove(struct i2c_client *client)
1922 {
1923 	struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1924 
1925 	dev_dbg(&client->dev, "\n");
1926 
1927 	if (dev->dt_client)
1928 		i2c_unregister_device(dev->dt_client);
1929 
1930 	i2c_mux_del_adapters(dev->muxc);
1931 
1932 	kfree(dev);
1933 	return 0;
1934 }
1935 
1936 static const struct i2c_device_id m88ds3103_id_table[] = {
1937 	{"m88ds3103",  M88DS3103_CHIPTYPE_3103},
1938 	{"m88rs6000",  M88DS3103_CHIPTYPE_RS6000},
1939 	{"m88ds3103b", M88DS3103_CHIPTYPE_3103B},
1940 	{}
1941 };
1942 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1943 
1944 static struct i2c_driver m88ds3103_driver = {
1945 	.driver = {
1946 		.name	= "m88ds3103",
1947 		.suppress_bind_attrs = true,
1948 	},
1949 	.probe		= m88ds3103_probe,
1950 	.remove		= m88ds3103_remove,
1951 	.id_table	= m88ds3103_id_table,
1952 };
1953 
1954 module_i2c_driver(m88ds3103_driver);
1955 
1956 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1957 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1958 MODULE_LICENSE("GPL");
1959 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1960 MODULE_FIRMWARE(M88RS6000_FIRMWARE);
1961 MODULE_FIRMWARE(M88DS3103B_FIRMWARE);
1962