1 /* 2 * Montage Technology M88DS3103/M88RS6000 demodulator driver 3 * 4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include "m88ds3103_priv.h" 18 19 static struct dvb_frontend_ops m88ds3103_ops; 20 21 /* write reg val table using reg addr auto increment */ 22 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev, 23 const struct m88ds3103_reg_val *tab, int tab_len) 24 { 25 struct i2c_client *client = dev->client; 26 int ret, i, j; 27 u8 buf[83]; 28 29 dev_dbg(&client->dev, "tab_len=%d\n", tab_len); 30 31 if (tab_len > 86) { 32 ret = -EINVAL; 33 goto err; 34 } 35 36 for (i = 0, j = 0; i < tab_len; i++, j++) { 37 buf[j] = tab[i].val; 38 39 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || 40 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) { 41 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); 42 if (ret) 43 goto err; 44 45 j = -1; 46 } 47 } 48 49 return 0; 50 err: 51 dev_dbg(&client->dev, "failed=%d\n", ret); 52 return ret; 53 } 54 55 static int m88ds3103_read_status(struct dvb_frontend *fe, 56 enum fe_status *status) 57 { 58 struct m88ds3103_dev *dev = fe->demodulator_priv; 59 struct i2c_client *client = dev->client; 60 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 61 int ret, i, itmp; 62 unsigned int utmp; 63 u8 buf[3]; 64 65 *status = 0; 66 67 if (!dev->warm) { 68 ret = -EAGAIN; 69 goto err; 70 } 71 72 switch (c->delivery_system) { 73 case SYS_DVBS: 74 ret = regmap_read(dev->regmap, 0xd1, &utmp); 75 if (ret) 76 goto err; 77 78 if ((utmp & 0x07) == 0x07) 79 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 80 FE_HAS_VITERBI | FE_HAS_SYNC | 81 FE_HAS_LOCK; 82 break; 83 case SYS_DVBS2: 84 ret = regmap_read(dev->regmap, 0x0d, &utmp); 85 if (ret) 86 goto err; 87 88 if ((utmp & 0x8f) == 0x8f) 89 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 90 FE_HAS_VITERBI | FE_HAS_SYNC | 91 FE_HAS_LOCK; 92 break; 93 default: 94 dev_dbg(&client->dev, "invalid delivery_system\n"); 95 ret = -EINVAL; 96 goto err; 97 } 98 99 dev->fe_status = *status; 100 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status); 101 102 /* CNR */ 103 if (dev->fe_status & FE_HAS_VITERBI) { 104 unsigned int cnr, noise, signal, noise_tot, signal_tot; 105 106 cnr = 0; 107 /* more iterations for more accurate estimation */ 108 #define M88DS3103_SNR_ITERATIONS 3 109 110 switch (c->delivery_system) { 111 case SYS_DVBS: 112 itmp = 0; 113 114 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 115 ret = regmap_read(dev->regmap, 0xff, &utmp); 116 if (ret) 117 goto err; 118 119 itmp += utmp; 120 } 121 122 /* use of single register limits max value to 15 dB */ 123 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */ 124 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS); 125 if (itmp) 126 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10)); 127 break; 128 case SYS_DVBS2: 129 noise_tot = 0; 130 signal_tot = 0; 131 132 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) { 133 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3); 134 if (ret) 135 goto err; 136 137 noise = buf[1] << 6; /* [13:6] */ 138 noise |= buf[0] & 0x3f; /* [5:0] */ 139 noise >>= 2; 140 signal = buf[2] * buf[2]; 141 signal >>= 1; 142 143 noise_tot += noise; 144 signal_tot += signal; 145 } 146 147 noise = noise_tot / M88DS3103_SNR_ITERATIONS; 148 signal = signal_tot / M88DS3103_SNR_ITERATIONS; 149 150 /* SNR(X) dB = 10 * log10(X) dB */ 151 if (signal > noise) { 152 itmp = signal / noise; 153 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24)); 154 } 155 break; 156 default: 157 dev_dbg(&client->dev, "invalid delivery_system\n"); 158 ret = -EINVAL; 159 goto err; 160 } 161 162 if (cnr) { 163 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; 164 c->cnr.stat[0].svalue = cnr; 165 } else { 166 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 167 } 168 } else { 169 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 170 } 171 172 /* BER */ 173 if (dev->fe_status & FE_HAS_LOCK) { 174 unsigned int utmp, post_bit_error, post_bit_count; 175 176 switch (c->delivery_system) { 177 case SYS_DVBS: 178 ret = regmap_write(dev->regmap, 0xf9, 0x04); 179 if (ret) 180 goto err; 181 182 ret = regmap_read(dev->regmap, 0xf8, &utmp); 183 if (ret) 184 goto err; 185 186 /* measurement ready? */ 187 if (!(utmp & 0x10)) { 188 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2); 189 if (ret) 190 goto err; 191 192 post_bit_error = buf[1] << 8 | buf[0] << 0; 193 post_bit_count = 0x800000; 194 dev->post_bit_error += post_bit_error; 195 dev->post_bit_count += post_bit_count; 196 dev->dvbv3_ber = post_bit_error; 197 198 /* restart measurement */ 199 utmp |= 0x10; 200 ret = regmap_write(dev->regmap, 0xf8, utmp); 201 if (ret) 202 goto err; 203 } 204 break; 205 case SYS_DVBS2: 206 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3); 207 if (ret) 208 goto err; 209 210 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0; 211 212 /* enough data? */ 213 if (utmp > 4000) { 214 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2); 215 if (ret) 216 goto err; 217 218 post_bit_error = buf[1] << 8 | buf[0] << 0; 219 post_bit_count = 32 * utmp; /* TODO: FEC */ 220 dev->post_bit_error += post_bit_error; 221 dev->post_bit_count += post_bit_count; 222 dev->dvbv3_ber = post_bit_error; 223 224 /* restart measurement */ 225 ret = regmap_write(dev->regmap, 0xd1, 0x01); 226 if (ret) 227 goto err; 228 229 ret = regmap_write(dev->regmap, 0xf9, 0x01); 230 if (ret) 231 goto err; 232 233 ret = regmap_write(dev->regmap, 0xf9, 0x00); 234 if (ret) 235 goto err; 236 237 ret = regmap_write(dev->regmap, 0xd1, 0x00); 238 if (ret) 239 goto err; 240 } 241 break; 242 default: 243 dev_dbg(&client->dev, "invalid delivery_system\n"); 244 ret = -EINVAL; 245 goto err; 246 } 247 248 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; 249 c->post_bit_error.stat[0].uvalue = dev->post_bit_error; 250 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; 251 c->post_bit_count.stat[0].uvalue = dev->post_bit_count; 252 } else { 253 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 254 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 255 } 256 257 return 0; 258 err: 259 dev_dbg(&client->dev, "failed=%d\n", ret); 260 return ret; 261 } 262 263 static int m88ds3103_set_frontend(struct dvb_frontend *fe) 264 { 265 struct m88ds3103_dev *dev = fe->demodulator_priv; 266 struct i2c_client *client = dev->client; 267 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 268 int ret, len; 269 const struct m88ds3103_reg_val *init; 270 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */ 271 u8 buf[3]; 272 u16 u16tmp, divide_ratio = 0; 273 u32 tuner_frequency, target_mclk; 274 s32 s32tmp; 275 276 dev_dbg(&client->dev, 277 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n", 278 c->delivery_system, c->modulation, c->frequency, c->symbol_rate, 279 c->inversion, c->pilot, c->rolloff); 280 281 if (!dev->warm) { 282 ret = -EAGAIN; 283 goto err; 284 } 285 286 /* reset */ 287 ret = regmap_write(dev->regmap, 0x07, 0x80); 288 if (ret) 289 goto err; 290 291 ret = regmap_write(dev->regmap, 0x07, 0x00); 292 if (ret) 293 goto err; 294 295 /* Disable demod clock path */ 296 if (dev->chip_id == M88RS6000_CHIP_ID) { 297 ret = regmap_write(dev->regmap, 0x06, 0xe0); 298 if (ret) 299 goto err; 300 } 301 302 /* program tuner */ 303 if (fe->ops.tuner_ops.set_params) { 304 ret = fe->ops.tuner_ops.set_params(fe); 305 if (ret) 306 goto err; 307 } 308 309 if (fe->ops.tuner_ops.get_frequency) { 310 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency); 311 if (ret) 312 goto err; 313 } else { 314 /* 315 * Use nominal target frequency as tuner driver does not provide 316 * actual frequency used. Carrier offset calculation is not 317 * valid. 318 */ 319 tuner_frequency = c->frequency; 320 } 321 322 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */ 323 if (dev->chip_id == M88RS6000_CHIP_ID) { 324 if (c->symbol_rate > 45010000) 325 dev->mclk_khz = 110250; 326 else 327 dev->mclk_khz = 96000; 328 329 if (c->delivery_system == SYS_DVBS) 330 target_mclk = 96000; 331 else 332 target_mclk = 144000; 333 334 /* Enable demod clock path */ 335 ret = regmap_write(dev->regmap, 0x06, 0x00); 336 if (ret) 337 goto err; 338 usleep_range(10000, 20000); 339 } else { 340 /* set M88DS3103 mclk and ts mclk. */ 341 dev->mclk_khz = 96000; 342 343 switch (dev->cfg->ts_mode) { 344 case M88DS3103_TS_SERIAL: 345 case M88DS3103_TS_SERIAL_D7: 346 target_mclk = dev->cfg->ts_clk; 347 break; 348 case M88DS3103_TS_PARALLEL: 349 case M88DS3103_TS_CI: 350 if (c->delivery_system == SYS_DVBS) 351 target_mclk = 96000; 352 else { 353 if (c->symbol_rate < 18000000) 354 target_mclk = 96000; 355 else if (c->symbol_rate < 28000000) 356 target_mclk = 144000; 357 else 358 target_mclk = 192000; 359 } 360 break; 361 default: 362 dev_dbg(&client->dev, "invalid ts_mode\n"); 363 ret = -EINVAL; 364 goto err; 365 } 366 367 switch (target_mclk) { 368 case 96000: 369 u8tmp1 = 0x02; /* 0b10 */ 370 u8tmp2 = 0x01; /* 0b01 */ 371 break; 372 case 144000: 373 u8tmp1 = 0x00; /* 0b00 */ 374 u8tmp2 = 0x01; /* 0b01 */ 375 break; 376 case 192000: 377 u8tmp1 = 0x03; /* 0b11 */ 378 u8tmp2 = 0x00; /* 0b00 */ 379 break; 380 } 381 ret = regmap_update_bits(dev->regmap, 0x22, 0xc0, u8tmp1 << 6); 382 if (ret) 383 goto err; 384 ret = regmap_update_bits(dev->regmap, 0x24, 0xc0, u8tmp2 << 6); 385 if (ret) 386 goto err; 387 } 388 389 ret = regmap_write(dev->regmap, 0xb2, 0x01); 390 if (ret) 391 goto err; 392 393 ret = regmap_write(dev->regmap, 0x00, 0x01); 394 if (ret) 395 goto err; 396 397 switch (c->delivery_system) { 398 case SYS_DVBS: 399 if (dev->chip_id == M88RS6000_CHIP_ID) { 400 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals); 401 init = m88rs6000_dvbs_init_reg_vals; 402 } else { 403 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals); 404 init = m88ds3103_dvbs_init_reg_vals; 405 } 406 break; 407 case SYS_DVBS2: 408 if (dev->chip_id == M88RS6000_CHIP_ID) { 409 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals); 410 init = m88rs6000_dvbs2_init_reg_vals; 411 } else { 412 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals); 413 init = m88ds3103_dvbs2_init_reg_vals; 414 } 415 break; 416 default: 417 dev_dbg(&client->dev, "invalid delivery_system\n"); 418 ret = -EINVAL; 419 goto err; 420 } 421 422 /* program init table */ 423 if (c->delivery_system != dev->delivery_system) { 424 ret = m88ds3103_wr_reg_val_tab(dev, init, len); 425 if (ret) 426 goto err; 427 } 428 429 if (dev->chip_id == M88RS6000_CHIP_ID) { 430 if ((c->delivery_system == SYS_DVBS2) 431 && ((c->symbol_rate / 1000) <= 5000)) { 432 ret = regmap_write(dev->regmap, 0xc0, 0x04); 433 if (ret) 434 goto err; 435 buf[0] = 0x09; 436 buf[1] = 0x22; 437 buf[2] = 0x88; 438 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3); 439 if (ret) 440 goto err; 441 } 442 ret = regmap_update_bits(dev->regmap, 0x9d, 0x08, 0x08); 443 if (ret) 444 goto err; 445 ret = regmap_write(dev->regmap, 0xf1, 0x01); 446 if (ret) 447 goto err; 448 ret = regmap_update_bits(dev->regmap, 0x30, 0x80, 0x80); 449 if (ret) 450 goto err; 451 } 452 453 switch (dev->cfg->ts_mode) { 454 case M88DS3103_TS_SERIAL: 455 u8tmp1 = 0x00; 456 u8tmp = 0x06; 457 break; 458 case M88DS3103_TS_SERIAL_D7: 459 u8tmp1 = 0x20; 460 u8tmp = 0x06; 461 break; 462 case M88DS3103_TS_PARALLEL: 463 u8tmp = 0x02; 464 break; 465 case M88DS3103_TS_CI: 466 u8tmp = 0x03; 467 break; 468 default: 469 dev_dbg(&client->dev, "invalid ts_mode\n"); 470 ret = -EINVAL; 471 goto err; 472 } 473 474 if (dev->cfg->ts_clk_pol) 475 u8tmp |= 0x40; 476 477 /* TS mode */ 478 ret = regmap_write(dev->regmap, 0xfd, u8tmp); 479 if (ret) 480 goto err; 481 482 switch (dev->cfg->ts_mode) { 483 case M88DS3103_TS_SERIAL: 484 case M88DS3103_TS_SERIAL_D7: 485 ret = regmap_update_bits(dev->regmap, 0x29, 0x20, u8tmp1); 486 if (ret) 487 goto err; 488 u8tmp1 = 0; 489 u8tmp2 = 0; 490 break; 491 default: 492 if (dev->cfg->ts_clk) { 493 divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk); 494 u8tmp1 = divide_ratio / 2; 495 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2); 496 } 497 } 498 499 dev_dbg(&client->dev, 500 "target_mclk=%d ts_clk=%d divide_ratio=%d\n", 501 target_mclk, dev->cfg->ts_clk, divide_ratio); 502 503 u8tmp1--; 504 u8tmp2--; 505 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */ 506 u8tmp1 &= 0x3f; 507 /* u8tmp2[5:0] => ea[5:0] */ 508 u8tmp2 &= 0x3f; 509 510 ret = regmap_bulk_read(dev->regmap, 0xfe, &u8tmp, 1); 511 if (ret) 512 goto err; 513 514 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2; 515 ret = regmap_write(dev->regmap, 0xfe, u8tmp); 516 if (ret) 517 goto err; 518 519 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0; 520 ret = regmap_write(dev->regmap, 0xea, u8tmp); 521 if (ret) 522 goto err; 523 524 if (c->symbol_rate <= 3000000) 525 u8tmp = 0x20; 526 else if (c->symbol_rate <= 10000000) 527 u8tmp = 0x10; 528 else 529 u8tmp = 0x06; 530 531 ret = regmap_write(dev->regmap, 0xc3, 0x08); 532 if (ret) 533 goto err; 534 535 ret = regmap_write(dev->regmap, 0xc8, u8tmp); 536 if (ret) 537 goto err; 538 539 ret = regmap_write(dev->regmap, 0xc4, 0x08); 540 if (ret) 541 goto err; 542 543 ret = regmap_write(dev->regmap, 0xc7, 0x00); 544 if (ret) 545 goto err; 546 547 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2); 548 buf[0] = (u16tmp >> 0) & 0xff; 549 buf[1] = (u16tmp >> 8) & 0xff; 550 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2); 551 if (ret) 552 goto err; 553 554 ret = regmap_update_bits(dev->regmap, 0x4d, 0x02, dev->cfg->spec_inv << 1); 555 if (ret) 556 goto err; 557 558 ret = regmap_update_bits(dev->regmap, 0x30, 0x10, dev->cfg->agc_inv << 4); 559 if (ret) 560 goto err; 561 562 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc); 563 if (ret) 564 goto err; 565 566 dev_dbg(&client->dev, "carrier offset=%d\n", 567 (tuner_frequency - c->frequency)); 568 569 s32tmp = 0x10000 * (tuner_frequency - c->frequency); 570 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz); 571 if (s32tmp < 0) 572 s32tmp += 0x10000; 573 574 buf[0] = (s32tmp >> 0) & 0xff; 575 buf[1] = (s32tmp >> 8) & 0xff; 576 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2); 577 if (ret) 578 goto err; 579 580 ret = regmap_write(dev->regmap, 0x00, 0x00); 581 if (ret) 582 goto err; 583 584 ret = regmap_write(dev->regmap, 0xb2, 0x00); 585 if (ret) 586 goto err; 587 588 dev->delivery_system = c->delivery_system; 589 590 return 0; 591 err: 592 dev_dbg(&client->dev, "failed=%d\n", ret); 593 return ret; 594 } 595 596 static int m88ds3103_init(struct dvb_frontend *fe) 597 { 598 struct m88ds3103_dev *dev = fe->demodulator_priv; 599 struct i2c_client *client = dev->client; 600 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 601 int ret, len, remaining; 602 unsigned int utmp; 603 const struct firmware *fw = NULL; 604 u8 *fw_file; 605 606 dev_dbg(&client->dev, "\n"); 607 608 /* set cold state by default */ 609 dev->warm = false; 610 611 /* wake up device from sleep */ 612 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x01); 613 if (ret) 614 goto err; 615 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x00); 616 if (ret) 617 goto err; 618 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x00); 619 if (ret) 620 goto err; 621 622 /* firmware status */ 623 ret = regmap_read(dev->regmap, 0xb9, &utmp); 624 if (ret) 625 goto err; 626 627 dev_dbg(&client->dev, "firmware=%02x\n", utmp); 628 629 if (utmp) 630 goto skip_fw_download; 631 632 /* global reset, global diseqc reset, golbal fec reset */ 633 ret = regmap_write(dev->regmap, 0x07, 0xe0); 634 if (ret) 635 goto err; 636 ret = regmap_write(dev->regmap, 0x07, 0x00); 637 if (ret) 638 goto err; 639 640 /* cold state - try to download firmware */ 641 dev_info(&client->dev, "found a '%s' in cold state\n", 642 m88ds3103_ops.info.name); 643 644 if (dev->chip_id == M88RS6000_CHIP_ID) 645 fw_file = M88RS6000_FIRMWARE; 646 else 647 fw_file = M88DS3103_FIRMWARE; 648 /* request the firmware, this will block and timeout */ 649 ret = request_firmware(&fw, fw_file, &client->dev); 650 if (ret) { 651 dev_err(&client->dev, "firmare file '%s' not found\n", fw_file); 652 goto err; 653 } 654 655 dev_info(&client->dev, "downloading firmware from file '%s'\n", 656 fw_file); 657 658 ret = regmap_write(dev->regmap, 0xb2, 0x01); 659 if (ret) 660 goto error_fw_release; 661 662 for (remaining = fw->size; remaining > 0; 663 remaining -= (dev->cfg->i2c_wr_max - 1)) { 664 len = remaining; 665 if (len > (dev->cfg->i2c_wr_max - 1)) 666 len = (dev->cfg->i2c_wr_max - 1); 667 668 ret = regmap_bulk_write(dev->regmap, 0xb0, 669 &fw->data[fw->size - remaining], len); 670 if (ret) { 671 dev_err(&client->dev, "firmware download failed=%d\n", 672 ret); 673 goto error_fw_release; 674 } 675 } 676 677 ret = regmap_write(dev->regmap, 0xb2, 0x00); 678 if (ret) 679 goto error_fw_release; 680 681 release_firmware(fw); 682 fw = NULL; 683 684 ret = regmap_read(dev->regmap, 0xb9, &utmp); 685 if (ret) 686 goto err; 687 688 if (!utmp) { 689 dev_info(&client->dev, "firmware did not run\n"); 690 ret = -EFAULT; 691 goto err; 692 } 693 694 dev_info(&client->dev, "found a '%s' in warm state\n", 695 m88ds3103_ops.info.name); 696 dev_info(&client->dev, "firmware version: %X.%X\n", 697 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf)); 698 699 skip_fw_download: 700 /* warm state */ 701 dev->warm = true; 702 703 /* init stats here in order signal app which stats are supported */ 704 c->cnr.len = 1; 705 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 706 c->post_bit_error.len = 1; 707 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 708 c->post_bit_count.len = 1; 709 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; 710 711 return 0; 712 error_fw_release: 713 release_firmware(fw); 714 err: 715 dev_dbg(&client->dev, "failed=%d\n", ret); 716 return ret; 717 } 718 719 static int m88ds3103_sleep(struct dvb_frontend *fe) 720 { 721 struct m88ds3103_dev *dev = fe->demodulator_priv; 722 struct i2c_client *client = dev->client; 723 int ret; 724 unsigned int utmp; 725 726 dev_dbg(&client->dev, "\n"); 727 728 dev->fe_status = 0; 729 dev->delivery_system = SYS_UNDEFINED; 730 731 /* TS Hi-Z */ 732 if (dev->chip_id == M88RS6000_CHIP_ID) 733 utmp = 0x29; 734 else 735 utmp = 0x27; 736 ret = regmap_update_bits(dev->regmap, utmp, 0x01, 0x00); 737 if (ret) 738 goto err; 739 740 /* sleep */ 741 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x00); 742 if (ret) 743 goto err; 744 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x01); 745 if (ret) 746 goto err; 747 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x10); 748 if (ret) 749 goto err; 750 751 return 0; 752 err: 753 dev_dbg(&client->dev, "failed=%d\n", ret); 754 return ret; 755 } 756 757 static int m88ds3103_get_frontend(struct dvb_frontend *fe) 758 { 759 struct m88ds3103_dev *dev = fe->demodulator_priv; 760 struct i2c_client *client = dev->client; 761 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 762 int ret; 763 u8 buf[3]; 764 765 dev_dbg(&client->dev, "\n"); 766 767 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) { 768 ret = 0; 769 goto err; 770 } 771 772 switch (c->delivery_system) { 773 case SYS_DVBS: 774 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1); 775 if (ret) 776 goto err; 777 778 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1); 779 if (ret) 780 goto err; 781 782 switch ((buf[0] >> 2) & 0x01) { 783 case 0: 784 c->inversion = INVERSION_OFF; 785 break; 786 case 1: 787 c->inversion = INVERSION_ON; 788 break; 789 } 790 791 switch ((buf[1] >> 5) & 0x07) { 792 case 0: 793 c->fec_inner = FEC_7_8; 794 break; 795 case 1: 796 c->fec_inner = FEC_5_6; 797 break; 798 case 2: 799 c->fec_inner = FEC_3_4; 800 break; 801 case 3: 802 c->fec_inner = FEC_2_3; 803 break; 804 case 4: 805 c->fec_inner = FEC_1_2; 806 break; 807 default: 808 dev_dbg(&client->dev, "invalid fec_inner\n"); 809 } 810 811 c->modulation = QPSK; 812 813 break; 814 case SYS_DVBS2: 815 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1); 816 if (ret) 817 goto err; 818 819 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1); 820 if (ret) 821 goto err; 822 823 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1); 824 if (ret) 825 goto err; 826 827 switch ((buf[0] >> 0) & 0x0f) { 828 case 2: 829 c->fec_inner = FEC_2_5; 830 break; 831 case 3: 832 c->fec_inner = FEC_1_2; 833 break; 834 case 4: 835 c->fec_inner = FEC_3_5; 836 break; 837 case 5: 838 c->fec_inner = FEC_2_3; 839 break; 840 case 6: 841 c->fec_inner = FEC_3_4; 842 break; 843 case 7: 844 c->fec_inner = FEC_4_5; 845 break; 846 case 8: 847 c->fec_inner = FEC_5_6; 848 break; 849 case 9: 850 c->fec_inner = FEC_8_9; 851 break; 852 case 10: 853 c->fec_inner = FEC_9_10; 854 break; 855 default: 856 dev_dbg(&client->dev, "invalid fec_inner\n"); 857 } 858 859 switch ((buf[0] >> 5) & 0x01) { 860 case 0: 861 c->pilot = PILOT_OFF; 862 break; 863 case 1: 864 c->pilot = PILOT_ON; 865 break; 866 } 867 868 switch ((buf[0] >> 6) & 0x07) { 869 case 0: 870 c->modulation = QPSK; 871 break; 872 case 1: 873 c->modulation = PSK_8; 874 break; 875 case 2: 876 c->modulation = APSK_16; 877 break; 878 case 3: 879 c->modulation = APSK_32; 880 break; 881 default: 882 dev_dbg(&client->dev, "invalid modulation\n"); 883 } 884 885 switch ((buf[1] >> 7) & 0x01) { 886 case 0: 887 c->inversion = INVERSION_OFF; 888 break; 889 case 1: 890 c->inversion = INVERSION_ON; 891 break; 892 } 893 894 switch ((buf[2] >> 0) & 0x03) { 895 case 0: 896 c->rolloff = ROLLOFF_35; 897 break; 898 case 1: 899 c->rolloff = ROLLOFF_25; 900 break; 901 case 2: 902 c->rolloff = ROLLOFF_20; 903 break; 904 default: 905 dev_dbg(&client->dev, "invalid rolloff\n"); 906 } 907 break; 908 default: 909 dev_dbg(&client->dev, "invalid delivery_system\n"); 910 ret = -EINVAL; 911 goto err; 912 } 913 914 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2); 915 if (ret) 916 goto err; 917 918 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) * 919 dev->mclk_khz * 1000 / 0x10000; 920 921 return 0; 922 err: 923 dev_dbg(&client->dev, "failed=%d\n", ret); 924 return ret; 925 } 926 927 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr) 928 { 929 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 930 931 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) 932 *snr = div_s64(c->cnr.stat[0].svalue, 100); 933 else 934 *snr = 0; 935 936 return 0; 937 } 938 939 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber) 940 { 941 struct m88ds3103_dev *dev = fe->demodulator_priv; 942 943 *ber = dev->dvbv3_ber; 944 945 return 0; 946 } 947 948 static int m88ds3103_set_tone(struct dvb_frontend *fe, 949 enum fe_sec_tone_mode fe_sec_tone_mode) 950 { 951 struct m88ds3103_dev *dev = fe->demodulator_priv; 952 struct i2c_client *client = dev->client; 953 int ret; 954 unsigned int utmp, tone, reg_a1_mask; 955 956 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode); 957 958 if (!dev->warm) { 959 ret = -EAGAIN; 960 goto err; 961 } 962 963 switch (fe_sec_tone_mode) { 964 case SEC_TONE_ON: 965 tone = 0; 966 reg_a1_mask = 0x47; 967 break; 968 case SEC_TONE_OFF: 969 tone = 1; 970 reg_a1_mask = 0x00; 971 break; 972 default: 973 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n"); 974 ret = -EINVAL; 975 goto err; 976 } 977 978 utmp = tone << 7 | dev->cfg->envelope_mode << 5; 979 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp); 980 if (ret) 981 goto err; 982 983 utmp = 1 << 2; 984 ret = regmap_update_bits(dev->regmap, 0xa1, reg_a1_mask, utmp); 985 if (ret) 986 goto err; 987 988 return 0; 989 err: 990 dev_dbg(&client->dev, "failed=%d\n", ret); 991 return ret; 992 } 993 994 static int m88ds3103_set_voltage(struct dvb_frontend *fe, 995 enum fe_sec_voltage fe_sec_voltage) 996 { 997 struct m88ds3103_dev *dev = fe->demodulator_priv; 998 struct i2c_client *client = dev->client; 999 int ret; 1000 unsigned int utmp; 1001 bool voltage_sel, voltage_dis; 1002 1003 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage); 1004 1005 if (!dev->warm) { 1006 ret = -EAGAIN; 1007 goto err; 1008 } 1009 1010 switch (fe_sec_voltage) { 1011 case SEC_VOLTAGE_18: 1012 voltage_sel = true; 1013 voltage_dis = false; 1014 break; 1015 case SEC_VOLTAGE_13: 1016 voltage_sel = false; 1017 voltage_dis = false; 1018 break; 1019 case SEC_VOLTAGE_OFF: 1020 voltage_sel = false; 1021 voltage_dis = true; 1022 break; 1023 default: 1024 dev_dbg(&client->dev, "invalid fe_sec_voltage\n"); 1025 ret = -EINVAL; 1026 goto err; 1027 } 1028 1029 /* output pin polarity */ 1030 voltage_sel ^= dev->cfg->lnb_hv_pol; 1031 voltage_dis ^= dev->cfg->lnb_en_pol; 1032 1033 utmp = voltage_dis << 1 | voltage_sel << 0; 1034 ret = regmap_update_bits(dev->regmap, 0xa2, 0x03, utmp); 1035 if (ret) 1036 goto err; 1037 1038 return 0; 1039 err: 1040 dev_dbg(&client->dev, "failed=%d\n", ret); 1041 return ret; 1042 } 1043 1044 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe, 1045 struct dvb_diseqc_master_cmd *diseqc_cmd) 1046 { 1047 struct m88ds3103_dev *dev = fe->demodulator_priv; 1048 struct i2c_client *client = dev->client; 1049 int ret; 1050 unsigned int utmp; 1051 unsigned long timeout; 1052 1053 dev_dbg(&client->dev, "msg=%*ph\n", 1054 diseqc_cmd->msg_len, diseqc_cmd->msg); 1055 1056 if (!dev->warm) { 1057 ret = -EAGAIN; 1058 goto err; 1059 } 1060 1061 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) { 1062 ret = -EINVAL; 1063 goto err; 1064 } 1065 1066 utmp = dev->cfg->envelope_mode << 5; 1067 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp); 1068 if (ret) 1069 goto err; 1070 1071 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg, 1072 diseqc_cmd->msg_len); 1073 if (ret) 1074 goto err; 1075 1076 ret = regmap_write(dev->regmap, 0xa1, 1077 (diseqc_cmd->msg_len - 1) << 3 | 0x07); 1078 if (ret) 1079 goto err; 1080 1081 /* wait DiSEqC TX ready */ 1082 #define SEND_MASTER_CMD_TIMEOUT 120 1083 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT); 1084 1085 /* DiSEqC message typical period is 54 ms */ 1086 usleep_range(50000, 54000); 1087 1088 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { 1089 ret = regmap_read(dev->regmap, 0xa1, &utmp); 1090 if (ret) 1091 goto err; 1092 utmp = (utmp >> 6) & 0x1; 1093 } 1094 1095 if (utmp == 0) { 1096 dev_dbg(&client->dev, "diseqc tx took %u ms\n", 1097 jiffies_to_msecs(jiffies) - 1098 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT)); 1099 } else { 1100 dev_dbg(&client->dev, "diseqc tx timeout\n"); 1101 1102 ret = regmap_update_bits(dev->regmap, 0xa1, 0xc0, 0x40); 1103 if (ret) 1104 goto err; 1105 } 1106 1107 ret = regmap_update_bits(dev->regmap, 0xa2, 0xc0, 0x80); 1108 if (ret) 1109 goto err; 1110 1111 if (utmp == 1) { 1112 ret = -ETIMEDOUT; 1113 goto err; 1114 } 1115 1116 return 0; 1117 err: 1118 dev_dbg(&client->dev, "failed=%d\n", ret); 1119 return ret; 1120 } 1121 1122 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, 1123 enum fe_sec_mini_cmd fe_sec_mini_cmd) 1124 { 1125 struct m88ds3103_dev *dev = fe->demodulator_priv; 1126 struct i2c_client *client = dev->client; 1127 int ret; 1128 unsigned int utmp, burst; 1129 unsigned long timeout; 1130 1131 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd); 1132 1133 if (!dev->warm) { 1134 ret = -EAGAIN; 1135 goto err; 1136 } 1137 1138 utmp = dev->cfg->envelope_mode << 5; 1139 ret = regmap_update_bits(dev->regmap, 0xa2, 0xe0, utmp); 1140 if (ret) 1141 goto err; 1142 1143 switch (fe_sec_mini_cmd) { 1144 case SEC_MINI_A: 1145 burst = 0x02; 1146 break; 1147 case SEC_MINI_B: 1148 burst = 0x01; 1149 break; 1150 default: 1151 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n"); 1152 ret = -EINVAL; 1153 goto err; 1154 } 1155 1156 ret = regmap_write(dev->regmap, 0xa1, burst); 1157 if (ret) 1158 goto err; 1159 1160 /* wait DiSEqC TX ready */ 1161 #define SEND_BURST_TIMEOUT 40 1162 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT); 1163 1164 /* DiSEqC ToneBurst period is 12.5 ms */ 1165 usleep_range(8500, 12500); 1166 1167 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) { 1168 ret = regmap_read(dev->regmap, 0xa1, &utmp); 1169 if (ret) 1170 goto err; 1171 utmp = (utmp >> 6) & 0x1; 1172 } 1173 1174 if (utmp == 0) { 1175 dev_dbg(&client->dev, "diseqc tx took %u ms\n", 1176 jiffies_to_msecs(jiffies) - 1177 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT)); 1178 } else { 1179 dev_dbg(&client->dev, "diseqc tx timeout\n"); 1180 1181 ret = regmap_update_bits(dev->regmap, 0xa1, 0xc0, 0x40); 1182 if (ret) 1183 goto err; 1184 } 1185 1186 ret = regmap_update_bits(dev->regmap, 0xa2, 0xc0, 0x80); 1187 if (ret) 1188 goto err; 1189 1190 if (utmp == 1) { 1191 ret = -ETIMEDOUT; 1192 goto err; 1193 } 1194 1195 return 0; 1196 err: 1197 dev_dbg(&client->dev, "failed=%d\n", ret); 1198 return ret; 1199 } 1200 1201 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe, 1202 struct dvb_frontend_tune_settings *s) 1203 { 1204 s->min_delay_ms = 3000; 1205 1206 return 0; 1207 } 1208 1209 static void m88ds3103_release(struct dvb_frontend *fe) 1210 { 1211 struct m88ds3103_dev *dev = fe->demodulator_priv; 1212 struct i2c_client *client = dev->client; 1213 1214 i2c_unregister_device(client); 1215 } 1216 1217 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan) 1218 { 1219 struct m88ds3103_dev *dev = mux_priv; 1220 struct i2c_client *client = dev->client; 1221 int ret; 1222 struct i2c_msg msg = { 1223 .addr = client->addr, 1224 .flags = 0, 1225 .len = 2, 1226 .buf = "\x03\x11", 1227 }; 1228 1229 /* Open tuner I2C repeater for 1 xfer, closes automatically */ 1230 ret = __i2c_transfer(client->adapter, &msg, 1); 1231 if (ret != 1) { 1232 dev_warn(&client->dev, "i2c wr failed=%d\n", ret); 1233 if (ret >= 0) 1234 ret = -EREMOTEIO; 1235 return ret; 1236 } 1237 1238 return 0; 1239 } 1240 1241 /* 1242 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide 1243 * proper I2C client for legacy media attach binding. 1244 * New users must use I2C client binding directly! 1245 */ 1246 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, 1247 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter) 1248 { 1249 struct i2c_client *client; 1250 struct i2c_board_info board_info; 1251 struct m88ds3103_platform_data pdata; 1252 1253 pdata.clk = cfg->clock; 1254 pdata.i2c_wr_max = cfg->i2c_wr_max; 1255 pdata.ts_mode = cfg->ts_mode; 1256 pdata.ts_clk = cfg->ts_clk; 1257 pdata.ts_clk_pol = cfg->ts_clk_pol; 1258 pdata.spec_inv = cfg->spec_inv; 1259 pdata.agc = cfg->agc; 1260 pdata.agc_inv = cfg->agc_inv; 1261 pdata.clk_out = cfg->clock_out; 1262 pdata.envelope_mode = cfg->envelope_mode; 1263 pdata.lnb_hv_pol = cfg->lnb_hv_pol; 1264 pdata.lnb_en_pol = cfg->lnb_en_pol; 1265 pdata.attach_in_use = true; 1266 1267 memset(&board_info, 0, sizeof(board_info)); 1268 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE); 1269 board_info.addr = cfg->i2c_addr; 1270 board_info.platform_data = &pdata; 1271 client = i2c_new_device(i2c, &board_info); 1272 if (!client || !client->dev.driver) 1273 return NULL; 1274 1275 *tuner_i2c_adapter = pdata.get_i2c_adapter(client); 1276 return pdata.get_dvb_frontend(client); 1277 } 1278 EXPORT_SYMBOL(m88ds3103_attach); 1279 1280 static struct dvb_frontend_ops m88ds3103_ops = { 1281 .delsys = {SYS_DVBS, SYS_DVBS2}, 1282 .info = { 1283 .name = "Montage Technology M88DS3103", 1284 .frequency_min = 950000, 1285 .frequency_max = 2150000, 1286 .frequency_tolerance = 5000, 1287 .symbol_rate_min = 1000000, 1288 .symbol_rate_max = 45000000, 1289 .caps = FE_CAN_INVERSION_AUTO | 1290 FE_CAN_FEC_1_2 | 1291 FE_CAN_FEC_2_3 | 1292 FE_CAN_FEC_3_4 | 1293 FE_CAN_FEC_4_5 | 1294 FE_CAN_FEC_5_6 | 1295 FE_CAN_FEC_6_7 | 1296 FE_CAN_FEC_7_8 | 1297 FE_CAN_FEC_8_9 | 1298 FE_CAN_FEC_AUTO | 1299 FE_CAN_QPSK | 1300 FE_CAN_RECOVER | 1301 FE_CAN_2G_MODULATION 1302 }, 1303 1304 .release = m88ds3103_release, 1305 1306 .get_tune_settings = m88ds3103_get_tune_settings, 1307 1308 .init = m88ds3103_init, 1309 .sleep = m88ds3103_sleep, 1310 1311 .set_frontend = m88ds3103_set_frontend, 1312 .get_frontend = m88ds3103_get_frontend, 1313 1314 .read_status = m88ds3103_read_status, 1315 .read_snr = m88ds3103_read_snr, 1316 .read_ber = m88ds3103_read_ber, 1317 1318 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd, 1319 .diseqc_send_burst = m88ds3103_diseqc_send_burst, 1320 1321 .set_tone = m88ds3103_set_tone, 1322 .set_voltage = m88ds3103_set_voltage, 1323 }; 1324 1325 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client) 1326 { 1327 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 1328 1329 dev_dbg(&client->dev, "\n"); 1330 1331 return &dev->fe; 1332 } 1333 1334 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client) 1335 { 1336 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 1337 1338 dev_dbg(&client->dev, "\n"); 1339 1340 return dev->i2c_adapter; 1341 } 1342 1343 static int m88ds3103_probe(struct i2c_client *client, 1344 const struct i2c_device_id *id) 1345 { 1346 struct m88ds3103_dev *dev; 1347 struct m88ds3103_platform_data *pdata = client->dev.platform_data; 1348 int ret; 1349 unsigned int utmp; 1350 1351 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1352 if (!dev) { 1353 ret = -ENOMEM; 1354 goto err; 1355 } 1356 1357 dev->client = client; 1358 dev->config.clock = pdata->clk; 1359 dev->config.i2c_wr_max = pdata->i2c_wr_max; 1360 dev->config.ts_mode = pdata->ts_mode; 1361 dev->config.ts_clk = pdata->ts_clk; 1362 dev->config.ts_clk_pol = pdata->ts_clk_pol; 1363 dev->config.spec_inv = pdata->spec_inv; 1364 dev->config.agc_inv = pdata->agc_inv; 1365 dev->config.clock_out = pdata->clk_out; 1366 dev->config.envelope_mode = pdata->envelope_mode; 1367 dev->config.agc = pdata->agc; 1368 dev->config.lnb_hv_pol = pdata->lnb_hv_pol; 1369 dev->config.lnb_en_pol = pdata->lnb_en_pol; 1370 dev->cfg = &dev->config; 1371 /* create regmap */ 1372 dev->regmap_config.reg_bits = 8, 1373 dev->regmap_config.val_bits = 8, 1374 dev->regmap_config.lock_arg = dev, 1375 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config); 1376 if (IS_ERR(dev->regmap)) { 1377 ret = PTR_ERR(dev->regmap); 1378 goto err_kfree; 1379 } 1380 1381 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */ 1382 ret = regmap_read(dev->regmap, 0x00, &utmp); 1383 if (ret) 1384 goto err_kfree; 1385 1386 dev->chip_id = utmp >> 1; 1387 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id); 1388 1389 switch (dev->chip_id) { 1390 case M88RS6000_CHIP_ID: 1391 case M88DS3103_CHIP_ID: 1392 break; 1393 default: 1394 goto err_kfree; 1395 } 1396 1397 switch (dev->cfg->clock_out) { 1398 case M88DS3103_CLOCK_OUT_DISABLED: 1399 utmp = 0x80; 1400 break; 1401 case M88DS3103_CLOCK_OUT_ENABLED: 1402 utmp = 0x00; 1403 break; 1404 case M88DS3103_CLOCK_OUT_ENABLED_DIV2: 1405 utmp = 0x10; 1406 break; 1407 default: 1408 ret = -EINVAL; 1409 goto err_kfree; 1410 } 1411 1412 /* 0x29 register is defined differently for m88rs6000. */ 1413 /* set internal tuner address to 0x21 */ 1414 if (dev->chip_id == M88RS6000_CHIP_ID) 1415 utmp = 0x00; 1416 1417 ret = regmap_write(dev->regmap, 0x29, utmp); 1418 if (ret) 1419 goto err_kfree; 1420 1421 /* sleep */ 1422 ret = regmap_update_bits(dev->regmap, 0x08, 0x01, 0x00); 1423 if (ret) 1424 goto err_kfree; 1425 ret = regmap_update_bits(dev->regmap, 0x04, 0x01, 0x01); 1426 if (ret) 1427 goto err_kfree; 1428 ret = regmap_update_bits(dev->regmap, 0x23, 0x10, 0x10); 1429 if (ret) 1430 goto err_kfree; 1431 1432 /* create mux i2c adapter for tuner */ 1433 dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev, 1434 dev, 0, 0, 0, m88ds3103_select, 1435 NULL); 1436 if (dev->i2c_adapter == NULL) { 1437 ret = -ENOMEM; 1438 goto err_kfree; 1439 } 1440 1441 /* create dvb_frontend */ 1442 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops)); 1443 if (dev->chip_id == M88RS6000_CHIP_ID) 1444 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000", 1445 sizeof(dev->fe.ops.info.name)); 1446 if (!pdata->attach_in_use) 1447 dev->fe.ops.release = NULL; 1448 dev->fe.demodulator_priv = dev; 1449 i2c_set_clientdata(client, dev); 1450 1451 /* setup callbacks */ 1452 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend; 1453 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter; 1454 return 0; 1455 err_kfree: 1456 kfree(dev); 1457 err: 1458 dev_dbg(&client->dev, "failed=%d\n", ret); 1459 return ret; 1460 } 1461 1462 static int m88ds3103_remove(struct i2c_client *client) 1463 { 1464 struct m88ds3103_dev *dev = i2c_get_clientdata(client); 1465 1466 dev_dbg(&client->dev, "\n"); 1467 1468 i2c_del_mux_adapter(dev->i2c_adapter); 1469 1470 kfree(dev); 1471 return 0; 1472 } 1473 1474 static const struct i2c_device_id m88ds3103_id_table[] = { 1475 {"m88ds3103", 0}, 1476 {} 1477 }; 1478 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table); 1479 1480 static struct i2c_driver m88ds3103_driver = { 1481 .driver = { 1482 .owner = THIS_MODULE, 1483 .name = "m88ds3103", 1484 .suppress_bind_attrs = true, 1485 }, 1486 .probe = m88ds3103_probe, 1487 .remove = m88ds3103_remove, 1488 .id_table = m88ds3103_id_table, 1489 }; 1490 1491 module_i2c_driver(m88ds3103_driver); 1492 1493 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 1494 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver"); 1495 MODULE_LICENSE("GPL"); 1496 MODULE_FIRMWARE(M88DS3103_FIRMWARE); 1497 MODULE_FIRMWARE(M88RS6000_FIRMWARE); 1498