1 /* 2 Montage Technology DS3000 - DVBS/S2 Demodulator driver 3 Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 4 5 Copyright (C) 2009-2012 TurboSight.com 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/firmware.h> 28 29 #include "dvb_frontend.h" 30 #include "ts2020.h" 31 #include "ds3000.h" 32 33 static int debug; 34 35 #define dprintk(args...) \ 36 do { \ 37 if (debug) \ 38 printk(args); \ 39 } while (0) 40 41 /* as of March 2009 current DS3000 firmware version is 1.78 */ 42 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */ 43 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw" 44 45 #define DS3000_SAMPLE_RATE 96000 /* in kHz */ 46 47 /* Register values to initialise the demod in DVB-S mode */ 48 static u8 ds3000_dvbs_init_tab[] = { 49 0x23, 0x05, 50 0x08, 0x03, 51 0x0c, 0x00, 52 0x21, 0x54, 53 0x25, 0x82, 54 0x27, 0x31, 55 0x30, 0x08, 56 0x31, 0x40, 57 0x32, 0x32, 58 0x33, 0x35, 59 0x35, 0xff, 60 0x3a, 0x00, 61 0x37, 0x10, 62 0x38, 0x10, 63 0x39, 0x02, 64 0x42, 0x60, 65 0x4a, 0x40, 66 0x4b, 0x04, 67 0x4d, 0x91, 68 0x5d, 0xc8, 69 0x50, 0x77, 70 0x51, 0x77, 71 0x52, 0x36, 72 0x53, 0x36, 73 0x56, 0x01, 74 0x63, 0x43, 75 0x64, 0x30, 76 0x65, 0x40, 77 0x68, 0x26, 78 0x69, 0x4c, 79 0x70, 0x20, 80 0x71, 0x70, 81 0x72, 0x04, 82 0x73, 0x00, 83 0x70, 0x40, 84 0x71, 0x70, 85 0x72, 0x04, 86 0x73, 0x00, 87 0x70, 0x60, 88 0x71, 0x70, 89 0x72, 0x04, 90 0x73, 0x00, 91 0x70, 0x80, 92 0x71, 0x70, 93 0x72, 0x04, 94 0x73, 0x00, 95 0x70, 0xa0, 96 0x71, 0x70, 97 0x72, 0x04, 98 0x73, 0x00, 99 0x70, 0x1f, 100 0x76, 0x00, 101 0x77, 0xd1, 102 0x78, 0x0c, 103 0x79, 0x80, 104 0x7f, 0x04, 105 0x7c, 0x00, 106 0x80, 0x86, 107 0x81, 0xa6, 108 0x85, 0x04, 109 0xcd, 0xf4, 110 0x90, 0x33, 111 0xa0, 0x44, 112 0xc0, 0x18, 113 0xc3, 0x10, 114 0xc4, 0x08, 115 0xc5, 0x80, 116 0xc6, 0x80, 117 0xc7, 0x0a, 118 0xc8, 0x1a, 119 0xc9, 0x80, 120 0xfe, 0x92, 121 0xe0, 0xf8, 122 0xe6, 0x8b, 123 0xd0, 0x40, 124 0xf8, 0x20, 125 0xfa, 0x0f, 126 0xfd, 0x20, 127 0xad, 0x20, 128 0xae, 0x07, 129 0xb8, 0x00, 130 }; 131 132 /* Register values to initialise the demod in DVB-S2 mode */ 133 static u8 ds3000_dvbs2_init_tab[] = { 134 0x23, 0x0f, 135 0x08, 0x07, 136 0x0c, 0x00, 137 0x21, 0x54, 138 0x25, 0x82, 139 0x27, 0x31, 140 0x30, 0x08, 141 0x31, 0x32, 142 0x32, 0x32, 143 0x33, 0x35, 144 0x35, 0xff, 145 0x3a, 0x00, 146 0x37, 0x10, 147 0x38, 0x10, 148 0x39, 0x02, 149 0x42, 0x60, 150 0x4a, 0x80, 151 0x4b, 0x04, 152 0x4d, 0x81, 153 0x5d, 0x88, 154 0x50, 0x36, 155 0x51, 0x36, 156 0x52, 0x36, 157 0x53, 0x36, 158 0x63, 0x60, 159 0x64, 0x10, 160 0x65, 0x10, 161 0x68, 0x04, 162 0x69, 0x29, 163 0x70, 0x20, 164 0x71, 0x70, 165 0x72, 0x04, 166 0x73, 0x00, 167 0x70, 0x40, 168 0x71, 0x70, 169 0x72, 0x04, 170 0x73, 0x00, 171 0x70, 0x60, 172 0x71, 0x70, 173 0x72, 0x04, 174 0x73, 0x00, 175 0x70, 0x80, 176 0x71, 0x70, 177 0x72, 0x04, 178 0x73, 0x00, 179 0x70, 0xa0, 180 0x71, 0x70, 181 0x72, 0x04, 182 0x73, 0x00, 183 0x70, 0x1f, 184 0xa0, 0x44, 185 0xc0, 0x08, 186 0xc1, 0x10, 187 0xc2, 0x08, 188 0xc3, 0x10, 189 0xc4, 0x08, 190 0xc5, 0xf0, 191 0xc6, 0xf0, 192 0xc7, 0x0a, 193 0xc8, 0x1a, 194 0xc9, 0x80, 195 0xca, 0x23, 196 0xcb, 0x24, 197 0xce, 0x74, 198 0x90, 0x03, 199 0x76, 0x80, 200 0x77, 0x42, 201 0x78, 0x0a, 202 0x79, 0x80, 203 0xad, 0x40, 204 0xae, 0x07, 205 0x7f, 0xd4, 206 0x7c, 0x00, 207 0x80, 0xa8, 208 0x81, 0xda, 209 0x7c, 0x01, 210 0x80, 0xda, 211 0x81, 0xec, 212 0x7c, 0x02, 213 0x80, 0xca, 214 0x81, 0xeb, 215 0x7c, 0x03, 216 0x80, 0xba, 217 0x81, 0xdb, 218 0x85, 0x08, 219 0x86, 0x00, 220 0x87, 0x02, 221 0x89, 0x80, 222 0x8b, 0x44, 223 0x8c, 0xaa, 224 0x8a, 0x10, 225 0xba, 0x00, 226 0xf5, 0x04, 227 0xfe, 0x44, 228 0xd2, 0x32, 229 0xb8, 0x00, 230 }; 231 232 struct ds3000_state { 233 struct i2c_adapter *i2c; 234 const struct ds3000_config *config; 235 struct dvb_frontend frontend; 236 /* previous uncorrected block counter for DVB-S2 */ 237 u16 prevUCBS2; 238 }; 239 240 static int ds3000_writereg(struct ds3000_state *state, int reg, int data) 241 { 242 u8 buf[] = { reg, data }; 243 struct i2c_msg msg = { .addr = state->config->demod_address, 244 .flags = 0, .buf = buf, .len = 2 }; 245 int err; 246 247 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); 248 249 err = i2c_transfer(state->i2c, &msg, 1); 250 if (err != 1) { 251 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x," 252 " value == 0x%02x)\n", __func__, err, reg, data); 253 return -EREMOTEIO; 254 } 255 256 return 0; 257 } 258 259 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 260 { 261 struct ds3000_state *state = fe->demodulator_priv; 262 263 if (enable) 264 ds3000_writereg(state, 0x03, 0x12); 265 else 266 ds3000_writereg(state, 0x03, 0x02); 267 268 return 0; 269 } 270 271 /* I2C write for 8k firmware load */ 272 static int ds3000_writeFW(struct ds3000_state *state, int reg, 273 const u8 *data, u16 len) 274 { 275 int i, ret = 0; 276 struct i2c_msg msg; 277 u8 *buf; 278 279 buf = kmalloc(33, GFP_KERNEL); 280 if (buf == NULL) { 281 printk(KERN_ERR "Unable to kmalloc\n"); 282 return -ENOMEM; 283 } 284 285 *(buf) = reg; 286 287 msg.addr = state->config->demod_address; 288 msg.flags = 0; 289 msg.buf = buf; 290 msg.len = 33; 291 292 for (i = 0; i < len; i += 32) { 293 memcpy(buf + 1, data + i, 32); 294 295 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); 296 297 ret = i2c_transfer(state->i2c, &msg, 1); 298 if (ret != 1) { 299 printk(KERN_ERR "%s: write error(err == %i, " 300 "reg == 0x%02x\n", __func__, ret, reg); 301 ret = -EREMOTEIO; 302 goto error; 303 } 304 } 305 ret = 0; 306 307 error: 308 kfree(buf); 309 310 return ret; 311 } 312 313 static int ds3000_readreg(struct ds3000_state *state, u8 reg) 314 { 315 int ret; 316 u8 b0[] = { reg }; 317 u8 b1[] = { 0 }; 318 struct i2c_msg msg[] = { 319 { 320 .addr = state->config->demod_address, 321 .flags = 0, 322 .buf = b0, 323 .len = 1 324 }, { 325 .addr = state->config->demod_address, 326 .flags = I2C_M_RD, 327 .buf = b1, 328 .len = 1 329 } 330 }; 331 332 ret = i2c_transfer(state->i2c, msg, 2); 333 334 if (ret != 2) { 335 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); 336 return ret; 337 } 338 339 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); 340 341 return b1[0]; 342 } 343 344 static int ds3000_load_firmware(struct dvb_frontend *fe, 345 const struct firmware *fw); 346 347 static int ds3000_firmware_ondemand(struct dvb_frontend *fe) 348 { 349 struct ds3000_state *state = fe->demodulator_priv; 350 const struct firmware *fw; 351 int ret = 0; 352 353 dprintk("%s()\n", __func__); 354 355 ret = ds3000_readreg(state, 0xb2); 356 if (ret < 0) 357 return ret; 358 359 /* Load firmware */ 360 /* request the firmware, this will block until someone uploads it */ 361 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, 362 DS3000_DEFAULT_FIRMWARE); 363 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, 364 state->i2c->dev.parent); 365 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__); 366 if (ret) { 367 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not " 368 "found?)\n", __func__); 369 return ret; 370 } 371 372 ret = ds3000_load_firmware(fe, fw); 373 if (ret) 374 printk("%s: Writing firmware to device failed\n", __func__); 375 376 release_firmware(fw); 377 378 dprintk("%s: Firmware upload %s\n", __func__, 379 ret == 0 ? "complete" : "failed"); 380 381 return ret; 382 } 383 384 static int ds3000_load_firmware(struct dvb_frontend *fe, 385 const struct firmware *fw) 386 { 387 struct ds3000_state *state = fe->demodulator_priv; 388 int ret = 0; 389 390 dprintk("%s\n", __func__); 391 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n", 392 fw->size, 393 fw->data[0], 394 fw->data[1], 395 fw->data[fw->size - 2], 396 fw->data[fw->size - 1]); 397 398 /* Begin the firmware load process */ 399 ds3000_writereg(state, 0xb2, 0x01); 400 /* write the entire firmware */ 401 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size); 402 ds3000_writereg(state, 0xb2, 0x00); 403 404 return ret; 405 } 406 407 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 408 { 409 struct ds3000_state *state = fe->demodulator_priv; 410 u8 data; 411 412 dprintk("%s(%d)\n", __func__, voltage); 413 414 data = ds3000_readreg(state, 0xa2); 415 data |= 0x03; /* bit0 V/H, bit1 off/on */ 416 417 switch (voltage) { 418 case SEC_VOLTAGE_18: 419 data &= ~0x03; 420 break; 421 case SEC_VOLTAGE_13: 422 data &= ~0x03; 423 data |= 0x01; 424 break; 425 case SEC_VOLTAGE_OFF: 426 break; 427 } 428 429 ds3000_writereg(state, 0xa2, data); 430 431 return 0; 432 } 433 434 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status) 435 { 436 struct ds3000_state *state = fe->demodulator_priv; 437 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 438 int lock; 439 440 *status = 0; 441 442 switch (c->delivery_system) { 443 case SYS_DVBS: 444 lock = ds3000_readreg(state, 0xd1); 445 if ((lock & 0x07) == 0x07) 446 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 447 FE_HAS_VITERBI | FE_HAS_SYNC | 448 FE_HAS_LOCK; 449 450 break; 451 case SYS_DVBS2: 452 lock = ds3000_readreg(state, 0x0d); 453 if ((lock & 0x8f) == 0x8f) 454 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 455 FE_HAS_VITERBI | FE_HAS_SYNC | 456 FE_HAS_LOCK; 457 458 break; 459 default: 460 return 1; 461 } 462 463 if (state->config->set_lock_led) 464 state->config->set_lock_led(fe, *status == 0 ? 0 : 1); 465 466 dprintk("%s: status = 0x%02x\n", __func__, lock); 467 468 return 0; 469 } 470 471 /* read DS3000 BER value */ 472 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber) 473 { 474 struct ds3000_state *state = fe->demodulator_priv; 475 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 476 u8 data; 477 u32 ber_reading, lpdc_frames; 478 479 dprintk("%s()\n", __func__); 480 481 switch (c->delivery_system) { 482 case SYS_DVBS: 483 /* set the number of bytes checked during 484 BER estimation */ 485 ds3000_writereg(state, 0xf9, 0x04); 486 /* read BER estimation status */ 487 data = ds3000_readreg(state, 0xf8); 488 /* check if BER estimation is ready */ 489 if ((data & 0x10) == 0) { 490 /* this is the number of error bits, 491 to calculate the bit error rate 492 divide to 8388608 */ 493 *ber = (ds3000_readreg(state, 0xf7) << 8) | 494 ds3000_readreg(state, 0xf6); 495 /* start counting error bits */ 496 /* need to be set twice 497 otherwise it fails sometimes */ 498 data |= 0x10; 499 ds3000_writereg(state, 0xf8, data); 500 ds3000_writereg(state, 0xf8, data); 501 } else 502 /* used to indicate that BER estimation 503 is not ready, i.e. BER is unknown */ 504 *ber = 0xffffffff; 505 break; 506 case SYS_DVBS2: 507 /* read the number of LPDC decoded frames */ 508 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | 509 (ds3000_readreg(state, 0xd6) << 8) | 510 ds3000_readreg(state, 0xd5); 511 /* read the number of packets with bad CRC */ 512 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | 513 ds3000_readreg(state, 0xf7); 514 if (lpdc_frames > 750) { 515 /* clear LPDC frame counters */ 516 ds3000_writereg(state, 0xd1, 0x01); 517 /* clear bad packets counter */ 518 ds3000_writereg(state, 0xf9, 0x01); 519 /* enable bad packets counter */ 520 ds3000_writereg(state, 0xf9, 0x00); 521 /* enable LPDC frame counters */ 522 ds3000_writereg(state, 0xd1, 0x00); 523 *ber = ber_reading; 524 } else 525 /* used to indicate that BER estimation is not ready, 526 i.e. BER is unknown */ 527 *ber = 0xffffffff; 528 break; 529 default: 530 return 1; 531 } 532 533 return 0; 534 } 535 536 /* calculate DS3000 snr value in dB */ 537 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) 538 { 539 struct ds3000_state *state = fe->demodulator_priv; 540 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 541 u8 snr_reading, snr_value; 542 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp; 543 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */ 544 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, 545 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, 546 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 547 }; 548 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */ 549 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, 550 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, 551 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, 552 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, 553 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, 554 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, 555 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, 556 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, 557 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, 558 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, 559 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, 560 0x49e9, 0x4a20, 0x4a57 561 }; 562 563 dprintk("%s()\n", __func__); 564 565 switch (c->delivery_system) { 566 case SYS_DVBS: 567 snr_reading = ds3000_readreg(state, 0xff); 568 snr_reading /= 8; 569 if (snr_reading == 0) 570 *snr = 0x0000; 571 else { 572 if (snr_reading > 20) 573 snr_reading = 20; 574 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026; 575 /* cook the value to be suitable for szap-s2 576 human readable output */ 577 *snr = snr_value * 8 * 655; 578 } 579 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 580 snr_reading, *snr); 581 break; 582 case SYS_DVBS2: 583 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + 584 (ds3000_readreg(state, 0x8d) << 4); 585 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); 586 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1; 587 if (tmp == 0) { 588 *snr = 0x0000; 589 return 0; 590 } 591 if (dvbs2_noise_reading == 0) { 592 snr_value = 0x0013; 593 /* cook the value to be suitable for szap-s2 594 human readable output */ 595 *snr = 0xffff; 596 return 0; 597 } 598 if (tmp > dvbs2_noise_reading) { 599 snr_reading = tmp / dvbs2_noise_reading; 600 if (snr_reading > 80) 601 snr_reading = 80; 602 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000; 603 /* cook the value to be suitable for szap-s2 604 human readable output */ 605 *snr = snr_value * 5 * 655; 606 } else { 607 snr_reading = dvbs2_noise_reading / tmp; 608 if (snr_reading > 80) 609 snr_reading = 80; 610 *snr = -(dvbs2_snr_tab[snr_reading] / 1000); 611 } 612 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 613 snr_reading, *snr); 614 break; 615 default: 616 return 1; 617 } 618 619 return 0; 620 } 621 622 /* read DS3000 uncorrected blocks */ 623 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 624 { 625 struct ds3000_state *state = fe->demodulator_priv; 626 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 627 u8 data; 628 u16 _ucblocks; 629 630 dprintk("%s()\n", __func__); 631 632 switch (c->delivery_system) { 633 case SYS_DVBS: 634 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | 635 ds3000_readreg(state, 0xf4); 636 data = ds3000_readreg(state, 0xf8); 637 /* clear packet counters */ 638 data &= ~0x20; 639 ds3000_writereg(state, 0xf8, data); 640 /* enable packet counters */ 641 data |= 0x20; 642 ds3000_writereg(state, 0xf8, data); 643 break; 644 case SYS_DVBS2: 645 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | 646 ds3000_readreg(state, 0xe1); 647 if (_ucblocks > state->prevUCBS2) 648 *ucblocks = _ucblocks - state->prevUCBS2; 649 else 650 *ucblocks = state->prevUCBS2 - _ucblocks; 651 state->prevUCBS2 = _ucblocks; 652 break; 653 default: 654 return 1; 655 } 656 657 return 0; 658 } 659 660 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 661 { 662 struct ds3000_state *state = fe->demodulator_priv; 663 u8 data; 664 665 dprintk("%s(%d)\n", __func__, tone); 666 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { 667 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone); 668 return -EINVAL; 669 } 670 671 data = ds3000_readreg(state, 0xa2); 672 data &= ~0xc0; 673 ds3000_writereg(state, 0xa2, data); 674 675 switch (tone) { 676 case SEC_TONE_ON: 677 dprintk("%s: setting tone on\n", __func__); 678 data = ds3000_readreg(state, 0xa1); 679 data &= ~0x43; 680 data |= 0x04; 681 ds3000_writereg(state, 0xa1, data); 682 break; 683 case SEC_TONE_OFF: 684 dprintk("%s: setting tone off\n", __func__); 685 data = ds3000_readreg(state, 0xa2); 686 data |= 0x80; 687 ds3000_writereg(state, 0xa2, data); 688 break; 689 } 690 691 return 0; 692 } 693 694 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe, 695 struct dvb_diseqc_master_cmd *d) 696 { 697 struct ds3000_state *state = fe->demodulator_priv; 698 int i; 699 u8 data; 700 701 /* Dump DiSEqC message */ 702 dprintk("%s(", __func__); 703 for (i = 0 ; i < d->msg_len;) { 704 dprintk("0x%02x", d->msg[i]); 705 if (++i < d->msg_len) 706 dprintk(", "); 707 } 708 709 /* enable DiSEqC message send pin */ 710 data = ds3000_readreg(state, 0xa2); 711 data &= ~0xc0; 712 ds3000_writereg(state, 0xa2, data); 713 714 /* DiSEqC message */ 715 for (i = 0; i < d->msg_len; i++) 716 ds3000_writereg(state, 0xa3 + i, d->msg[i]); 717 718 data = ds3000_readreg(state, 0xa1); 719 /* clear DiSEqC message length and status, 720 enable DiSEqC message send */ 721 data &= ~0xf8; 722 /* set DiSEqC mode, modulation active during 33 pulses, 723 set DiSEqC message length */ 724 data |= ((d->msg_len - 1) << 3) | 0x07; 725 ds3000_writereg(state, 0xa1, data); 726 727 /* wait up to 150ms for DiSEqC transmission to complete */ 728 for (i = 0; i < 15; i++) { 729 data = ds3000_readreg(state, 0xa1); 730 if ((data & 0x40) == 0) 731 break; 732 msleep(10); 733 } 734 735 /* DiSEqC timeout after 150ms */ 736 if (i == 15) { 737 data = ds3000_readreg(state, 0xa1); 738 data &= ~0x80; 739 data |= 0x40; 740 ds3000_writereg(state, 0xa1, data); 741 742 data = ds3000_readreg(state, 0xa2); 743 data &= ~0xc0; 744 data |= 0x80; 745 ds3000_writereg(state, 0xa2, data); 746 747 return 1; 748 } 749 750 data = ds3000_readreg(state, 0xa2); 751 data &= ~0xc0; 752 data |= 0x80; 753 ds3000_writereg(state, 0xa2, data); 754 755 return 0; 756 } 757 758 /* Send DiSEqC burst */ 759 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe, 760 fe_sec_mini_cmd_t burst) 761 { 762 struct ds3000_state *state = fe->demodulator_priv; 763 int i; 764 u8 data; 765 766 dprintk("%s()\n", __func__); 767 768 data = ds3000_readreg(state, 0xa2); 769 data &= ~0xc0; 770 ds3000_writereg(state, 0xa2, data); 771 772 /* DiSEqC burst */ 773 if (burst == SEC_MINI_A) 774 /* Unmodulated tone burst */ 775 ds3000_writereg(state, 0xa1, 0x02); 776 else if (burst == SEC_MINI_B) 777 /* Modulated tone burst */ 778 ds3000_writereg(state, 0xa1, 0x01); 779 else 780 return -EINVAL; 781 782 msleep(13); 783 for (i = 0; i < 5; i++) { 784 data = ds3000_readreg(state, 0xa1); 785 if ((data & 0x40) == 0) 786 break; 787 msleep(1); 788 } 789 790 if (i == 5) { 791 data = ds3000_readreg(state, 0xa1); 792 data &= ~0x80; 793 data |= 0x40; 794 ds3000_writereg(state, 0xa1, data); 795 796 data = ds3000_readreg(state, 0xa2); 797 data &= ~0xc0; 798 data |= 0x80; 799 ds3000_writereg(state, 0xa2, data); 800 801 return 1; 802 } 803 804 data = ds3000_readreg(state, 0xa2); 805 data &= ~0xc0; 806 data |= 0x80; 807 ds3000_writereg(state, 0xa2, data); 808 809 return 0; 810 } 811 812 static void ds3000_release(struct dvb_frontend *fe) 813 { 814 struct ds3000_state *state = fe->demodulator_priv; 815 816 if (state->config->set_lock_led) 817 state->config->set_lock_led(fe, 0); 818 819 dprintk("%s\n", __func__); 820 kfree(state); 821 } 822 823 static struct dvb_frontend_ops ds3000_ops; 824 825 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, 826 struct i2c_adapter *i2c) 827 { 828 struct ds3000_state *state = NULL; 829 int ret; 830 831 dprintk("%s\n", __func__); 832 833 /* allocate memory for the internal state */ 834 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL); 835 if (state == NULL) { 836 printk(KERN_ERR "Unable to kmalloc\n"); 837 goto error2; 838 } 839 840 state->config = config; 841 state->i2c = i2c; 842 state->prevUCBS2 = 0; 843 844 /* check if the demod is present */ 845 ret = ds3000_readreg(state, 0x00) & 0xfe; 846 if (ret != 0xe0) { 847 printk(KERN_ERR "Invalid probe, probably not a DS3000\n"); 848 goto error3; 849 } 850 851 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n", 852 ds3000_readreg(state, 0x02), 853 ds3000_readreg(state, 0x01)); 854 855 memcpy(&state->frontend.ops, &ds3000_ops, 856 sizeof(struct dvb_frontend_ops)); 857 state->frontend.demodulator_priv = state; 858 return &state->frontend; 859 860 error3: 861 kfree(state); 862 error2: 863 return NULL; 864 } 865 EXPORT_SYMBOL(ds3000_attach); 866 867 static int ds3000_set_carrier_offset(struct dvb_frontend *fe, 868 s32 carrier_offset_khz) 869 { 870 struct ds3000_state *state = fe->demodulator_priv; 871 s32 tmp; 872 873 tmp = carrier_offset_khz; 874 tmp *= 65536; 875 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE); 876 877 if (tmp < 0) 878 tmp += 65536; 879 880 ds3000_writereg(state, 0x5f, tmp >> 8); 881 ds3000_writereg(state, 0x5e, tmp & 0xff); 882 883 return 0; 884 } 885 886 static int ds3000_set_frontend(struct dvb_frontend *fe) 887 { 888 struct ds3000_state *state = fe->demodulator_priv; 889 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 890 891 int i; 892 fe_status_t status; 893 s32 offset_khz; 894 u32 frequency; 895 u16 value; 896 897 dprintk("%s() ", __func__); 898 899 if (state->config->set_ts_params) 900 state->config->set_ts_params(fe, 0); 901 /* Tune */ 902 if (fe->ops.tuner_ops.set_params) 903 fe->ops.tuner_ops.set_params(fe); 904 905 /* ds3000 global reset */ 906 ds3000_writereg(state, 0x07, 0x80); 907 ds3000_writereg(state, 0x07, 0x00); 908 /* ds3000 build-in uC reset */ 909 ds3000_writereg(state, 0xb2, 0x01); 910 /* ds3000 software reset */ 911 ds3000_writereg(state, 0x00, 0x01); 912 913 switch (c->delivery_system) { 914 case SYS_DVBS: 915 /* initialise the demod in DVB-S mode */ 916 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) 917 ds3000_writereg(state, 918 ds3000_dvbs_init_tab[i], 919 ds3000_dvbs_init_tab[i + 1]); 920 value = ds3000_readreg(state, 0xfe); 921 value &= 0xc0; 922 value |= 0x1b; 923 ds3000_writereg(state, 0xfe, value); 924 break; 925 case SYS_DVBS2: 926 /* initialise the demod in DVB-S2 mode */ 927 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) 928 ds3000_writereg(state, 929 ds3000_dvbs2_init_tab[i], 930 ds3000_dvbs2_init_tab[i + 1]); 931 if (c->symbol_rate >= 30000000) 932 ds3000_writereg(state, 0xfe, 0x54); 933 else 934 ds3000_writereg(state, 0xfe, 0x98); 935 break; 936 default: 937 return 1; 938 } 939 940 /* enable 27MHz clock output */ 941 ds3000_writereg(state, 0x29, 0x80); 942 /* enable ac coupling */ 943 ds3000_writereg(state, 0x25, 0x8a); 944 945 /* enhance symbol rate performance */ 946 if ((c->symbol_rate / 1000) <= 5000) { 947 value = 29777 / (c->symbol_rate / 1000) + 1; 948 if (value % 2 != 0) 949 value++; 950 ds3000_writereg(state, 0xc3, 0x0d); 951 ds3000_writereg(state, 0xc8, value); 952 ds3000_writereg(state, 0xc4, 0x10); 953 ds3000_writereg(state, 0xc7, 0x0e); 954 } else if ((c->symbol_rate / 1000) <= 10000) { 955 value = 92166 / (c->symbol_rate / 1000) + 1; 956 if (value % 2 != 0) 957 value++; 958 ds3000_writereg(state, 0xc3, 0x07); 959 ds3000_writereg(state, 0xc8, value); 960 ds3000_writereg(state, 0xc4, 0x09); 961 ds3000_writereg(state, 0xc7, 0x12); 962 } else if ((c->symbol_rate / 1000) <= 20000) { 963 value = 64516 / (c->symbol_rate / 1000) + 1; 964 ds3000_writereg(state, 0xc3, value); 965 ds3000_writereg(state, 0xc8, 0x0e); 966 ds3000_writereg(state, 0xc4, 0x07); 967 ds3000_writereg(state, 0xc7, 0x18); 968 } else { 969 value = 129032 / (c->symbol_rate / 1000) + 1; 970 ds3000_writereg(state, 0xc3, value); 971 ds3000_writereg(state, 0xc8, 0x0a); 972 ds3000_writereg(state, 0xc4, 0x05); 973 ds3000_writereg(state, 0xc7, 0x24); 974 } 975 976 /* normalized symbol rate rounded to the closest integer */ 977 value = (((c->symbol_rate / 1000) << 16) + 978 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE; 979 ds3000_writereg(state, 0x61, value & 0x00ff); 980 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); 981 982 /* co-channel interference cancellation disabled */ 983 ds3000_writereg(state, 0x56, 0x00); 984 985 /* equalizer disabled */ 986 ds3000_writereg(state, 0x76, 0x00); 987 988 /*ds3000_writereg(state, 0x08, 0x03); 989 ds3000_writereg(state, 0xfd, 0x22); 990 ds3000_writereg(state, 0x08, 0x07); 991 ds3000_writereg(state, 0xfd, 0x42); 992 ds3000_writereg(state, 0x08, 0x07);*/ 993 994 if (state->config->ci_mode) { 995 switch (c->delivery_system) { 996 case SYS_DVBS: 997 default: 998 ds3000_writereg(state, 0xfd, 0x80); 999 break; 1000 case SYS_DVBS2: 1001 ds3000_writereg(state, 0xfd, 0x01); 1002 break; 1003 } 1004 } 1005 1006 /* ds3000 out of software reset */ 1007 ds3000_writereg(state, 0x00, 0x00); 1008 /* start ds3000 build-in uC */ 1009 ds3000_writereg(state, 0xb2, 0x00); 1010 1011 if (fe->ops.tuner_ops.get_frequency) { 1012 fe->ops.tuner_ops.get_frequency(fe, &frequency); 1013 offset_khz = frequency - c->frequency; 1014 ds3000_set_carrier_offset(fe, offset_khz); 1015 } 1016 1017 for (i = 0; i < 30 ; i++) { 1018 ds3000_read_status(fe, &status); 1019 if (status & FE_HAS_LOCK) 1020 break; 1021 1022 msleep(10); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int ds3000_tune(struct dvb_frontend *fe, 1029 bool re_tune, 1030 unsigned int mode_flags, 1031 unsigned int *delay, 1032 fe_status_t *status) 1033 { 1034 if (re_tune) { 1035 int ret = ds3000_set_frontend(fe); 1036 if (ret) 1037 return ret; 1038 } 1039 1040 *delay = HZ / 5; 1041 1042 return ds3000_read_status(fe, status); 1043 } 1044 1045 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe) 1046 { 1047 struct ds3000_state *state = fe->demodulator_priv; 1048 1049 if (state->config->set_lock_led) 1050 state->config->set_lock_led(fe, 0); 1051 1052 dprintk("%s()\n", __func__); 1053 return DVBFE_ALGO_HW; 1054 } 1055 1056 /* 1057 * Initialise or wake up device 1058 * 1059 * Power config will reset and load initial firmware if required 1060 */ 1061 static int ds3000_initfe(struct dvb_frontend *fe) 1062 { 1063 struct ds3000_state *state = fe->demodulator_priv; 1064 int ret; 1065 1066 dprintk("%s()\n", __func__); 1067 /* hard reset */ 1068 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); 1069 msleep(1); 1070 1071 /* Load the firmware if required */ 1072 ret = ds3000_firmware_ondemand(fe); 1073 if (ret != 0) { 1074 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__); 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static struct dvb_frontend_ops ds3000_ops = { 1082 .delsys = { SYS_DVBS, SYS_DVBS2 }, 1083 .info = { 1084 .name = "Montage Technology DS3000", 1085 .frequency_min = 950000, 1086 .frequency_max = 2150000, 1087 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1088 .frequency_tolerance = 5000, 1089 .symbol_rate_min = 1000000, 1090 .symbol_rate_max = 45000000, 1091 .caps = FE_CAN_INVERSION_AUTO | 1092 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1093 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1094 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1095 FE_CAN_2G_MODULATION | 1096 FE_CAN_QPSK | FE_CAN_RECOVER 1097 }, 1098 1099 .release = ds3000_release, 1100 1101 .init = ds3000_initfe, 1102 .i2c_gate_ctrl = ds3000_i2c_gate_ctrl, 1103 .read_status = ds3000_read_status, 1104 .read_ber = ds3000_read_ber, 1105 .read_snr = ds3000_read_snr, 1106 .read_ucblocks = ds3000_read_ucblocks, 1107 .set_voltage = ds3000_set_voltage, 1108 .set_tone = ds3000_set_tone, 1109 .diseqc_send_master_cmd = ds3000_send_diseqc_msg, 1110 .diseqc_send_burst = ds3000_diseqc_send_burst, 1111 .get_frontend_algo = ds3000_get_algo, 1112 1113 .set_frontend = ds3000_set_frontend, 1114 .tune = ds3000_tune, 1115 }; 1116 1117 module_param(debug, int, 0644); 1118 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 1119 1120 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology " 1121 "DS3000 hardware"); 1122 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>"); 1123 MODULE_LICENSE("GPL"); 1124 MODULE_FIRMWARE(DS3000_DEFAULT_FIRMWARE); 1125