1 /* 2 Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver 3 Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com> 4 5 Copyright (C) 2009 TurboSight.com 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 #include <linux/slab.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/firmware.h> 28 29 #include "dvb_frontend.h" 30 #include "ds3000.h" 31 32 static int debug; 33 static int force_fw_upload; 34 35 #define dprintk(args...) \ 36 do { \ 37 if (debug) \ 38 printk(args); \ 39 } while (0) 40 41 /* as of March 2009 current DS3000 firmware version is 1.78 */ 42 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */ 43 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw" 44 45 #define DS3000_SAMPLE_RATE 96000 /* in kHz */ 46 #define DS3000_XTAL_FREQ 27000 /* in kHz */ 47 48 /* Register values to initialise the demod in DVB-S mode */ 49 static u8 ds3000_dvbs_init_tab[] = { 50 0x23, 0x05, 51 0x08, 0x03, 52 0x0c, 0x00, 53 0x21, 0x54, 54 0x25, 0x82, 55 0x27, 0x31, 56 0x30, 0x08, 57 0x31, 0x40, 58 0x32, 0x32, 59 0x33, 0x35, 60 0x35, 0xff, 61 0x3a, 0x00, 62 0x37, 0x10, 63 0x38, 0x10, 64 0x39, 0x02, 65 0x42, 0x60, 66 0x4a, 0x40, 67 0x4b, 0x04, 68 0x4d, 0x91, 69 0x5d, 0xc8, 70 0x50, 0x77, 71 0x51, 0x77, 72 0x52, 0x36, 73 0x53, 0x36, 74 0x56, 0x01, 75 0x63, 0x43, 76 0x64, 0x30, 77 0x65, 0x40, 78 0x68, 0x26, 79 0x69, 0x4c, 80 0x70, 0x20, 81 0x71, 0x70, 82 0x72, 0x04, 83 0x73, 0x00, 84 0x70, 0x40, 85 0x71, 0x70, 86 0x72, 0x04, 87 0x73, 0x00, 88 0x70, 0x60, 89 0x71, 0x70, 90 0x72, 0x04, 91 0x73, 0x00, 92 0x70, 0x80, 93 0x71, 0x70, 94 0x72, 0x04, 95 0x73, 0x00, 96 0x70, 0xa0, 97 0x71, 0x70, 98 0x72, 0x04, 99 0x73, 0x00, 100 0x70, 0x1f, 101 0x76, 0x00, 102 0x77, 0xd1, 103 0x78, 0x0c, 104 0x79, 0x80, 105 0x7f, 0x04, 106 0x7c, 0x00, 107 0x80, 0x86, 108 0x81, 0xa6, 109 0x85, 0x04, 110 0xcd, 0xf4, 111 0x90, 0x33, 112 0xa0, 0x44, 113 0xc0, 0x18, 114 0xc3, 0x10, 115 0xc4, 0x08, 116 0xc5, 0x80, 117 0xc6, 0x80, 118 0xc7, 0x0a, 119 0xc8, 0x1a, 120 0xc9, 0x80, 121 0xfe, 0x92, 122 0xe0, 0xf8, 123 0xe6, 0x8b, 124 0xd0, 0x40, 125 0xf8, 0x20, 126 0xfa, 0x0f, 127 0xfd, 0x20, 128 0xad, 0x20, 129 0xae, 0x07, 130 0xb8, 0x00, 131 }; 132 133 /* Register values to initialise the demod in DVB-S2 mode */ 134 static u8 ds3000_dvbs2_init_tab[] = { 135 0x23, 0x0f, 136 0x08, 0x07, 137 0x0c, 0x00, 138 0x21, 0x54, 139 0x25, 0x82, 140 0x27, 0x31, 141 0x30, 0x08, 142 0x31, 0x32, 143 0x32, 0x32, 144 0x33, 0x35, 145 0x35, 0xff, 146 0x3a, 0x00, 147 0x37, 0x10, 148 0x38, 0x10, 149 0x39, 0x02, 150 0x42, 0x60, 151 0x4a, 0x80, 152 0x4b, 0x04, 153 0x4d, 0x81, 154 0x5d, 0x88, 155 0x50, 0x36, 156 0x51, 0x36, 157 0x52, 0x36, 158 0x53, 0x36, 159 0x63, 0x60, 160 0x64, 0x10, 161 0x65, 0x10, 162 0x68, 0x04, 163 0x69, 0x29, 164 0x70, 0x20, 165 0x71, 0x70, 166 0x72, 0x04, 167 0x73, 0x00, 168 0x70, 0x40, 169 0x71, 0x70, 170 0x72, 0x04, 171 0x73, 0x00, 172 0x70, 0x60, 173 0x71, 0x70, 174 0x72, 0x04, 175 0x73, 0x00, 176 0x70, 0x80, 177 0x71, 0x70, 178 0x72, 0x04, 179 0x73, 0x00, 180 0x70, 0xa0, 181 0x71, 0x70, 182 0x72, 0x04, 183 0x73, 0x00, 184 0x70, 0x1f, 185 0xa0, 0x44, 186 0xc0, 0x08, 187 0xc1, 0x10, 188 0xc2, 0x08, 189 0xc3, 0x10, 190 0xc4, 0x08, 191 0xc5, 0xf0, 192 0xc6, 0xf0, 193 0xc7, 0x0a, 194 0xc8, 0x1a, 195 0xc9, 0x80, 196 0xca, 0x23, 197 0xcb, 0x24, 198 0xce, 0x74, 199 0x90, 0x03, 200 0x76, 0x80, 201 0x77, 0x42, 202 0x78, 0x0a, 203 0x79, 0x80, 204 0xad, 0x40, 205 0xae, 0x07, 206 0x7f, 0xd4, 207 0x7c, 0x00, 208 0x80, 0xa8, 209 0x81, 0xda, 210 0x7c, 0x01, 211 0x80, 0xda, 212 0x81, 0xec, 213 0x7c, 0x02, 214 0x80, 0xca, 215 0x81, 0xeb, 216 0x7c, 0x03, 217 0x80, 0xba, 218 0x81, 0xdb, 219 0x85, 0x08, 220 0x86, 0x00, 221 0x87, 0x02, 222 0x89, 0x80, 223 0x8b, 0x44, 224 0x8c, 0xaa, 225 0x8a, 0x10, 226 0xba, 0x00, 227 0xf5, 0x04, 228 0xfe, 0x44, 229 0xd2, 0x32, 230 0xb8, 0x00, 231 }; 232 233 struct ds3000_state { 234 struct i2c_adapter *i2c; 235 const struct ds3000_config *config; 236 struct dvb_frontend frontend; 237 u8 skip_fw_load; 238 /* previous uncorrected block counter for DVB-S2 */ 239 u16 prevUCBS2; 240 }; 241 242 static int ds3000_writereg(struct ds3000_state *state, int reg, int data) 243 { 244 u8 buf[] = { reg, data }; 245 struct i2c_msg msg = { .addr = state->config->demod_address, 246 .flags = 0, .buf = buf, .len = 2 }; 247 int err; 248 249 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); 250 251 err = i2c_transfer(state->i2c, &msg, 1); 252 if (err != 1) { 253 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x," 254 " value == 0x%02x)\n", __func__, err, reg, data); 255 return -EREMOTEIO; 256 } 257 258 return 0; 259 } 260 261 static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data) 262 { 263 u8 buf[] = { reg, data }; 264 struct i2c_msg msg = { .addr = 0x60, 265 .flags = 0, .buf = buf, .len = 2 }; 266 int err; 267 268 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); 269 270 ds3000_writereg(state, 0x03, 0x11); 271 err = i2c_transfer(state->i2c, &msg, 1); 272 if (err != 1) { 273 printk("%s: writereg error(err == %i, reg == 0x%02x," 274 " value == 0x%02x)\n", __func__, err, reg, data); 275 return -EREMOTEIO; 276 } 277 278 return 0; 279 } 280 281 /* I2C write for 8k firmware load */ 282 static int ds3000_writeFW(struct ds3000_state *state, int reg, 283 const u8 *data, u16 len) 284 { 285 int i, ret = -EREMOTEIO; 286 struct i2c_msg msg; 287 u8 *buf; 288 289 buf = kmalloc(33, GFP_KERNEL); 290 if (buf == NULL) { 291 printk(KERN_ERR "Unable to kmalloc\n"); 292 ret = -ENOMEM; 293 goto error; 294 } 295 296 *(buf) = reg; 297 298 msg.addr = state->config->demod_address; 299 msg.flags = 0; 300 msg.buf = buf; 301 msg.len = 33; 302 303 for (i = 0; i < len; i += 32) { 304 memcpy(buf + 1, data + i, 32); 305 306 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); 307 308 ret = i2c_transfer(state->i2c, &msg, 1); 309 if (ret != 1) { 310 printk(KERN_ERR "%s: write error(err == %i, " 311 "reg == 0x%02x\n", __func__, ret, reg); 312 ret = -EREMOTEIO; 313 } 314 } 315 316 error: 317 kfree(buf); 318 319 return ret; 320 } 321 322 static int ds3000_readreg(struct ds3000_state *state, u8 reg) 323 { 324 int ret; 325 u8 b0[] = { reg }; 326 u8 b1[] = { 0 }; 327 struct i2c_msg msg[] = { 328 { 329 .addr = state->config->demod_address, 330 .flags = 0, 331 .buf = b0, 332 .len = 1 333 }, { 334 .addr = state->config->demod_address, 335 .flags = I2C_M_RD, 336 .buf = b1, 337 .len = 1 338 } 339 }; 340 341 ret = i2c_transfer(state->i2c, msg, 2); 342 343 if (ret != 2) { 344 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); 345 return ret; 346 } 347 348 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); 349 350 return b1[0]; 351 } 352 353 static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg) 354 { 355 int ret; 356 u8 b0[] = { reg }; 357 u8 b1[] = { 0 }; 358 struct i2c_msg msg[] = { 359 { 360 .addr = 0x60, 361 .flags = 0, 362 .buf = b0, 363 .len = 1 364 }, { 365 .addr = 0x60, 366 .flags = I2C_M_RD, 367 .buf = b1, 368 .len = 1 369 } 370 }; 371 372 ds3000_writereg(state, 0x03, 0x12); 373 ret = i2c_transfer(state->i2c, msg, 2); 374 375 if (ret != 2) { 376 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); 377 return ret; 378 } 379 380 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); 381 382 return b1[0]; 383 } 384 385 static int ds3000_load_firmware(struct dvb_frontend *fe, 386 const struct firmware *fw); 387 388 static int ds3000_firmware_ondemand(struct dvb_frontend *fe) 389 { 390 struct ds3000_state *state = fe->demodulator_priv; 391 const struct firmware *fw; 392 int ret = 0; 393 394 dprintk("%s()\n", __func__); 395 396 ret = ds3000_readreg(state, 0xb2); 397 if (ret < 0) 398 return ret; 399 400 if (state->skip_fw_load || !force_fw_upload) 401 return 0; /* Firmware already uploaded, skipping */ 402 403 /* Load firmware */ 404 /* request the firmware, this will block until someone uploads it */ 405 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, 406 DS3000_DEFAULT_FIRMWARE); 407 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, 408 state->i2c->dev.parent); 409 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__); 410 if (ret) { 411 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not " 412 "found?)\n", __func__); 413 return ret; 414 } 415 416 /* Make sure we don't recurse back through here during loading */ 417 state->skip_fw_load = 1; 418 419 ret = ds3000_load_firmware(fe, fw); 420 if (ret) 421 printk("%s: Writing firmware to device failed\n", __func__); 422 423 release_firmware(fw); 424 425 dprintk("%s: Firmware upload %s\n", __func__, 426 ret == 0 ? "complete" : "failed"); 427 428 /* Ensure firmware is always loaded if required */ 429 state->skip_fw_load = 0; 430 431 return ret; 432 } 433 434 static int ds3000_load_firmware(struct dvb_frontend *fe, 435 const struct firmware *fw) 436 { 437 struct ds3000_state *state = fe->demodulator_priv; 438 439 dprintk("%s\n", __func__); 440 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n", 441 fw->size, 442 fw->data[0], 443 fw->data[1], 444 fw->data[fw->size - 2], 445 fw->data[fw->size - 1]); 446 447 /* Begin the firmware load process */ 448 ds3000_writereg(state, 0xb2, 0x01); 449 /* write the entire firmware */ 450 ds3000_writeFW(state, 0xb0, fw->data, fw->size); 451 ds3000_writereg(state, 0xb2, 0x00); 452 453 return 0; 454 } 455 456 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) 457 { 458 struct ds3000_state *state = fe->demodulator_priv; 459 u8 data; 460 461 dprintk("%s(%d)\n", __func__, voltage); 462 463 data = ds3000_readreg(state, 0xa2); 464 data |= 0x03; /* bit0 V/H, bit1 off/on */ 465 466 switch (voltage) { 467 case SEC_VOLTAGE_18: 468 data &= ~0x03; 469 break; 470 case SEC_VOLTAGE_13: 471 data &= ~0x03; 472 data |= 0x01; 473 break; 474 case SEC_VOLTAGE_OFF: 475 break; 476 } 477 478 ds3000_writereg(state, 0xa2, data); 479 480 return 0; 481 } 482 483 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status) 484 { 485 struct ds3000_state *state = fe->demodulator_priv; 486 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 487 int lock; 488 489 *status = 0; 490 491 switch (c->delivery_system) { 492 case SYS_DVBS: 493 lock = ds3000_readreg(state, 0xd1); 494 if ((lock & 0x07) == 0x07) 495 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 496 FE_HAS_VITERBI | FE_HAS_SYNC | 497 FE_HAS_LOCK; 498 499 break; 500 case SYS_DVBS2: 501 lock = ds3000_readreg(state, 0x0d); 502 if ((lock & 0x8f) == 0x8f) 503 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | 504 FE_HAS_VITERBI | FE_HAS_SYNC | 505 FE_HAS_LOCK; 506 507 break; 508 default: 509 return 1; 510 } 511 512 dprintk("%s: status = 0x%02x\n", __func__, lock); 513 514 return 0; 515 } 516 517 /* read DS3000 BER value */ 518 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber) 519 { 520 struct ds3000_state *state = fe->demodulator_priv; 521 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 522 u8 data; 523 u32 ber_reading, lpdc_frames; 524 525 dprintk("%s()\n", __func__); 526 527 switch (c->delivery_system) { 528 case SYS_DVBS: 529 /* set the number of bytes checked during 530 BER estimation */ 531 ds3000_writereg(state, 0xf9, 0x04); 532 /* read BER estimation status */ 533 data = ds3000_readreg(state, 0xf8); 534 /* check if BER estimation is ready */ 535 if ((data & 0x10) == 0) { 536 /* this is the number of error bits, 537 to calculate the bit error rate 538 divide to 8388608 */ 539 *ber = (ds3000_readreg(state, 0xf7) << 8) | 540 ds3000_readreg(state, 0xf6); 541 /* start counting error bits */ 542 /* need to be set twice 543 otherwise it fails sometimes */ 544 data |= 0x10; 545 ds3000_writereg(state, 0xf8, data); 546 ds3000_writereg(state, 0xf8, data); 547 } else 548 /* used to indicate that BER estimation 549 is not ready, i.e. BER is unknown */ 550 *ber = 0xffffffff; 551 break; 552 case SYS_DVBS2: 553 /* read the number of LPDC decoded frames */ 554 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) | 555 (ds3000_readreg(state, 0xd6) << 8) | 556 ds3000_readreg(state, 0xd5); 557 /* read the number of packets with bad CRC */ 558 ber_reading = (ds3000_readreg(state, 0xf8) << 8) | 559 ds3000_readreg(state, 0xf7); 560 if (lpdc_frames > 750) { 561 /* clear LPDC frame counters */ 562 ds3000_writereg(state, 0xd1, 0x01); 563 /* clear bad packets counter */ 564 ds3000_writereg(state, 0xf9, 0x01); 565 /* enable bad packets counter */ 566 ds3000_writereg(state, 0xf9, 0x00); 567 /* enable LPDC frame counters */ 568 ds3000_writereg(state, 0xd1, 0x00); 569 *ber = ber_reading; 570 } else 571 /* used to indicate that BER estimation is not ready, 572 i.e. BER is unknown */ 573 *ber = 0xffffffff; 574 break; 575 default: 576 return 1; 577 } 578 579 return 0; 580 } 581 582 /* read TS2020 signal strength */ 583 static int ds3000_read_signal_strength(struct dvb_frontend *fe, 584 u16 *signal_strength) 585 { 586 struct ds3000_state *state = fe->demodulator_priv; 587 u16 sig_reading, sig_strength; 588 u8 rfgain, bbgain; 589 590 dprintk("%s()\n", __func__); 591 592 rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f; 593 bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f; 594 595 if (rfgain > 15) 596 rfgain = 15; 597 if (bbgain > 13) 598 bbgain = 13; 599 600 sig_reading = rfgain * 2 + bbgain * 3; 601 602 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ; 603 604 /* cook the value to be suitable for szap-s2 human readable output */ 605 *signal_strength = sig_strength * 1000; 606 607 dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__, 608 sig_reading, *signal_strength); 609 610 return 0; 611 } 612 613 /* calculate DS3000 snr value in dB */ 614 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr) 615 { 616 struct ds3000_state *state = fe->demodulator_priv; 617 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 618 u8 snr_reading, snr_value; 619 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp; 620 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */ 621 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03, 622 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717, 623 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505 624 }; 625 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */ 626 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103, 627 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5, 628 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6, 629 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888, 630 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51, 631 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68, 632 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206, 633 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a, 634 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649, 635 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813, 636 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1, 637 0x49e9, 0x4a20, 0x4a57 638 }; 639 640 dprintk("%s()\n", __func__); 641 642 switch (c->delivery_system) { 643 case SYS_DVBS: 644 snr_reading = ds3000_readreg(state, 0xff); 645 snr_reading /= 8; 646 if (snr_reading == 0) 647 *snr = 0x0000; 648 else { 649 if (snr_reading > 20) 650 snr_reading = 20; 651 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026; 652 /* cook the value to be suitable for szap-s2 653 human readable output */ 654 *snr = snr_value * 8 * 655; 655 } 656 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 657 snr_reading, *snr); 658 break; 659 case SYS_DVBS2: 660 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) + 661 (ds3000_readreg(state, 0x8d) << 4); 662 dvbs2_signal_reading = ds3000_readreg(state, 0x8e); 663 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1; 664 if (tmp == 0) { 665 *snr = 0x0000; 666 return 0; 667 } 668 if (dvbs2_noise_reading == 0) { 669 snr_value = 0x0013; 670 /* cook the value to be suitable for szap-s2 671 human readable output */ 672 *snr = 0xffff; 673 return 0; 674 } 675 if (tmp > dvbs2_noise_reading) { 676 snr_reading = tmp / dvbs2_noise_reading; 677 if (snr_reading > 80) 678 snr_reading = 80; 679 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000; 680 /* cook the value to be suitable for szap-s2 681 human readable output */ 682 *snr = snr_value * 5 * 655; 683 } else { 684 snr_reading = dvbs2_noise_reading / tmp; 685 if (snr_reading > 80) 686 snr_reading = 80; 687 *snr = -(dvbs2_snr_tab[snr_reading] / 1000); 688 } 689 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__, 690 snr_reading, *snr); 691 break; 692 default: 693 return 1; 694 } 695 696 return 0; 697 } 698 699 /* read DS3000 uncorrected blocks */ 700 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) 701 { 702 struct ds3000_state *state = fe->demodulator_priv; 703 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 704 u8 data; 705 u16 _ucblocks; 706 707 dprintk("%s()\n", __func__); 708 709 switch (c->delivery_system) { 710 case SYS_DVBS: 711 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) | 712 ds3000_readreg(state, 0xf4); 713 data = ds3000_readreg(state, 0xf8); 714 /* clear packet counters */ 715 data &= ~0x20; 716 ds3000_writereg(state, 0xf8, data); 717 /* enable packet counters */ 718 data |= 0x20; 719 ds3000_writereg(state, 0xf8, data); 720 break; 721 case SYS_DVBS2: 722 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) | 723 ds3000_readreg(state, 0xe1); 724 if (_ucblocks > state->prevUCBS2) 725 *ucblocks = _ucblocks - state->prevUCBS2; 726 else 727 *ucblocks = state->prevUCBS2 - _ucblocks; 728 state->prevUCBS2 = _ucblocks; 729 break; 730 default: 731 return 1; 732 } 733 734 return 0; 735 } 736 737 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) 738 { 739 struct ds3000_state *state = fe->demodulator_priv; 740 u8 data; 741 742 dprintk("%s(%d)\n", __func__, tone); 743 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { 744 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone); 745 return -EINVAL; 746 } 747 748 data = ds3000_readreg(state, 0xa2); 749 data &= ~0xc0; 750 ds3000_writereg(state, 0xa2, data); 751 752 switch (tone) { 753 case SEC_TONE_ON: 754 dprintk("%s: setting tone on\n", __func__); 755 data = ds3000_readreg(state, 0xa1); 756 data &= ~0x43; 757 data |= 0x04; 758 ds3000_writereg(state, 0xa1, data); 759 break; 760 case SEC_TONE_OFF: 761 dprintk("%s: setting tone off\n", __func__); 762 data = ds3000_readreg(state, 0xa2); 763 data |= 0x80; 764 ds3000_writereg(state, 0xa2, data); 765 break; 766 } 767 768 return 0; 769 } 770 771 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe, 772 struct dvb_diseqc_master_cmd *d) 773 { 774 struct ds3000_state *state = fe->demodulator_priv; 775 int i; 776 u8 data; 777 778 /* Dump DiSEqC message */ 779 dprintk("%s(", __func__); 780 for (i = 0 ; i < d->msg_len;) { 781 dprintk("0x%02x", d->msg[i]); 782 if (++i < d->msg_len) 783 dprintk(", "); 784 } 785 786 /* enable DiSEqC message send pin */ 787 data = ds3000_readreg(state, 0xa2); 788 data &= ~0xc0; 789 ds3000_writereg(state, 0xa2, data); 790 791 /* DiSEqC message */ 792 for (i = 0; i < d->msg_len; i++) 793 ds3000_writereg(state, 0xa3 + i, d->msg[i]); 794 795 data = ds3000_readreg(state, 0xa1); 796 /* clear DiSEqC message length and status, 797 enable DiSEqC message send */ 798 data &= ~0xf8; 799 /* set DiSEqC mode, modulation active during 33 pulses, 800 set DiSEqC message length */ 801 data |= ((d->msg_len - 1) << 3) | 0x07; 802 ds3000_writereg(state, 0xa1, data); 803 804 /* wait up to 150ms for DiSEqC transmission to complete */ 805 for (i = 0; i < 15; i++) { 806 data = ds3000_readreg(state, 0xa1); 807 if ((data & 0x40) == 0) 808 break; 809 msleep(10); 810 } 811 812 /* DiSEqC timeout after 150ms */ 813 if (i == 15) { 814 data = ds3000_readreg(state, 0xa1); 815 data &= ~0x80; 816 data |= 0x40; 817 ds3000_writereg(state, 0xa1, data); 818 819 data = ds3000_readreg(state, 0xa2); 820 data &= ~0xc0; 821 data |= 0x80; 822 ds3000_writereg(state, 0xa2, data); 823 824 return 1; 825 } 826 827 data = ds3000_readreg(state, 0xa2); 828 data &= ~0xc0; 829 data |= 0x80; 830 ds3000_writereg(state, 0xa2, data); 831 832 return 0; 833 } 834 835 /* Send DiSEqC burst */ 836 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe, 837 fe_sec_mini_cmd_t burst) 838 { 839 struct ds3000_state *state = fe->demodulator_priv; 840 int i; 841 u8 data; 842 843 dprintk("%s()\n", __func__); 844 845 data = ds3000_readreg(state, 0xa2); 846 data &= ~0xc0; 847 ds3000_writereg(state, 0xa2, data); 848 849 /* DiSEqC burst */ 850 if (burst == SEC_MINI_A) 851 /* Unmodulated tone burst */ 852 ds3000_writereg(state, 0xa1, 0x02); 853 else if (burst == SEC_MINI_B) 854 /* Modulated tone burst */ 855 ds3000_writereg(state, 0xa1, 0x01); 856 else 857 return -EINVAL; 858 859 msleep(13); 860 for (i = 0; i < 5; i++) { 861 data = ds3000_readreg(state, 0xa1); 862 if ((data & 0x40) == 0) 863 break; 864 msleep(1); 865 } 866 867 if (i == 5) { 868 data = ds3000_readreg(state, 0xa1); 869 data &= ~0x80; 870 data |= 0x40; 871 ds3000_writereg(state, 0xa1, data); 872 873 data = ds3000_readreg(state, 0xa2); 874 data &= ~0xc0; 875 data |= 0x80; 876 ds3000_writereg(state, 0xa2, data); 877 878 return 1; 879 } 880 881 data = ds3000_readreg(state, 0xa2); 882 data &= ~0xc0; 883 data |= 0x80; 884 ds3000_writereg(state, 0xa2, data); 885 886 return 0; 887 } 888 889 static void ds3000_release(struct dvb_frontend *fe) 890 { 891 struct ds3000_state *state = fe->demodulator_priv; 892 dprintk("%s\n", __func__); 893 kfree(state); 894 } 895 896 static struct dvb_frontend_ops ds3000_ops; 897 898 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, 899 struct i2c_adapter *i2c) 900 { 901 struct ds3000_state *state = NULL; 902 int ret; 903 904 dprintk("%s\n", __func__); 905 906 /* allocate memory for the internal state */ 907 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL); 908 if (state == NULL) { 909 printk(KERN_ERR "Unable to kmalloc\n"); 910 goto error2; 911 } 912 913 state->config = config; 914 state->i2c = i2c; 915 state->prevUCBS2 = 0; 916 917 /* check if the demod is present */ 918 ret = ds3000_readreg(state, 0x00) & 0xfe; 919 if (ret != 0xe0) { 920 printk(KERN_ERR "Invalid probe, probably not a DS3000\n"); 921 goto error3; 922 } 923 924 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n", 925 ds3000_readreg(state, 0x02), 926 ds3000_readreg(state, 0x01)); 927 928 memcpy(&state->frontend.ops, &ds3000_ops, 929 sizeof(struct dvb_frontend_ops)); 930 state->frontend.demodulator_priv = state; 931 return &state->frontend; 932 933 error3: 934 kfree(state); 935 error2: 936 return NULL; 937 } 938 EXPORT_SYMBOL(ds3000_attach); 939 940 static int ds3000_set_carrier_offset(struct dvb_frontend *fe, 941 s32 carrier_offset_khz) 942 { 943 struct ds3000_state *state = fe->demodulator_priv; 944 s32 tmp; 945 946 tmp = carrier_offset_khz; 947 tmp *= 65536; 948 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE); 949 950 if (tmp < 0) 951 tmp += 65536; 952 953 ds3000_writereg(state, 0x5f, tmp >> 8); 954 ds3000_writereg(state, 0x5e, tmp & 0xff); 955 956 return 0; 957 } 958 959 static int ds3000_set_frontend(struct dvb_frontend *fe) 960 { 961 struct ds3000_state *state = fe->demodulator_priv; 962 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 963 964 int i; 965 fe_status_t status; 966 u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4; 967 s32 offset_khz; 968 u16 value, ndiv; 969 u32 f3db; 970 971 dprintk("%s() ", __func__); 972 973 if (state->config->set_ts_params) 974 state->config->set_ts_params(fe, 0); 975 /* Tune */ 976 /* unknown */ 977 ds3000_tuner_writereg(state, 0x07, 0x02); 978 ds3000_tuner_writereg(state, 0x10, 0x00); 979 ds3000_tuner_writereg(state, 0x60, 0x79); 980 ds3000_tuner_writereg(state, 0x08, 0x01); 981 ds3000_tuner_writereg(state, 0x00, 0x01); 982 div4 = 0; 983 984 /* calculate and set freq divider */ 985 if (c->frequency < 1146000) { 986 ds3000_tuner_writereg(state, 0x10, 0x11); 987 div4 = 1; 988 ndiv = ((c->frequency * (6 + 8) * 4) + 989 (DS3000_XTAL_FREQ / 2)) / 990 DS3000_XTAL_FREQ - 1024; 991 } else { 992 ds3000_tuner_writereg(state, 0x10, 0x01); 993 ndiv = ((c->frequency * (6 + 8) * 2) + 994 (DS3000_XTAL_FREQ / 2)) / 995 DS3000_XTAL_FREQ - 1024; 996 } 997 998 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8); 999 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff); 1000 1001 /* set pll */ 1002 ds3000_tuner_writereg(state, 0x03, 0x06); 1003 ds3000_tuner_writereg(state, 0x51, 0x0f); 1004 ds3000_tuner_writereg(state, 0x51, 0x1f); 1005 ds3000_tuner_writereg(state, 0x50, 0x10); 1006 ds3000_tuner_writereg(state, 0x50, 0x00); 1007 msleep(5); 1008 1009 /* unknown */ 1010 ds3000_tuner_writereg(state, 0x51, 0x17); 1011 ds3000_tuner_writereg(state, 0x51, 0x1f); 1012 ds3000_tuner_writereg(state, 0x50, 0x08); 1013 ds3000_tuner_writereg(state, 0x50, 0x00); 1014 msleep(5); 1015 1016 value = ds3000_tuner_readreg(state, 0x3d); 1017 value &= 0x0f; 1018 if ((value > 4) && (value < 15)) { 1019 value -= 3; 1020 if (value < 4) 1021 value = 4; 1022 value = ((value << 3) | 0x01) & 0x79; 1023 } 1024 1025 ds3000_tuner_writereg(state, 0x60, value); 1026 ds3000_tuner_writereg(state, 0x51, 0x17); 1027 ds3000_tuner_writereg(state, 0x51, 0x1f); 1028 ds3000_tuner_writereg(state, 0x50, 0x08); 1029 ds3000_tuner_writereg(state, 0x50, 0x00); 1030 1031 /* set low-pass filter period */ 1032 ds3000_tuner_writereg(state, 0x04, 0x2e); 1033 ds3000_tuner_writereg(state, 0x51, 0x1b); 1034 ds3000_tuner_writereg(state, 0x51, 0x1f); 1035 ds3000_tuner_writereg(state, 0x50, 0x04); 1036 ds3000_tuner_writereg(state, 0x50, 0x00); 1037 msleep(5); 1038 1039 f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000; 1040 if ((c->symbol_rate / 1000) < 5000) 1041 f3db += 3000; 1042 if (f3db < 7000) 1043 f3db = 7000; 1044 if (f3db > 40000) 1045 f3db = 40000; 1046 1047 /* set low-pass filter baseband */ 1048 value = ds3000_tuner_readreg(state, 0x26); 1049 mlpf = 0x2e * 207 / ((value << 1) + 151); 1050 mlpf_max = mlpf * 135 / 100; 1051 mlpf_min = mlpf * 78 / 100; 1052 if (mlpf_max > 63) 1053 mlpf_max = 63; 1054 1055 /* rounded to the closest integer */ 1056 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2)) 1057 / (2766 * DS3000_XTAL_FREQ); 1058 if (nlpf > 23) 1059 nlpf = 23; 1060 if (nlpf < 1) 1061 nlpf = 1; 1062 1063 /* rounded to the closest integer */ 1064 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) + 1065 (1000 * f3db / 2)) / (1000 * f3db); 1066 1067 if (mlpf_new < mlpf_min) { 1068 nlpf++; 1069 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) + 1070 (1000 * f3db / 2)) / (1000 * f3db); 1071 } 1072 1073 if (mlpf_new > mlpf_max) 1074 mlpf_new = mlpf_max; 1075 1076 ds3000_tuner_writereg(state, 0x04, mlpf_new); 1077 ds3000_tuner_writereg(state, 0x06, nlpf); 1078 ds3000_tuner_writereg(state, 0x51, 0x1b); 1079 ds3000_tuner_writereg(state, 0x51, 0x1f); 1080 ds3000_tuner_writereg(state, 0x50, 0x04); 1081 ds3000_tuner_writereg(state, 0x50, 0x00); 1082 msleep(5); 1083 1084 /* unknown */ 1085 ds3000_tuner_writereg(state, 0x51, 0x1e); 1086 ds3000_tuner_writereg(state, 0x51, 0x1f); 1087 ds3000_tuner_writereg(state, 0x50, 0x01); 1088 ds3000_tuner_writereg(state, 0x50, 0x00); 1089 msleep(60); 1090 1091 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ 1092 / (6 + 8) / (div4 + 1) / 2 - c->frequency; 1093 1094 /* ds3000 global reset */ 1095 ds3000_writereg(state, 0x07, 0x80); 1096 ds3000_writereg(state, 0x07, 0x00); 1097 /* ds3000 build-in uC reset */ 1098 ds3000_writereg(state, 0xb2, 0x01); 1099 /* ds3000 software reset */ 1100 ds3000_writereg(state, 0x00, 0x01); 1101 1102 switch (c->delivery_system) { 1103 case SYS_DVBS: 1104 /* initialise the demod in DVB-S mode */ 1105 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2) 1106 ds3000_writereg(state, 1107 ds3000_dvbs_init_tab[i], 1108 ds3000_dvbs_init_tab[i + 1]); 1109 value = ds3000_readreg(state, 0xfe); 1110 value &= 0xc0; 1111 value |= 0x1b; 1112 ds3000_writereg(state, 0xfe, value); 1113 break; 1114 case SYS_DVBS2: 1115 /* initialise the demod in DVB-S2 mode */ 1116 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2) 1117 ds3000_writereg(state, 1118 ds3000_dvbs2_init_tab[i], 1119 ds3000_dvbs2_init_tab[i + 1]); 1120 if (c->symbol_rate >= 30000000) 1121 ds3000_writereg(state, 0xfe, 0x54); 1122 else 1123 ds3000_writereg(state, 0xfe, 0x98); 1124 break; 1125 default: 1126 return 1; 1127 } 1128 1129 /* enable 27MHz clock output */ 1130 ds3000_writereg(state, 0x29, 0x80); 1131 /* enable ac coupling */ 1132 ds3000_writereg(state, 0x25, 0x8a); 1133 1134 /* enhance symbol rate performance */ 1135 if ((c->symbol_rate / 1000) <= 5000) { 1136 value = 29777 / (c->symbol_rate / 1000) + 1; 1137 if (value % 2 != 0) 1138 value++; 1139 ds3000_writereg(state, 0xc3, 0x0d); 1140 ds3000_writereg(state, 0xc8, value); 1141 ds3000_writereg(state, 0xc4, 0x10); 1142 ds3000_writereg(state, 0xc7, 0x0e); 1143 } else if ((c->symbol_rate / 1000) <= 10000) { 1144 value = 92166 / (c->symbol_rate / 1000) + 1; 1145 if (value % 2 != 0) 1146 value++; 1147 ds3000_writereg(state, 0xc3, 0x07); 1148 ds3000_writereg(state, 0xc8, value); 1149 ds3000_writereg(state, 0xc4, 0x09); 1150 ds3000_writereg(state, 0xc7, 0x12); 1151 } else if ((c->symbol_rate / 1000) <= 20000) { 1152 value = 64516 / (c->symbol_rate / 1000) + 1; 1153 ds3000_writereg(state, 0xc3, value); 1154 ds3000_writereg(state, 0xc8, 0x0e); 1155 ds3000_writereg(state, 0xc4, 0x07); 1156 ds3000_writereg(state, 0xc7, 0x18); 1157 } else { 1158 value = 129032 / (c->symbol_rate / 1000) + 1; 1159 ds3000_writereg(state, 0xc3, value); 1160 ds3000_writereg(state, 0xc8, 0x0a); 1161 ds3000_writereg(state, 0xc4, 0x05); 1162 ds3000_writereg(state, 0xc7, 0x24); 1163 } 1164 1165 /* normalized symbol rate rounded to the closest integer */ 1166 value = (((c->symbol_rate / 1000) << 16) + 1167 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE; 1168 ds3000_writereg(state, 0x61, value & 0x00ff); 1169 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8); 1170 1171 /* co-channel interference cancellation disabled */ 1172 ds3000_writereg(state, 0x56, 0x00); 1173 1174 /* equalizer disabled */ 1175 ds3000_writereg(state, 0x76, 0x00); 1176 1177 /*ds3000_writereg(state, 0x08, 0x03); 1178 ds3000_writereg(state, 0xfd, 0x22); 1179 ds3000_writereg(state, 0x08, 0x07); 1180 ds3000_writereg(state, 0xfd, 0x42); 1181 ds3000_writereg(state, 0x08, 0x07);*/ 1182 1183 if (state->config->ci_mode) { 1184 switch (c->delivery_system) { 1185 case SYS_DVBS: 1186 default: 1187 ds3000_writereg(state, 0xfd, 0x80); 1188 break; 1189 case SYS_DVBS2: 1190 ds3000_writereg(state, 0xfd, 0x01); 1191 break; 1192 } 1193 } 1194 1195 /* ds3000 out of software reset */ 1196 ds3000_writereg(state, 0x00, 0x00); 1197 /* start ds3000 build-in uC */ 1198 ds3000_writereg(state, 0xb2, 0x00); 1199 1200 ds3000_set_carrier_offset(fe, offset_khz); 1201 1202 for (i = 0; i < 30 ; i++) { 1203 ds3000_read_status(fe, &status); 1204 if (status & FE_HAS_LOCK) 1205 break; 1206 1207 msleep(10); 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int ds3000_tune(struct dvb_frontend *fe, 1214 bool re_tune, 1215 unsigned int mode_flags, 1216 unsigned int *delay, 1217 fe_status_t *status) 1218 { 1219 if (re_tune) { 1220 int ret = ds3000_set_frontend(fe); 1221 if (ret) 1222 return ret; 1223 } 1224 1225 *delay = HZ / 5; 1226 1227 return ds3000_read_status(fe, status); 1228 } 1229 1230 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe) 1231 { 1232 dprintk("%s()\n", __func__); 1233 return DVBFE_ALGO_HW; 1234 } 1235 1236 /* 1237 * Initialise or wake up device 1238 * 1239 * Power config will reset and load initial firmware if required 1240 */ 1241 static int ds3000_initfe(struct dvb_frontend *fe) 1242 { 1243 struct ds3000_state *state = fe->demodulator_priv; 1244 int ret; 1245 1246 dprintk("%s()\n", __func__); 1247 /* hard reset */ 1248 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08)); 1249 msleep(1); 1250 1251 /* TS2020 init */ 1252 ds3000_tuner_writereg(state, 0x42, 0x73); 1253 ds3000_tuner_writereg(state, 0x05, 0x01); 1254 ds3000_tuner_writereg(state, 0x62, 0xf5); 1255 /* Load the firmware if required */ 1256 ret = ds3000_firmware_ondemand(fe); 1257 if (ret != 0) { 1258 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__); 1259 return ret; 1260 } 1261 1262 return 0; 1263 } 1264 1265 /* Put device to sleep */ 1266 static int ds3000_sleep(struct dvb_frontend *fe) 1267 { 1268 dprintk("%s()\n", __func__); 1269 return 0; 1270 } 1271 1272 static struct dvb_frontend_ops ds3000_ops = { 1273 .delsys = { SYS_DVBS, SYS_DVBS2}, 1274 .info = { 1275 .name = "Montage Technology DS3000/TS2020", 1276 .frequency_min = 950000, 1277 .frequency_max = 2150000, 1278 .frequency_stepsize = 1011, /* kHz for QPSK frontends */ 1279 .frequency_tolerance = 5000, 1280 .symbol_rate_min = 1000000, 1281 .symbol_rate_max = 45000000, 1282 .caps = FE_CAN_INVERSION_AUTO | 1283 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1284 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | 1285 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1286 FE_CAN_2G_MODULATION | 1287 FE_CAN_QPSK | FE_CAN_RECOVER 1288 }, 1289 1290 .release = ds3000_release, 1291 1292 .init = ds3000_initfe, 1293 .sleep = ds3000_sleep, 1294 .read_status = ds3000_read_status, 1295 .read_ber = ds3000_read_ber, 1296 .read_signal_strength = ds3000_read_signal_strength, 1297 .read_snr = ds3000_read_snr, 1298 .read_ucblocks = ds3000_read_ucblocks, 1299 .set_voltage = ds3000_set_voltage, 1300 .set_tone = ds3000_set_tone, 1301 .diseqc_send_master_cmd = ds3000_send_diseqc_msg, 1302 .diseqc_send_burst = ds3000_diseqc_send_burst, 1303 .get_frontend_algo = ds3000_get_algo, 1304 1305 .set_frontend = ds3000_set_frontend, 1306 .tune = ds3000_tune, 1307 }; 1308 1309 module_param(debug, int, 0644); 1310 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); 1311 1312 module_param(force_fw_upload, int, 0644); 1313 MODULE_PARM_DESC(force_fw_upload, "Force firmware upload (default:0)"); 1314 1315 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology " 1316 "DS3000/TS2020 hardware"); 1317 MODULE_AUTHOR("Konstantin Dimitrov"); 1318 MODULE_LICENSE("GPL"); 1319