1 /* 2 * w6692.c mISDN driver for Winbond w6692 based cards 3 * 4 * Author Karsten Keil <kkeil@suse.de> 5 * based on the w6692 I4L driver from Petr Novak <petr.novak@i.cz> 6 * 7 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 24 #include <linux/interrupt.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/delay.h> 28 #include <linux/mISDNhw.h> 29 #include <linux/slab.h> 30 #include "w6692.h" 31 32 #define W6692_REV "2.0" 33 34 #define DBUSY_TIMER_VALUE 80 35 36 enum { 37 W6692_ASUS, 38 W6692_WINBOND, 39 W6692_USR 40 }; 41 42 /* private data in the PCI devices list */ 43 struct w6692map { 44 u_int subtype; 45 char *name; 46 }; 47 48 static const struct w6692map w6692_map[] = 49 { 50 {W6692_ASUS, "Dynalink/AsusCom IS64PH"}, 51 {W6692_WINBOND, "Winbond W6692"}, 52 {W6692_USR, "USR W6692"} 53 }; 54 55 #ifndef PCI_VENDOR_ID_USR 56 #define PCI_VENDOR_ID_USR 0x16ec 57 #define PCI_DEVICE_ID_USR_6692 0x3409 58 #endif 59 60 struct w6692_ch { 61 struct bchannel bch; 62 u32 addr; 63 struct timer_list timer; 64 u8 b_mode; 65 }; 66 67 struct w6692_hw { 68 struct list_head list; 69 struct pci_dev *pdev; 70 char name[MISDN_MAX_IDLEN]; 71 u32 irq; 72 u32 irqcnt; 73 u32 addr; 74 u32 fmask; /* feature mask - bit set per card nr */ 75 int subtype; 76 spinlock_t lock; /* hw lock */ 77 u8 imask; 78 u8 pctl; 79 u8 xaddr; 80 u8 xdata; 81 u8 state; 82 struct w6692_ch bc[2]; 83 struct dchannel dch; 84 char log[64]; 85 }; 86 87 static LIST_HEAD(Cards); 88 static DEFINE_RWLOCK(card_lock); /* protect Cards */ 89 90 static int w6692_cnt; 91 static int debug; 92 static u32 led; 93 static u32 pots; 94 95 static void 96 _set_debug(struct w6692_hw *card) 97 { 98 card->dch.debug = debug; 99 card->bc[0].bch.debug = debug; 100 card->bc[1].bch.debug = debug; 101 } 102 103 static int 104 set_debug(const char *val, const struct kernel_param *kp) 105 { 106 int ret; 107 struct w6692_hw *card; 108 109 ret = param_set_uint(val, kp); 110 if (!ret) { 111 read_lock(&card_lock); 112 list_for_each_entry(card, &Cards, list) 113 _set_debug(card); 114 read_unlock(&card_lock); 115 } 116 return ret; 117 } 118 119 MODULE_AUTHOR("Karsten Keil"); 120 MODULE_LICENSE("GPL v2"); 121 MODULE_VERSION(W6692_REV); 122 module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR); 123 MODULE_PARM_DESC(debug, "W6692 debug mask"); 124 module_param(led, uint, S_IRUGO | S_IWUSR); 125 MODULE_PARM_DESC(led, "W6692 LED support bitmask (one bit per card)"); 126 module_param(pots, uint, S_IRUGO | S_IWUSR); 127 MODULE_PARM_DESC(pots, "W6692 POTS support bitmask (one bit per card)"); 128 129 static inline u8 130 ReadW6692(struct w6692_hw *card, u8 offset) 131 { 132 return inb(card->addr + offset); 133 } 134 135 static inline void 136 WriteW6692(struct w6692_hw *card, u8 offset, u8 value) 137 { 138 outb(value, card->addr + offset); 139 } 140 141 static inline u8 142 ReadW6692B(struct w6692_ch *bc, u8 offset) 143 { 144 return inb(bc->addr + offset); 145 } 146 147 static inline void 148 WriteW6692B(struct w6692_ch *bc, u8 offset, u8 value) 149 { 150 outb(value, bc->addr + offset); 151 } 152 153 static void 154 enable_hwirq(struct w6692_hw *card) 155 { 156 WriteW6692(card, W_IMASK, card->imask); 157 } 158 159 static void 160 disable_hwirq(struct w6692_hw *card) 161 { 162 WriteW6692(card, W_IMASK, 0xff); 163 } 164 165 static const char *W6692Ver[] = {"V00", "V01", "V10", "V11"}; 166 167 static void 168 W6692Version(struct w6692_hw *card) 169 { 170 int val; 171 172 val = ReadW6692(card, W_D_RBCH); 173 pr_notice("%s: Winbond W6692 version: %s\n", card->name, 174 W6692Ver[(val >> 6) & 3]); 175 } 176 177 static void 178 w6692_led_handler(struct w6692_hw *card, int on) 179 { 180 if ((!(card->fmask & led)) || card->subtype == W6692_USR) 181 return; 182 if (on) { 183 card->xdata &= 0xfb; /* LED ON */ 184 WriteW6692(card, W_XDATA, card->xdata); 185 } else { 186 card->xdata |= 0x04; /* LED OFF */ 187 WriteW6692(card, W_XDATA, card->xdata); 188 } 189 } 190 191 static void 192 ph_command(struct w6692_hw *card, u8 cmd) 193 { 194 pr_debug("%s: ph_command %x\n", card->name, cmd); 195 WriteW6692(card, W_CIX, cmd); 196 } 197 198 static void 199 W6692_new_ph(struct w6692_hw *card) 200 { 201 if (card->state == W_L1CMD_RST) 202 ph_command(card, W_L1CMD_DRC); 203 schedule_event(&card->dch, FLG_PHCHANGE); 204 } 205 206 static void 207 W6692_ph_bh(struct dchannel *dch) 208 { 209 struct w6692_hw *card = dch->hw; 210 211 switch (card->state) { 212 case W_L1CMD_RST: 213 dch->state = 0; 214 l1_event(dch->l1, HW_RESET_IND); 215 break; 216 case W_L1IND_CD: 217 dch->state = 3; 218 l1_event(dch->l1, HW_DEACT_CNF); 219 break; 220 case W_L1IND_DRD: 221 dch->state = 3; 222 l1_event(dch->l1, HW_DEACT_IND); 223 break; 224 case W_L1IND_CE: 225 dch->state = 4; 226 l1_event(dch->l1, HW_POWERUP_IND); 227 break; 228 case W_L1IND_LD: 229 if (dch->state <= 5) { 230 dch->state = 5; 231 l1_event(dch->l1, ANYSIGNAL); 232 } else { 233 dch->state = 8; 234 l1_event(dch->l1, LOSTFRAMING); 235 } 236 break; 237 case W_L1IND_ARD: 238 dch->state = 6; 239 l1_event(dch->l1, INFO2); 240 break; 241 case W_L1IND_AI8: 242 dch->state = 7; 243 l1_event(dch->l1, INFO4_P8); 244 break; 245 case W_L1IND_AI10: 246 dch->state = 7; 247 l1_event(dch->l1, INFO4_P10); 248 break; 249 default: 250 pr_debug("%s: TE unknown state %02x dch state %02x\n", 251 card->name, card->state, dch->state); 252 break; 253 } 254 pr_debug("%s: TE newstate %02x\n", card->name, dch->state); 255 } 256 257 static void 258 W6692_empty_Dfifo(struct w6692_hw *card, int count) 259 { 260 struct dchannel *dch = &card->dch; 261 u8 *ptr; 262 263 pr_debug("%s: empty_Dfifo %d\n", card->name, count); 264 if (!dch->rx_skb) { 265 dch->rx_skb = mI_alloc_skb(card->dch.maxlen, GFP_ATOMIC); 266 if (!dch->rx_skb) { 267 pr_info("%s: D receive out of memory\n", card->name); 268 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK); 269 return; 270 } 271 } 272 if ((dch->rx_skb->len + count) >= dch->maxlen) { 273 pr_debug("%s: empty_Dfifo overrun %d\n", card->name, 274 dch->rx_skb->len + count); 275 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK); 276 return; 277 } 278 ptr = skb_put(dch->rx_skb, count); 279 insb(card->addr + W_D_RFIFO, ptr, count); 280 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK); 281 if (debug & DEBUG_HW_DFIFO) { 282 snprintf(card->log, 63, "D-recv %s %d ", 283 card->name, count); 284 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count); 285 } 286 } 287 288 static void 289 W6692_fill_Dfifo(struct w6692_hw *card) 290 { 291 struct dchannel *dch = &card->dch; 292 int count; 293 u8 *ptr; 294 u8 cmd = W_D_CMDR_XMS; 295 296 pr_debug("%s: fill_Dfifo\n", card->name); 297 if (!dch->tx_skb) 298 return; 299 count = dch->tx_skb->len - dch->tx_idx; 300 if (count <= 0) 301 return; 302 if (count > W_D_FIFO_THRESH) 303 count = W_D_FIFO_THRESH; 304 else 305 cmd |= W_D_CMDR_XME; 306 ptr = dch->tx_skb->data + dch->tx_idx; 307 dch->tx_idx += count; 308 outsb(card->addr + W_D_XFIFO, ptr, count); 309 WriteW6692(card, W_D_CMDR, cmd); 310 if (test_and_set_bit(FLG_BUSY_TIMER, &dch->Flags)) { 311 pr_debug("%s: fill_Dfifo dbusytimer running\n", card->name); 312 del_timer(&dch->timer); 313 } 314 dch->timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000); 315 add_timer(&dch->timer); 316 if (debug & DEBUG_HW_DFIFO) { 317 snprintf(card->log, 63, "D-send %s %d ", 318 card->name, count); 319 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count); 320 } 321 } 322 323 static void 324 d_retransmit(struct w6692_hw *card) 325 { 326 struct dchannel *dch = &card->dch; 327 328 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 329 del_timer(&dch->timer); 330 #ifdef FIXME 331 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) 332 dchannel_sched_event(dch, D_CLEARBUSY); 333 #endif 334 if (test_bit(FLG_TX_BUSY, &dch->Flags)) { 335 /* Restart frame */ 336 dch->tx_idx = 0; 337 W6692_fill_Dfifo(card); 338 } else if (dch->tx_skb) { /* should not happen */ 339 pr_info("%s: %s without TX_BUSY\n", card->name, __func__); 340 test_and_set_bit(FLG_TX_BUSY, &dch->Flags); 341 dch->tx_idx = 0; 342 W6692_fill_Dfifo(card); 343 } else { 344 pr_info("%s: XDU no TX_BUSY\n", card->name); 345 if (get_next_dframe(dch)) 346 W6692_fill_Dfifo(card); 347 } 348 } 349 350 static void 351 handle_rxD(struct w6692_hw *card) { 352 u8 stat; 353 int count; 354 355 stat = ReadW6692(card, W_D_RSTA); 356 if (stat & (W_D_RSTA_RDOV | W_D_RSTA_CRCE | W_D_RSTA_RMB)) { 357 if (stat & W_D_RSTA_RDOV) { 358 pr_debug("%s: D-channel RDOV\n", card->name); 359 #ifdef ERROR_STATISTIC 360 card->dch.err_rx++; 361 #endif 362 } 363 if (stat & W_D_RSTA_CRCE) { 364 pr_debug("%s: D-channel CRC error\n", card->name); 365 #ifdef ERROR_STATISTIC 366 card->dch.err_crc++; 367 #endif 368 } 369 if (stat & W_D_RSTA_RMB) { 370 pr_debug("%s: D-channel ABORT\n", card->name); 371 #ifdef ERROR_STATISTIC 372 card->dch.err_rx++; 373 #endif 374 } 375 if (card->dch.rx_skb) 376 dev_kfree_skb(card->dch.rx_skb); 377 card->dch.rx_skb = NULL; 378 WriteW6692(card, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST); 379 } else { 380 count = ReadW6692(card, W_D_RBCL) & (W_D_FIFO_THRESH - 1); 381 if (count == 0) 382 count = W_D_FIFO_THRESH; 383 W6692_empty_Dfifo(card, count); 384 recv_Dchannel(&card->dch); 385 } 386 } 387 388 static void 389 handle_txD(struct w6692_hw *card) { 390 if (test_and_clear_bit(FLG_BUSY_TIMER, &card->dch.Flags)) 391 del_timer(&card->dch.timer); 392 if (card->dch.tx_skb && card->dch.tx_idx < card->dch.tx_skb->len) { 393 W6692_fill_Dfifo(card); 394 } else { 395 if (card->dch.tx_skb) 396 dev_kfree_skb(card->dch.tx_skb); 397 if (get_next_dframe(&card->dch)) 398 W6692_fill_Dfifo(card); 399 } 400 } 401 402 static void 403 handle_statusD(struct w6692_hw *card) 404 { 405 struct dchannel *dch = &card->dch; 406 u8 exval, v1, cir; 407 408 exval = ReadW6692(card, W_D_EXIR); 409 410 pr_debug("%s: D_EXIR %02x\n", card->name, exval); 411 if (exval & (W_D_EXI_XDUN | W_D_EXI_XCOL)) { 412 /* Transmit underrun/collision */ 413 pr_debug("%s: D-channel underrun/collision\n", card->name); 414 #ifdef ERROR_STATISTIC 415 dch->err_tx++; 416 #endif 417 d_retransmit(card); 418 } 419 if (exval & W_D_EXI_RDOV) { /* RDOV */ 420 pr_debug("%s: D-channel RDOV\n", card->name); 421 WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST); 422 } 423 if (exval & W_D_EXI_TIN2) /* TIN2 - never */ 424 pr_debug("%s: spurious TIN2 interrupt\n", card->name); 425 if (exval & W_D_EXI_MOC) { /* MOC - not supported */ 426 v1 = ReadW6692(card, W_MOSR); 427 pr_debug("%s: spurious MOC interrupt MOSR %02x\n", 428 card->name, v1); 429 } 430 if (exval & W_D_EXI_ISC) { /* ISC - Level1 change */ 431 cir = ReadW6692(card, W_CIR); 432 pr_debug("%s: ISC CIR %02X\n", card->name, cir); 433 if (cir & W_CIR_ICC) { 434 v1 = cir & W_CIR_COD_MASK; 435 pr_debug("%s: ph_state_change %x -> %x\n", card->name, 436 dch->state, v1); 437 card->state = v1; 438 if (card->fmask & led) { 439 switch (v1) { 440 case W_L1IND_AI8: 441 case W_L1IND_AI10: 442 w6692_led_handler(card, 1); 443 break; 444 default: 445 w6692_led_handler(card, 0); 446 break; 447 } 448 } 449 W6692_new_ph(card); 450 } 451 if (cir & W_CIR_SCC) { 452 v1 = ReadW6692(card, W_SQR); 453 pr_debug("%s: SCC SQR %02X\n", card->name, v1); 454 } 455 } 456 if (exval & W_D_EXI_WEXP) 457 pr_debug("%s: spurious WEXP interrupt!\n", card->name); 458 if (exval & W_D_EXI_TEXP) 459 pr_debug("%s: spurious TEXP interrupt!\n", card->name); 460 } 461 462 static void 463 W6692_empty_Bfifo(struct w6692_ch *wch, int count) 464 { 465 struct w6692_hw *card = wch->bch.hw; 466 u8 *ptr; 467 int maxlen; 468 469 pr_debug("%s: empty_Bfifo %d\n", card->name, count); 470 if (unlikely(wch->bch.state == ISDN_P_NONE)) { 471 pr_debug("%s: empty_Bfifo ISDN_P_NONE\n", card->name); 472 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); 473 if (wch->bch.rx_skb) 474 skb_trim(wch->bch.rx_skb, 0); 475 return; 476 } 477 if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) { 478 wch->bch.dropcnt += count; 479 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); 480 return; 481 } 482 maxlen = bchannel_get_rxbuf(&wch->bch, count); 483 if (maxlen < 0) { 484 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); 485 if (wch->bch.rx_skb) 486 skb_trim(wch->bch.rx_skb, 0); 487 pr_warning("%s.B%d: No bufferspace for %d bytes\n", 488 card->name, wch->bch.nr, count); 489 return; 490 } 491 ptr = skb_put(wch->bch.rx_skb, count); 492 insb(wch->addr + W_B_RFIFO, ptr, count); 493 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); 494 if (debug & DEBUG_HW_DFIFO) { 495 snprintf(card->log, 63, "B%1d-recv %s %d ", 496 wch->bch.nr, card->name, count); 497 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count); 498 } 499 } 500 501 static void 502 W6692_fill_Bfifo(struct w6692_ch *wch) 503 { 504 struct w6692_hw *card = wch->bch.hw; 505 int count, fillempty = 0; 506 u8 *ptr, cmd = W_B_CMDR_RACT | W_B_CMDR_XMS; 507 508 pr_debug("%s: fill Bfifo\n", card->name); 509 if (!wch->bch.tx_skb) { 510 if (!test_bit(FLG_TX_EMPTY, &wch->bch.Flags)) 511 return; 512 ptr = wch->bch.fill; 513 count = W_B_FIFO_THRESH; 514 fillempty = 1; 515 } else { 516 count = wch->bch.tx_skb->len - wch->bch.tx_idx; 517 if (count <= 0) 518 return; 519 ptr = wch->bch.tx_skb->data + wch->bch.tx_idx; 520 } 521 if (count > W_B_FIFO_THRESH) 522 count = W_B_FIFO_THRESH; 523 else if (test_bit(FLG_HDLC, &wch->bch.Flags)) 524 cmd |= W_B_CMDR_XME; 525 526 pr_debug("%s: fill Bfifo%d/%d\n", card->name, 527 count, wch->bch.tx_idx); 528 wch->bch.tx_idx += count; 529 if (fillempty) { 530 while (count > 0) { 531 outsb(wch->addr + W_B_XFIFO, ptr, MISDN_BCH_FILL_SIZE); 532 count -= MISDN_BCH_FILL_SIZE; 533 } 534 } else { 535 outsb(wch->addr + W_B_XFIFO, ptr, count); 536 } 537 WriteW6692B(wch, W_B_CMDR, cmd); 538 if ((debug & DEBUG_HW_BFIFO) && !fillempty) { 539 snprintf(card->log, 63, "B%1d-send %s %d ", 540 wch->bch.nr, card->name, count); 541 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, ptr, count); 542 } 543 } 544 545 #if 0 546 static int 547 setvolume(struct w6692_ch *wch, int mic, struct sk_buff *skb) 548 { 549 struct w6692_hw *card = wch->bch.hw; 550 u16 *vol = (u16 *)skb->data; 551 u8 val; 552 553 if ((!(card->fmask & pots)) || 554 !test_bit(FLG_TRANSPARENT, &wch->bch.Flags)) 555 return -ENODEV; 556 if (skb->len < 2) 557 return -EINVAL; 558 if (*vol > 7) 559 return -EINVAL; 560 val = *vol & 7; 561 val = 7 - val; 562 if (mic) { 563 val <<= 3; 564 card->xaddr &= 0xc7; 565 } else { 566 card->xaddr &= 0xf8; 567 } 568 card->xaddr |= val; 569 WriteW6692(card, W_XADDR, card->xaddr); 570 return 0; 571 } 572 573 static int 574 enable_pots(struct w6692_ch *wch) 575 { 576 struct w6692_hw *card = wch->bch.hw; 577 578 if ((!(card->fmask & pots)) || 579 !test_bit(FLG_TRANSPARENT, &wch->bch.Flags)) 580 return -ENODEV; 581 wch->b_mode |= W_B_MODE_EPCM | W_B_MODE_BSW0; 582 WriteW6692B(wch, W_B_MODE, wch->b_mode); 583 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST); 584 card->pctl |= ((wch->bch.nr & 2) ? W_PCTL_PCX : 0); 585 WriteW6692(card, W_PCTL, card->pctl); 586 return 0; 587 } 588 #endif 589 590 static int 591 disable_pots(struct w6692_ch *wch) 592 { 593 struct w6692_hw *card = wch->bch.hw; 594 595 if (!(card->fmask & pots)) 596 return -ENODEV; 597 wch->b_mode &= ~(W_B_MODE_EPCM | W_B_MODE_BSW0); 598 WriteW6692B(wch, W_B_MODE, wch->b_mode); 599 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT | 600 W_B_CMDR_XRST); 601 return 0; 602 } 603 604 static int 605 w6692_mode(struct w6692_ch *wch, u32 pr) 606 { 607 struct w6692_hw *card; 608 609 card = wch->bch.hw; 610 pr_debug("%s: B%d protocol %x-->%x\n", card->name, 611 wch->bch.nr, wch->bch.state, pr); 612 switch (pr) { 613 case ISDN_P_NONE: 614 if ((card->fmask & pots) && (wch->b_mode & W_B_MODE_EPCM)) 615 disable_pots(wch); 616 wch->b_mode = 0; 617 mISDN_clear_bchannel(&wch->bch); 618 WriteW6692B(wch, W_B_MODE, wch->b_mode); 619 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST); 620 test_and_clear_bit(FLG_HDLC, &wch->bch.Flags); 621 test_and_clear_bit(FLG_TRANSPARENT, &wch->bch.Flags); 622 break; 623 case ISDN_P_B_RAW: 624 wch->b_mode = W_B_MODE_MMS; 625 WriteW6692B(wch, W_B_MODE, wch->b_mode); 626 WriteW6692B(wch, W_B_EXIM, 0); 627 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT | 628 W_B_CMDR_XRST); 629 test_and_set_bit(FLG_TRANSPARENT, &wch->bch.Flags); 630 break; 631 case ISDN_P_B_HDLC: 632 wch->b_mode = W_B_MODE_ITF; 633 WriteW6692B(wch, W_B_MODE, wch->b_mode); 634 WriteW6692B(wch, W_B_ADM1, 0xff); 635 WriteW6692B(wch, W_B_ADM2, 0xff); 636 WriteW6692B(wch, W_B_EXIM, 0); 637 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_RACT | 638 W_B_CMDR_XRST); 639 test_and_set_bit(FLG_HDLC, &wch->bch.Flags); 640 break; 641 default: 642 pr_info("%s: protocol %x not known\n", card->name, pr); 643 return -ENOPROTOOPT; 644 } 645 wch->bch.state = pr; 646 return 0; 647 } 648 649 static void 650 send_next(struct w6692_ch *wch) 651 { 652 if (wch->bch.tx_skb && wch->bch.tx_idx < wch->bch.tx_skb->len) { 653 W6692_fill_Bfifo(wch); 654 } else { 655 if (wch->bch.tx_skb) 656 dev_kfree_skb(wch->bch.tx_skb); 657 if (get_next_bframe(&wch->bch)) { 658 W6692_fill_Bfifo(wch); 659 test_and_clear_bit(FLG_TX_EMPTY, &wch->bch.Flags); 660 } else if (test_bit(FLG_TX_EMPTY, &wch->bch.Flags)) { 661 W6692_fill_Bfifo(wch); 662 } 663 } 664 } 665 666 static void 667 W6692B_interrupt(struct w6692_hw *card, int ch) 668 { 669 struct w6692_ch *wch = &card->bc[ch]; 670 int count; 671 u8 stat, star = 0; 672 673 stat = ReadW6692B(wch, W_B_EXIR); 674 pr_debug("%s: B%d EXIR %02x\n", card->name, wch->bch.nr, stat); 675 if (stat & W_B_EXI_RME) { 676 star = ReadW6692B(wch, W_B_STAR); 677 if (star & (W_B_STAR_RDOV | W_B_STAR_CRCE | W_B_STAR_RMB)) { 678 if ((star & W_B_STAR_RDOV) && 679 test_bit(FLG_ACTIVE, &wch->bch.Flags)) { 680 pr_debug("%s: B%d RDOV proto=%x\n", card->name, 681 wch->bch.nr, wch->bch.state); 682 #ifdef ERROR_STATISTIC 683 wch->bch.err_rdo++; 684 #endif 685 } 686 if (test_bit(FLG_HDLC, &wch->bch.Flags)) { 687 if (star & W_B_STAR_CRCE) { 688 pr_debug("%s: B%d CRC error\n", 689 card->name, wch->bch.nr); 690 #ifdef ERROR_STATISTIC 691 wch->bch.err_crc++; 692 #endif 693 } 694 if (star & W_B_STAR_RMB) { 695 pr_debug("%s: B%d message abort\n", 696 card->name, wch->bch.nr); 697 #ifdef ERROR_STATISTIC 698 wch->bch.err_inv++; 699 #endif 700 } 701 } 702 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | 703 W_B_CMDR_RRST | W_B_CMDR_RACT); 704 if (wch->bch.rx_skb) 705 skb_trim(wch->bch.rx_skb, 0); 706 } else { 707 count = ReadW6692B(wch, W_B_RBCL) & 708 (W_B_FIFO_THRESH - 1); 709 if (count == 0) 710 count = W_B_FIFO_THRESH; 711 W6692_empty_Bfifo(wch, count); 712 recv_Bchannel(&wch->bch, 0, false); 713 } 714 } 715 if (stat & W_B_EXI_RMR) { 716 if (!(stat & W_B_EXI_RME)) 717 star = ReadW6692B(wch, W_B_STAR); 718 if (star & W_B_STAR_RDOV) { 719 pr_debug("%s: B%d RDOV proto=%x\n", card->name, 720 wch->bch.nr, wch->bch.state); 721 #ifdef ERROR_STATISTIC 722 wch->bch.err_rdo++; 723 #endif 724 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | 725 W_B_CMDR_RRST | W_B_CMDR_RACT); 726 } else { 727 W6692_empty_Bfifo(wch, W_B_FIFO_THRESH); 728 if (test_bit(FLG_TRANSPARENT, &wch->bch.Flags)) 729 recv_Bchannel(&wch->bch, 0, false); 730 } 731 } 732 if (stat & W_B_EXI_RDOV) { 733 /* only if it is not handled yet */ 734 if (!(star & W_B_STAR_RDOV)) { 735 pr_debug("%s: B%d RDOV IRQ proto=%x\n", card->name, 736 wch->bch.nr, wch->bch.state); 737 #ifdef ERROR_STATISTIC 738 wch->bch.err_rdo++; 739 #endif 740 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_RACK | 741 W_B_CMDR_RRST | W_B_CMDR_RACT); 742 } 743 } 744 if (stat & W_B_EXI_XFR) { 745 if (!(stat & (W_B_EXI_RME | W_B_EXI_RMR))) { 746 star = ReadW6692B(wch, W_B_STAR); 747 pr_debug("%s: B%d star %02x\n", card->name, 748 wch->bch.nr, star); 749 } 750 if (star & W_B_STAR_XDOW) { 751 pr_warning("%s: B%d XDOW proto=%x\n", card->name, 752 wch->bch.nr, wch->bch.state); 753 #ifdef ERROR_STATISTIC 754 wch->bch.err_xdu++; 755 #endif 756 WriteW6692B(wch, W_B_CMDR, W_B_CMDR_XRST | 757 W_B_CMDR_RACT); 758 /* resend */ 759 if (wch->bch.tx_skb) { 760 if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags)) 761 wch->bch.tx_idx = 0; 762 } 763 } 764 send_next(wch); 765 if (star & W_B_STAR_XDOW) 766 return; /* handle XDOW only once */ 767 } 768 if (stat & W_B_EXI_XDUN) { 769 pr_warning("%s: B%d XDUN proto=%x\n", card->name, 770 wch->bch.nr, wch->bch.state); 771 #ifdef ERROR_STATISTIC 772 wch->bch.err_xdu++; 773 #endif 774 /* resend - no XRST needed */ 775 if (wch->bch.tx_skb) { 776 if (!test_bit(FLG_TRANSPARENT, &wch->bch.Flags)) 777 wch->bch.tx_idx = 0; 778 } else if (test_bit(FLG_FILLEMPTY, &wch->bch.Flags)) { 779 test_and_set_bit(FLG_TX_EMPTY, &wch->bch.Flags); 780 } 781 send_next(wch); 782 } 783 } 784 785 static irqreturn_t 786 w6692_irq(int intno, void *dev_id) 787 { 788 struct w6692_hw *card = dev_id; 789 u8 ista; 790 791 spin_lock(&card->lock); 792 ista = ReadW6692(card, W_ISTA); 793 if ((ista | card->imask) == card->imask) { 794 /* possible a shared IRQ reqest */ 795 spin_unlock(&card->lock); 796 return IRQ_NONE; 797 } 798 card->irqcnt++; 799 pr_debug("%s: ista %02x\n", card->name, ista); 800 ista &= ~card->imask; 801 if (ista & W_INT_B1_EXI) 802 W6692B_interrupt(card, 0); 803 if (ista & W_INT_B2_EXI) 804 W6692B_interrupt(card, 1); 805 if (ista & W_INT_D_RME) 806 handle_rxD(card); 807 if (ista & W_INT_D_RMR) 808 W6692_empty_Dfifo(card, W_D_FIFO_THRESH); 809 if (ista & W_INT_D_XFR) 810 handle_txD(card); 811 if (ista & W_INT_D_EXI) 812 handle_statusD(card); 813 if (ista & (W_INT_XINT0 | W_INT_XINT1)) /* XINT0/1 - never */ 814 pr_debug("%s: W6692 spurious XINT!\n", card->name); 815 /* End IRQ Handler */ 816 spin_unlock(&card->lock); 817 return IRQ_HANDLED; 818 } 819 820 static void 821 dbusy_timer_handler(struct timer_list *t) 822 { 823 struct dchannel *dch = from_timer(dch, t, timer); 824 struct w6692_hw *card = dch->hw; 825 int rbch, star; 826 u_long flags; 827 828 if (test_bit(FLG_BUSY_TIMER, &dch->Flags)) { 829 spin_lock_irqsave(&card->lock, flags); 830 rbch = ReadW6692(card, W_D_RBCH); 831 star = ReadW6692(card, W_D_STAR); 832 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n", 833 card->name, rbch, star); 834 if (star & W_D_STAR_XBZ) /* D-Channel Busy */ 835 test_and_set_bit(FLG_L1_BUSY, &dch->Flags); 836 else { 837 /* discard frame; reset transceiver */ 838 test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags); 839 if (dch->tx_idx) 840 dch->tx_idx = 0; 841 else 842 pr_info("%s: W6692 D-Channel Busy no tx_idx\n", 843 card->name); 844 /* Transmitter reset */ 845 WriteW6692(card, W_D_CMDR, W_D_CMDR_XRST); 846 } 847 spin_unlock_irqrestore(&card->lock, flags); 848 } 849 } 850 851 static void initW6692(struct w6692_hw *card) 852 { 853 u8 val; 854 855 timer_setup(&card->dch.timer, dbusy_timer_handler, 0); 856 w6692_mode(&card->bc[0], ISDN_P_NONE); 857 w6692_mode(&card->bc[1], ISDN_P_NONE); 858 WriteW6692(card, W_D_CTL, 0x00); 859 disable_hwirq(card); 860 WriteW6692(card, W_D_SAM, 0xff); 861 WriteW6692(card, W_D_TAM, 0xff); 862 WriteW6692(card, W_D_MODE, W_D_MODE_RACT); 863 card->state = W_L1CMD_RST; 864 ph_command(card, W_L1CMD_RST); 865 ph_command(card, W_L1CMD_ECK); 866 /* enable all IRQ but extern */ 867 card->imask = 0x18; 868 WriteW6692(card, W_D_EXIM, 0x00); 869 WriteW6692B(&card->bc[0], W_B_EXIM, 0); 870 WriteW6692B(&card->bc[1], W_B_EXIM, 0); 871 /* Reset D-chan receiver and transmitter */ 872 WriteW6692(card, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST); 873 /* Reset B-chan receiver and transmitter */ 874 WriteW6692B(&card->bc[0], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST); 875 WriteW6692B(&card->bc[1], W_B_CMDR, W_B_CMDR_RRST | W_B_CMDR_XRST); 876 /* enable peripheral */ 877 if (card->subtype == W6692_USR) { 878 /* seems that USR implemented some power control features 879 * Pin 79 is connected to the oscilator circuit so we 880 * have to handle it here 881 */ 882 card->pctl = 0x80; 883 card->xdata = 0; 884 WriteW6692(card, W_PCTL, card->pctl); 885 WriteW6692(card, W_XDATA, card->xdata); 886 } else { 887 card->pctl = W_PCTL_OE5 | W_PCTL_OE4 | W_PCTL_OE2 | 888 W_PCTL_OE1 | W_PCTL_OE0; 889 card->xaddr = 0x00;/* all sw off */ 890 if (card->fmask & pots) 891 card->xdata |= 0x06; /* POWER UP/ LED OFF / ALAW */ 892 if (card->fmask & led) 893 card->xdata |= 0x04; /* LED OFF */ 894 if ((card->fmask & pots) || (card->fmask & led)) { 895 WriteW6692(card, W_PCTL, card->pctl); 896 WriteW6692(card, W_XADDR, card->xaddr); 897 WriteW6692(card, W_XDATA, card->xdata); 898 val = ReadW6692(card, W_XADDR); 899 if (debug & DEBUG_HW) 900 pr_notice("%s: W_XADDR=%02x\n", 901 card->name, val); 902 } 903 } 904 } 905 906 static void 907 reset_w6692(struct w6692_hw *card) 908 { 909 WriteW6692(card, W_D_CTL, W_D_CTL_SRST); 910 mdelay(10); 911 WriteW6692(card, W_D_CTL, 0); 912 } 913 914 static int 915 init_card(struct w6692_hw *card) 916 { 917 int cnt = 3; 918 u_long flags; 919 920 spin_lock_irqsave(&card->lock, flags); 921 disable_hwirq(card); 922 spin_unlock_irqrestore(&card->lock, flags); 923 if (request_irq(card->irq, w6692_irq, IRQF_SHARED, card->name, card)) { 924 pr_info("%s: couldn't get interrupt %d\n", card->name, 925 card->irq); 926 return -EIO; 927 } 928 while (cnt--) { 929 spin_lock_irqsave(&card->lock, flags); 930 initW6692(card); 931 enable_hwirq(card); 932 spin_unlock_irqrestore(&card->lock, flags); 933 /* Timeout 10ms */ 934 msleep_interruptible(10); 935 if (debug & DEBUG_HW) 936 pr_notice("%s: IRQ %d count %d\n", card->name, 937 card->irq, card->irqcnt); 938 if (!card->irqcnt) { 939 pr_info("%s: IRQ(%d) getting no IRQs during init %d\n", 940 card->name, card->irq, 3 - cnt); 941 reset_w6692(card); 942 } else 943 return 0; 944 } 945 free_irq(card->irq, card); 946 return -EIO; 947 } 948 949 static int 950 w6692_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb) 951 { 952 struct bchannel *bch = container_of(ch, struct bchannel, ch); 953 struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch); 954 struct w6692_hw *card = bch->hw; 955 int ret = -EINVAL; 956 struct mISDNhead *hh = mISDN_HEAD_P(skb); 957 unsigned long flags; 958 959 switch (hh->prim) { 960 case PH_DATA_REQ: 961 spin_lock_irqsave(&card->lock, flags); 962 ret = bchannel_senddata(bch, skb); 963 if (ret > 0) { /* direct TX */ 964 ret = 0; 965 W6692_fill_Bfifo(bc); 966 } 967 spin_unlock_irqrestore(&card->lock, flags); 968 return ret; 969 case PH_ACTIVATE_REQ: 970 spin_lock_irqsave(&card->lock, flags); 971 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) 972 ret = w6692_mode(bc, ch->protocol); 973 else 974 ret = 0; 975 spin_unlock_irqrestore(&card->lock, flags); 976 if (!ret) 977 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, 978 NULL, GFP_KERNEL); 979 break; 980 case PH_DEACTIVATE_REQ: 981 spin_lock_irqsave(&card->lock, flags); 982 mISDN_clear_bchannel(bch); 983 w6692_mode(bc, ISDN_P_NONE); 984 spin_unlock_irqrestore(&card->lock, flags); 985 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, 986 NULL, GFP_KERNEL); 987 ret = 0; 988 break; 989 default: 990 pr_info("%s: %s unknown prim(%x,%x)\n", 991 card->name, __func__, hh->prim, hh->id); 992 ret = -EINVAL; 993 } 994 if (!ret) 995 dev_kfree_skb(skb); 996 return ret; 997 } 998 999 static int 1000 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) 1001 { 1002 return mISDN_ctrl_bchannel(bch, cq); 1003 } 1004 1005 static int 1006 open_bchannel(struct w6692_hw *card, struct channel_req *rq) 1007 { 1008 struct bchannel *bch; 1009 1010 if (rq->adr.channel == 0 || rq->adr.channel > 2) 1011 return -EINVAL; 1012 if (rq->protocol == ISDN_P_NONE) 1013 return -EINVAL; 1014 bch = &card->bc[rq->adr.channel - 1].bch; 1015 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) 1016 return -EBUSY; /* b-channel can be only open once */ 1017 bch->ch.protocol = rq->protocol; 1018 rq->ch = &bch->ch; 1019 return 0; 1020 } 1021 1022 static int 1023 channel_ctrl(struct w6692_hw *card, struct mISDN_ctrl_req *cq) 1024 { 1025 int ret = 0; 1026 1027 switch (cq->op) { 1028 case MISDN_CTRL_GETOP: 1029 cq->op = MISDN_CTRL_L1_TIMER3; 1030 break; 1031 case MISDN_CTRL_L1_TIMER3: 1032 ret = l1_event(card->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff)); 1033 break; 1034 default: 1035 pr_info("%s: unknown CTRL OP %x\n", card->name, cq->op); 1036 ret = -EINVAL; 1037 break; 1038 } 1039 return ret; 1040 } 1041 1042 static int 1043 w6692_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 1044 { 1045 struct bchannel *bch = container_of(ch, struct bchannel, ch); 1046 struct w6692_ch *bc = container_of(bch, struct w6692_ch, bch); 1047 struct w6692_hw *card = bch->hw; 1048 int ret = -EINVAL; 1049 u_long flags; 1050 1051 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg); 1052 switch (cmd) { 1053 case CLOSE_CHANNEL: 1054 test_and_clear_bit(FLG_OPEN, &bch->Flags); 1055 cancel_work_sync(&bch->workq); 1056 spin_lock_irqsave(&card->lock, flags); 1057 mISDN_clear_bchannel(bch); 1058 w6692_mode(bc, ISDN_P_NONE); 1059 spin_unlock_irqrestore(&card->lock, flags); 1060 ch->protocol = ISDN_P_NONE; 1061 ch->peer = NULL; 1062 module_put(THIS_MODULE); 1063 ret = 0; 1064 break; 1065 case CONTROL_CHANNEL: 1066 ret = channel_bctrl(bch, arg); 1067 break; 1068 default: 1069 pr_info("%s: %s unknown prim(%x)\n", 1070 card->name, __func__, cmd); 1071 } 1072 return ret; 1073 } 1074 1075 static int 1076 w6692_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb) 1077 { 1078 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 1079 struct dchannel *dch = container_of(dev, struct dchannel, dev); 1080 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch); 1081 int ret = -EINVAL; 1082 struct mISDNhead *hh = mISDN_HEAD_P(skb); 1083 u32 id; 1084 u_long flags; 1085 1086 switch (hh->prim) { 1087 case PH_DATA_REQ: 1088 spin_lock_irqsave(&card->lock, flags); 1089 ret = dchannel_senddata(dch, skb); 1090 if (ret > 0) { /* direct TX */ 1091 id = hh->id; /* skb can be freed */ 1092 W6692_fill_Dfifo(card); 1093 ret = 0; 1094 spin_unlock_irqrestore(&card->lock, flags); 1095 queue_ch_frame(ch, PH_DATA_CNF, id, NULL); 1096 } else 1097 spin_unlock_irqrestore(&card->lock, flags); 1098 return ret; 1099 case PH_ACTIVATE_REQ: 1100 ret = l1_event(dch->l1, hh->prim); 1101 break; 1102 case PH_DEACTIVATE_REQ: 1103 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); 1104 ret = l1_event(dch->l1, hh->prim); 1105 break; 1106 } 1107 1108 if (!ret) 1109 dev_kfree_skb(skb); 1110 return ret; 1111 } 1112 1113 static int 1114 w6692_l1callback(struct dchannel *dch, u32 cmd) 1115 { 1116 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch); 1117 u_long flags; 1118 1119 pr_debug("%s: cmd(%x) state(%02x)\n", card->name, cmd, card->state); 1120 switch (cmd) { 1121 case INFO3_P8: 1122 spin_lock_irqsave(&card->lock, flags); 1123 ph_command(card, W_L1CMD_AR8); 1124 spin_unlock_irqrestore(&card->lock, flags); 1125 break; 1126 case INFO3_P10: 1127 spin_lock_irqsave(&card->lock, flags); 1128 ph_command(card, W_L1CMD_AR10); 1129 spin_unlock_irqrestore(&card->lock, flags); 1130 break; 1131 case HW_RESET_REQ: 1132 spin_lock_irqsave(&card->lock, flags); 1133 if (card->state != W_L1IND_DRD) 1134 ph_command(card, W_L1CMD_RST); 1135 ph_command(card, W_L1CMD_ECK); 1136 spin_unlock_irqrestore(&card->lock, flags); 1137 break; 1138 case HW_DEACT_REQ: 1139 skb_queue_purge(&dch->squeue); 1140 if (dch->tx_skb) { 1141 dev_kfree_skb(dch->tx_skb); 1142 dch->tx_skb = NULL; 1143 } 1144 dch->tx_idx = 0; 1145 if (dch->rx_skb) { 1146 dev_kfree_skb(dch->rx_skb); 1147 dch->rx_skb = NULL; 1148 } 1149 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); 1150 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) 1151 del_timer(&dch->timer); 1152 break; 1153 case HW_POWERUP_REQ: 1154 spin_lock_irqsave(&card->lock, flags); 1155 ph_command(card, W_L1CMD_ECK); 1156 spin_unlock_irqrestore(&card->lock, flags); 1157 break; 1158 case PH_ACTIVATE_IND: 1159 test_and_set_bit(FLG_ACTIVE, &dch->Flags); 1160 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 1161 GFP_ATOMIC); 1162 break; 1163 case PH_DEACTIVATE_IND: 1164 test_and_clear_bit(FLG_ACTIVE, &dch->Flags); 1165 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, 1166 GFP_ATOMIC); 1167 break; 1168 default: 1169 pr_debug("%s: %s unknown command %x\n", card->name, 1170 __func__, cmd); 1171 return -1; 1172 } 1173 return 0; 1174 } 1175 1176 static int 1177 open_dchannel(struct w6692_hw *card, struct channel_req *rq, void *caller) 1178 { 1179 pr_debug("%s: %s dev(%d) open from %p\n", card->name, __func__, 1180 card->dch.dev.id, caller); 1181 if (rq->protocol != ISDN_P_TE_S0) 1182 return -EINVAL; 1183 if (rq->adr.channel == 1) 1184 /* E-Channel not supported */ 1185 return -EINVAL; 1186 rq->ch = &card->dch.dev.D; 1187 rq->ch->protocol = rq->protocol; 1188 if (card->dch.state == 7) 1189 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 1190 0, NULL, GFP_KERNEL); 1191 return 0; 1192 } 1193 1194 static int 1195 w6692_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg) 1196 { 1197 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); 1198 struct dchannel *dch = container_of(dev, struct dchannel, dev); 1199 struct w6692_hw *card = container_of(dch, struct w6692_hw, dch); 1200 struct channel_req *rq; 1201 int err = 0; 1202 1203 pr_debug("%s: DCTRL: %x %p\n", card->name, cmd, arg); 1204 switch (cmd) { 1205 case OPEN_CHANNEL: 1206 rq = arg; 1207 if (rq->protocol == ISDN_P_TE_S0) 1208 err = open_dchannel(card, rq, __builtin_return_address(0)); 1209 else 1210 err = open_bchannel(card, rq); 1211 if (err) 1212 break; 1213 if (!try_module_get(THIS_MODULE)) 1214 pr_info("%s: cannot get module\n", card->name); 1215 break; 1216 case CLOSE_CHANNEL: 1217 pr_debug("%s: dev(%d) close from %p\n", card->name, 1218 dch->dev.id, __builtin_return_address(0)); 1219 module_put(THIS_MODULE); 1220 break; 1221 case CONTROL_CHANNEL: 1222 err = channel_ctrl(card, arg); 1223 break; 1224 default: 1225 pr_debug("%s: unknown DCTRL command %x\n", card->name, cmd); 1226 return -EINVAL; 1227 } 1228 return err; 1229 } 1230 1231 static int 1232 setup_w6692(struct w6692_hw *card) 1233 { 1234 u32 val; 1235 1236 if (!request_region(card->addr, 256, card->name)) { 1237 pr_info("%s: config port %x-%x already in use\n", card->name, 1238 card->addr, card->addr + 255); 1239 return -EIO; 1240 } 1241 W6692Version(card); 1242 card->bc[0].addr = card->addr; 1243 card->bc[1].addr = card->addr + 0x40; 1244 val = ReadW6692(card, W_ISTA); 1245 if (debug & DEBUG_HW) 1246 pr_notice("%s ISTA=%02x\n", card->name, val); 1247 val = ReadW6692(card, W_IMASK); 1248 if (debug & DEBUG_HW) 1249 pr_notice("%s IMASK=%02x\n", card->name, val); 1250 val = ReadW6692(card, W_D_EXIR); 1251 if (debug & DEBUG_HW) 1252 pr_notice("%s D_EXIR=%02x\n", card->name, val); 1253 val = ReadW6692(card, W_D_EXIM); 1254 if (debug & DEBUG_HW) 1255 pr_notice("%s D_EXIM=%02x\n", card->name, val); 1256 val = ReadW6692(card, W_D_RSTA); 1257 if (debug & DEBUG_HW) 1258 pr_notice("%s D_RSTA=%02x\n", card->name, val); 1259 return 0; 1260 } 1261 1262 static void 1263 release_card(struct w6692_hw *card) 1264 { 1265 u_long flags; 1266 1267 spin_lock_irqsave(&card->lock, flags); 1268 disable_hwirq(card); 1269 w6692_mode(&card->bc[0], ISDN_P_NONE); 1270 w6692_mode(&card->bc[1], ISDN_P_NONE); 1271 if ((card->fmask & led) || card->subtype == W6692_USR) { 1272 card->xdata |= 0x04; /* LED OFF */ 1273 WriteW6692(card, W_XDATA, card->xdata); 1274 } 1275 spin_unlock_irqrestore(&card->lock, flags); 1276 free_irq(card->irq, card); 1277 l1_event(card->dch.l1, CLOSE_CHANNEL); 1278 mISDN_unregister_device(&card->dch.dev); 1279 release_region(card->addr, 256); 1280 mISDN_freebchannel(&card->bc[1].bch); 1281 mISDN_freebchannel(&card->bc[0].bch); 1282 mISDN_freedchannel(&card->dch); 1283 write_lock_irqsave(&card_lock, flags); 1284 list_del(&card->list); 1285 write_unlock_irqrestore(&card_lock, flags); 1286 pci_disable_device(card->pdev); 1287 pci_set_drvdata(card->pdev, NULL); 1288 kfree(card); 1289 } 1290 1291 static int 1292 setup_instance(struct w6692_hw *card) 1293 { 1294 int i, err; 1295 u_long flags; 1296 1297 snprintf(card->name, MISDN_MAX_IDLEN - 1, "w6692.%d", w6692_cnt + 1); 1298 write_lock_irqsave(&card_lock, flags); 1299 list_add_tail(&card->list, &Cards); 1300 write_unlock_irqrestore(&card_lock, flags); 1301 card->fmask = (1 << w6692_cnt); 1302 _set_debug(card); 1303 spin_lock_init(&card->lock); 1304 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, W6692_ph_bh); 1305 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0); 1306 card->dch.dev.D.send = w6692_l2l1D; 1307 card->dch.dev.D.ctrl = w6692_dctrl; 1308 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | 1309 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); 1310 card->dch.hw = card; 1311 card->dch.dev.nrbchan = 2; 1312 for (i = 0; i < 2; i++) { 1313 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM, 1314 W_B_FIFO_THRESH); 1315 card->bc[i].bch.hw = card; 1316 card->bc[i].bch.nr = i + 1; 1317 card->bc[i].bch.ch.nr = i + 1; 1318 card->bc[i].bch.ch.send = w6692_l2l1B; 1319 card->bc[i].bch.ch.ctrl = w6692_bctrl; 1320 set_channelmap(i + 1, card->dch.dev.channelmap); 1321 list_add(&card->bc[i].bch.ch.list, &card->dch.dev.bchannels); 1322 } 1323 err = setup_w6692(card); 1324 if (err) 1325 goto error_setup; 1326 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, 1327 card->name); 1328 if (err) 1329 goto error_reg; 1330 err = init_card(card); 1331 if (err) 1332 goto error_init; 1333 err = create_l1(&card->dch, w6692_l1callback); 1334 if (!err) { 1335 w6692_cnt++; 1336 pr_notice("W6692 %d cards installed\n", w6692_cnt); 1337 return 0; 1338 } 1339 1340 free_irq(card->irq, card); 1341 error_init: 1342 mISDN_unregister_device(&card->dch.dev); 1343 error_reg: 1344 release_region(card->addr, 256); 1345 error_setup: 1346 mISDN_freebchannel(&card->bc[1].bch); 1347 mISDN_freebchannel(&card->bc[0].bch); 1348 mISDN_freedchannel(&card->dch); 1349 write_lock_irqsave(&card_lock, flags); 1350 list_del(&card->list); 1351 write_unlock_irqrestore(&card_lock, flags); 1352 kfree(card); 1353 return err; 1354 } 1355 1356 static int 1357 w6692_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1358 { 1359 int err = -ENOMEM; 1360 struct w6692_hw *card; 1361 struct w6692map *m = (struct w6692map *)ent->driver_data; 1362 1363 card = kzalloc(sizeof(struct w6692_hw), GFP_KERNEL); 1364 if (!card) { 1365 pr_info("No kmem for w6692 card\n"); 1366 return err; 1367 } 1368 card->pdev = pdev; 1369 card->subtype = m->subtype; 1370 err = pci_enable_device(pdev); 1371 if (err) { 1372 kfree(card); 1373 return err; 1374 } 1375 1376 printk(KERN_INFO "mISDN_w6692: found adapter %s at %s\n", 1377 m->name, pci_name(pdev)); 1378 1379 card->addr = pci_resource_start(pdev, 1); 1380 card->irq = pdev->irq; 1381 pci_set_drvdata(pdev, card); 1382 err = setup_instance(card); 1383 if (err) 1384 pci_set_drvdata(pdev, NULL); 1385 return err; 1386 } 1387 1388 static void 1389 w6692_remove_pci(struct pci_dev *pdev) 1390 { 1391 struct w6692_hw *card = pci_get_drvdata(pdev); 1392 1393 if (card) 1394 release_card(card); 1395 else 1396 if (debug) 1397 pr_notice("%s: drvdata already removed\n", __func__); 1398 } 1399 1400 static const struct pci_device_id w6692_ids[] = { 1401 { PCI_VENDOR_ID_DYNALINK, PCI_DEVICE_ID_DYNALINK_IS64PH, 1402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[0]}, 1403 { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692, 1404 PCI_VENDOR_ID_USR, PCI_DEVICE_ID_USR_6692, 0, 0, 1405 (ulong)&w6692_map[2]}, 1406 { PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692, 1407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (ulong)&w6692_map[1]}, 1408 { } 1409 }; 1410 MODULE_DEVICE_TABLE(pci, w6692_ids); 1411 1412 static struct pci_driver w6692_driver = { 1413 .name = "w6692", 1414 .probe = w6692_probe, 1415 .remove = w6692_remove_pci, 1416 .id_table = w6692_ids, 1417 }; 1418 1419 static int __init w6692_init(void) 1420 { 1421 int err; 1422 1423 pr_notice("Winbond W6692 PCI driver Rev. %s\n", W6692_REV); 1424 1425 err = pci_register_driver(&w6692_driver); 1426 return err; 1427 } 1428 1429 static void __exit w6692_cleanup(void) 1430 { 1431 pci_unregister_driver(&w6692_driver); 1432 } 1433 1434 module_init(w6692_init); 1435 module_exit(w6692_cleanup); 1436