1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 * 5 * Interrupt architecture for the GIC: 6 * 7 * o There is one Interrupt Distributor, which receives interrupts 8 * from system devices and sends them to the Interrupt Controllers. 9 * 10 * o There is one CPU Interface per CPU, which sends interrupts sent 11 * by the Distributor, and interrupts generated locally, to the 12 * associated CPU. The base address of the CPU interface is usually 13 * aliased so that the same address points to different chips depending 14 * on the CPU it is accessed from. 15 * 16 * Note that IRQs 0-31 are special - they are local to each CPU. 17 * As such, the enable set/clear, pending set/clear and active bit 18 * registers are banked per-cpu for these sources. 19 */ 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 #include <linux/cpu_pm.h> 28 #include <linux/cpumask.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/acpi.h> 34 #include <linux/irqdomain.h> 35 #include <linux/interrupt.h> 36 #include <linux/percpu.h> 37 #include <linux/slab.h> 38 #include <linux/irqchip.h> 39 #include <linux/irqchip/chained_irq.h> 40 #include <linux/irqchip/arm-gic.h> 41 42 #include <asm/cputype.h> 43 #include <asm/irq.h> 44 #include <asm/exception.h> 45 #include <asm/smp_plat.h> 46 #include <asm/virt.h> 47 48 #include "irq-gic-common.h" 49 50 #ifdef CONFIG_ARM64 51 #include <asm/cpufeature.h> 52 53 static void gic_check_cpu_features(void) 54 { 55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 56 TAINT_CPU_OUT_OF_SPEC, 57 "GICv3 system registers enabled, broken firmware!\n"); 58 } 59 #else 60 #define gic_check_cpu_features() do { } while(0) 61 #endif 62 63 union gic_base { 64 void __iomem *common_base; 65 void __percpu * __iomem *percpu_base; 66 }; 67 68 struct gic_chip_data { 69 struct irq_chip chip; 70 union gic_base dist_base; 71 union gic_base cpu_base; 72 void __iomem *raw_dist_base; 73 void __iomem *raw_cpu_base; 74 u32 percpu_offset; 75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 #ifdef CONFIG_GIC_NON_BANKED 87 void __iomem *(*get_base)(union gic_base *); 88 #endif 89 }; 90 91 #ifdef CONFIG_BL_SWITCHER 92 93 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 94 95 #define gic_lock_irqsave(f) \ 96 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 97 #define gic_unlock_irqrestore(f) \ 98 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 99 100 #define gic_lock() raw_spin_lock(&cpu_map_lock) 101 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 102 103 #else 104 105 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 106 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 107 108 #define gic_lock() do { } while(0) 109 #define gic_unlock() do { } while(0) 110 111 #endif 112 113 /* 114 * The GIC mapping of CPU interfaces does not necessarily match 115 * the logical CPU numbering. Let's use a mapping as returned 116 * by the GIC itself. 117 */ 118 #define NR_GIC_CPU_IF 8 119 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 120 121 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 122 123 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 124 125 static struct gic_kvm_info gic_v2_kvm_info; 126 127 #ifdef CONFIG_GIC_NON_BANKED 128 static void __iomem *gic_get_percpu_base(union gic_base *base) 129 { 130 return raw_cpu_read(*base->percpu_base); 131 } 132 133 static void __iomem *gic_get_common_base(union gic_base *base) 134 { 135 return base->common_base; 136 } 137 138 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 139 { 140 return data->get_base(&data->dist_base); 141 } 142 143 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 144 { 145 return data->get_base(&data->cpu_base); 146 } 147 148 static inline void gic_set_base_accessor(struct gic_chip_data *data, 149 void __iomem *(*f)(union gic_base *)) 150 { 151 data->get_base = f; 152 } 153 #else 154 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 155 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 156 #define gic_set_base_accessor(d, f) 157 #endif 158 159 static inline void __iomem *gic_dist_base(struct irq_data *d) 160 { 161 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 162 return gic_data_dist_base(gic_data); 163 } 164 165 static inline void __iomem *gic_cpu_base(struct irq_data *d) 166 { 167 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 168 return gic_data_cpu_base(gic_data); 169 } 170 171 static inline unsigned int gic_irq(struct irq_data *d) 172 { 173 return d->hwirq; 174 } 175 176 static inline bool cascading_gic_irq(struct irq_data *d) 177 { 178 void *data = irq_data_get_irq_handler_data(d); 179 180 /* 181 * If handler_data is set, this is a cascading interrupt, and 182 * it cannot possibly be forwarded. 183 */ 184 return data != NULL; 185 } 186 187 /* 188 * Routines to acknowledge, disable and enable interrupts 189 */ 190 static void gic_poke_irq(struct irq_data *d, u32 offset) 191 { 192 u32 mask = 1 << (gic_irq(d) % 32); 193 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 194 } 195 196 static int gic_peek_irq(struct irq_data *d, u32 offset) 197 { 198 u32 mask = 1 << (gic_irq(d) % 32); 199 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 200 } 201 202 static void gic_mask_irq(struct irq_data *d) 203 { 204 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 205 } 206 207 static void gic_eoimode1_mask_irq(struct irq_data *d) 208 { 209 gic_mask_irq(d); 210 /* 211 * When masking a forwarded interrupt, make sure it is 212 * deactivated as well. 213 * 214 * This ensures that an interrupt that is getting 215 * disabled/masked will not get "stuck", because there is 216 * noone to deactivate it (guest is being terminated). 217 */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 220 } 221 222 static void gic_unmask_irq(struct irq_data *d) 223 { 224 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 225 } 226 227 static void gic_eoi_irq(struct irq_data *d) 228 { 229 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 230 } 231 232 static void gic_eoimode1_eoi_irq(struct irq_data *d) 233 { 234 /* Do not deactivate an IRQ forwarded to a vcpu. */ 235 if (irqd_is_forwarded_to_vcpu(d)) 236 return; 237 238 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 239 } 240 241 static int gic_irq_set_irqchip_state(struct irq_data *d, 242 enum irqchip_irq_state which, bool val) 243 { 244 u32 reg; 245 246 switch (which) { 247 case IRQCHIP_STATE_PENDING: 248 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 249 break; 250 251 case IRQCHIP_STATE_ACTIVE: 252 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 253 break; 254 255 case IRQCHIP_STATE_MASKED: 256 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 257 break; 258 259 default: 260 return -EINVAL; 261 } 262 263 gic_poke_irq(d, reg); 264 return 0; 265 } 266 267 static int gic_irq_get_irqchip_state(struct irq_data *d, 268 enum irqchip_irq_state which, bool *val) 269 { 270 switch (which) { 271 case IRQCHIP_STATE_PENDING: 272 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 273 break; 274 275 case IRQCHIP_STATE_ACTIVE: 276 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 277 break; 278 279 case IRQCHIP_STATE_MASKED: 280 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 281 break; 282 283 default: 284 return -EINVAL; 285 } 286 287 return 0; 288 } 289 290 static int gic_set_type(struct irq_data *d, unsigned int type) 291 { 292 void __iomem *base = gic_dist_base(d); 293 unsigned int gicirq = gic_irq(d); 294 int ret; 295 296 /* Interrupt configuration for SGIs can't be changed */ 297 if (gicirq < 16) 298 return -EINVAL; 299 300 /* SPIs have restrictions on the supported types */ 301 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 302 type != IRQ_TYPE_EDGE_RISING) 303 return -EINVAL; 304 305 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); 306 if (ret && gicirq < 32) { 307 /* Misconfigured PPIs are usually not fatal */ 308 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); 309 ret = 0; 310 } 311 312 return ret; 313 } 314 315 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 316 { 317 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 318 if (cascading_gic_irq(d)) 319 return -EINVAL; 320 321 if (vcpu) 322 irqd_set_forwarded_to_vcpu(d); 323 else 324 irqd_clr_forwarded_to_vcpu(d); 325 return 0; 326 } 327 328 #ifdef CONFIG_SMP 329 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 330 bool force) 331 { 332 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d); 333 unsigned int cpu; 334 335 if (!force) 336 cpu = cpumask_any_and(mask_val, cpu_online_mask); 337 else 338 cpu = cpumask_first(mask_val); 339 340 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 341 return -EINVAL; 342 343 writeb_relaxed(gic_cpu_map[cpu], reg); 344 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 345 346 return IRQ_SET_MASK_OK_DONE; 347 } 348 #endif 349 350 static int gic_retrigger(struct irq_data *data) 351 { 352 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 353 } 354 355 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 356 { 357 u32 irqstat, irqnr; 358 struct gic_chip_data *gic = &gic_data[0]; 359 void __iomem *cpu_base = gic_data_cpu_base(gic); 360 361 do { 362 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 363 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 364 365 if (likely(irqnr > 15 && irqnr < 1020)) { 366 if (static_branch_likely(&supports_deactivate_key)) 367 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 368 isb(); 369 handle_domain_irq(gic->domain, irqnr, regs); 370 continue; 371 } 372 if (irqnr < 16) { 373 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 374 if (static_branch_likely(&supports_deactivate_key)) 375 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 376 #ifdef CONFIG_SMP 377 /* 378 * Ensure any shared data written by the CPU sending 379 * the IPI is read after we've read the ACK register 380 * on the GIC. 381 * 382 * Pairs with the write barrier in gic_raise_softirq 383 */ 384 smp_rmb(); 385 handle_IPI(irqnr, regs); 386 #endif 387 continue; 388 } 389 break; 390 } while (1); 391 } 392 393 static void gic_handle_cascade_irq(struct irq_desc *desc) 394 { 395 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 396 struct irq_chip *chip = irq_desc_get_chip(desc); 397 unsigned int cascade_irq, gic_irq; 398 unsigned long status; 399 400 chained_irq_enter(chip, desc); 401 402 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 403 404 gic_irq = (status & GICC_IAR_INT_ID_MASK); 405 if (gic_irq == GICC_INT_SPURIOUS) 406 goto out; 407 408 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 409 if (unlikely(gic_irq < 32 || gic_irq > 1020)) { 410 handle_bad_irq(desc); 411 } else { 412 isb(); 413 generic_handle_irq(cascade_irq); 414 } 415 416 out: 417 chained_irq_exit(chip, desc); 418 } 419 420 static const struct irq_chip gic_chip = { 421 .irq_mask = gic_mask_irq, 422 .irq_unmask = gic_unmask_irq, 423 .irq_eoi = gic_eoi_irq, 424 .irq_set_type = gic_set_type, 425 .irq_retrigger = gic_retrigger, 426 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 427 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 428 .flags = IRQCHIP_SET_TYPE_MASKED | 429 IRQCHIP_SKIP_SET_WAKE | 430 IRQCHIP_MASK_ON_SUSPEND, 431 }; 432 433 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 434 { 435 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 436 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 437 &gic_data[gic_nr]); 438 } 439 440 static u8 gic_get_cpumask(struct gic_chip_data *gic) 441 { 442 void __iomem *base = gic_data_dist_base(gic); 443 u32 mask, i; 444 445 for (i = mask = 0; i < 32; i += 4) { 446 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 447 mask |= mask >> 16; 448 mask |= mask >> 8; 449 if (mask) 450 break; 451 } 452 453 if (!mask && num_possible_cpus() > 1) 454 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 455 456 return mask; 457 } 458 459 static bool gic_check_gicv2(void __iomem *base) 460 { 461 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 462 return (val & 0xff0fff) == 0x02043B; 463 } 464 465 static void gic_cpu_if_up(struct gic_chip_data *gic) 466 { 467 void __iomem *cpu_base = gic_data_cpu_base(gic); 468 u32 bypass = 0; 469 u32 mode = 0; 470 int i; 471 472 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) 473 mode = GIC_CPU_CTRL_EOImodeNS; 474 475 if (gic_check_gicv2(cpu_base)) 476 for (i = 0; i < 4; i++) 477 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); 478 479 /* 480 * Preserve bypass disable bits to be written back later 481 */ 482 bypass = readl(cpu_base + GIC_CPU_CTRL); 483 bypass &= GICC_DIS_BYPASS_MASK; 484 485 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 486 } 487 488 489 static void gic_dist_init(struct gic_chip_data *gic) 490 { 491 unsigned int i; 492 u32 cpumask; 493 unsigned int gic_irqs = gic->gic_irqs; 494 void __iomem *base = gic_data_dist_base(gic); 495 496 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 497 498 /* 499 * Set all global interrupts to this CPU only. 500 */ 501 cpumask = gic_get_cpumask(gic); 502 cpumask |= cpumask << 8; 503 cpumask |= cpumask << 16; 504 for (i = 32; i < gic_irqs; i += 4) 505 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 506 507 gic_dist_config(base, gic_irqs, NULL); 508 509 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 510 } 511 512 static int gic_cpu_init(struct gic_chip_data *gic) 513 { 514 void __iomem *dist_base = gic_data_dist_base(gic); 515 void __iomem *base = gic_data_cpu_base(gic); 516 unsigned int cpu_mask, cpu = smp_processor_id(); 517 int i; 518 519 /* 520 * Setting up the CPU map is only relevant for the primary GIC 521 * because any nested/secondary GICs do not directly interface 522 * with the CPU(s). 523 */ 524 if (gic == &gic_data[0]) { 525 /* 526 * Get what the GIC says our CPU mask is. 527 */ 528 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 529 return -EINVAL; 530 531 gic_check_cpu_features(); 532 cpu_mask = gic_get_cpumask(gic); 533 gic_cpu_map[cpu] = cpu_mask; 534 535 /* 536 * Clear our mask from the other map entries in case they're 537 * still undefined. 538 */ 539 for (i = 0; i < NR_GIC_CPU_IF; i++) 540 if (i != cpu) 541 gic_cpu_map[i] &= ~cpu_mask; 542 } 543 544 gic_cpu_config(dist_base, 32, NULL); 545 546 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 547 gic_cpu_if_up(gic); 548 549 return 0; 550 } 551 552 int gic_cpu_if_down(unsigned int gic_nr) 553 { 554 void __iomem *cpu_base; 555 u32 val = 0; 556 557 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 558 return -EINVAL; 559 560 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 561 val = readl(cpu_base + GIC_CPU_CTRL); 562 val &= ~GICC_ENABLE; 563 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 564 565 return 0; 566 } 567 568 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 569 /* 570 * Saves the GIC distributor registers during suspend or idle. Must be called 571 * with interrupts disabled but before powering down the GIC. After calling 572 * this function, no interrupts will be delivered by the GIC, and another 573 * platform-specific wakeup source must be enabled. 574 */ 575 void gic_dist_save(struct gic_chip_data *gic) 576 { 577 unsigned int gic_irqs; 578 void __iomem *dist_base; 579 int i; 580 581 if (WARN_ON(!gic)) 582 return; 583 584 gic_irqs = gic->gic_irqs; 585 dist_base = gic_data_dist_base(gic); 586 587 if (!dist_base) 588 return; 589 590 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 591 gic->saved_spi_conf[i] = 592 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 593 594 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 595 gic->saved_spi_target[i] = 596 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 597 598 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 599 gic->saved_spi_enable[i] = 600 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 601 602 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 603 gic->saved_spi_active[i] = 604 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 605 } 606 607 /* 608 * Restores the GIC distributor registers during resume or when coming out of 609 * idle. Must be called before enabling interrupts. If a level interrupt 610 * that occurred while the GIC was suspended is still present, it will be 611 * handled normally, but any edge interrupts that occurred will not be seen by 612 * the GIC and need to be handled by the platform-specific wakeup source. 613 */ 614 void gic_dist_restore(struct gic_chip_data *gic) 615 { 616 unsigned int gic_irqs; 617 unsigned int i; 618 void __iomem *dist_base; 619 620 if (WARN_ON(!gic)) 621 return; 622 623 gic_irqs = gic->gic_irqs; 624 dist_base = gic_data_dist_base(gic); 625 626 if (!dist_base) 627 return; 628 629 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 630 631 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 632 writel_relaxed(gic->saved_spi_conf[i], 633 dist_base + GIC_DIST_CONFIG + i * 4); 634 635 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 636 writel_relaxed(GICD_INT_DEF_PRI_X4, 637 dist_base + GIC_DIST_PRI + i * 4); 638 639 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 640 writel_relaxed(gic->saved_spi_target[i], 641 dist_base + GIC_DIST_TARGET + i * 4); 642 643 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 644 writel_relaxed(GICD_INT_EN_CLR_X32, 645 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 646 writel_relaxed(gic->saved_spi_enable[i], 647 dist_base + GIC_DIST_ENABLE_SET + i * 4); 648 } 649 650 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 651 writel_relaxed(GICD_INT_EN_CLR_X32, 652 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 653 writel_relaxed(gic->saved_spi_active[i], 654 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 655 } 656 657 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 658 } 659 660 void gic_cpu_save(struct gic_chip_data *gic) 661 { 662 int i; 663 u32 *ptr; 664 void __iomem *dist_base; 665 void __iomem *cpu_base; 666 667 if (WARN_ON(!gic)) 668 return; 669 670 dist_base = gic_data_dist_base(gic); 671 cpu_base = gic_data_cpu_base(gic); 672 673 if (!dist_base || !cpu_base) 674 return; 675 676 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 677 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 678 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 679 680 ptr = raw_cpu_ptr(gic->saved_ppi_active); 681 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 682 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 683 684 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 685 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 686 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 687 688 } 689 690 void gic_cpu_restore(struct gic_chip_data *gic) 691 { 692 int i; 693 u32 *ptr; 694 void __iomem *dist_base; 695 void __iomem *cpu_base; 696 697 if (WARN_ON(!gic)) 698 return; 699 700 dist_base = gic_data_dist_base(gic); 701 cpu_base = gic_data_cpu_base(gic); 702 703 if (!dist_base || !cpu_base) 704 return; 705 706 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 707 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 708 writel_relaxed(GICD_INT_EN_CLR_X32, 709 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 710 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 711 } 712 713 ptr = raw_cpu_ptr(gic->saved_ppi_active); 714 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 715 writel_relaxed(GICD_INT_EN_CLR_X32, 716 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 717 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 718 } 719 720 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 721 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 722 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 723 724 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 725 writel_relaxed(GICD_INT_DEF_PRI_X4, 726 dist_base + GIC_DIST_PRI + i * 4); 727 728 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 729 gic_cpu_if_up(gic); 730 } 731 732 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 733 { 734 int i; 735 736 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 737 #ifdef CONFIG_GIC_NON_BANKED 738 /* Skip over unused GICs */ 739 if (!gic_data[i].get_base) 740 continue; 741 #endif 742 switch (cmd) { 743 case CPU_PM_ENTER: 744 gic_cpu_save(&gic_data[i]); 745 break; 746 case CPU_PM_ENTER_FAILED: 747 case CPU_PM_EXIT: 748 gic_cpu_restore(&gic_data[i]); 749 break; 750 case CPU_CLUSTER_PM_ENTER: 751 gic_dist_save(&gic_data[i]); 752 break; 753 case CPU_CLUSTER_PM_ENTER_FAILED: 754 case CPU_CLUSTER_PM_EXIT: 755 gic_dist_restore(&gic_data[i]); 756 break; 757 } 758 } 759 760 return NOTIFY_OK; 761 } 762 763 static struct notifier_block gic_notifier_block = { 764 .notifier_call = gic_notifier, 765 }; 766 767 static int gic_pm_init(struct gic_chip_data *gic) 768 { 769 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 770 sizeof(u32)); 771 if (WARN_ON(!gic->saved_ppi_enable)) 772 return -ENOMEM; 773 774 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 775 sizeof(u32)); 776 if (WARN_ON(!gic->saved_ppi_active)) 777 goto free_ppi_enable; 778 779 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 780 sizeof(u32)); 781 if (WARN_ON(!gic->saved_ppi_conf)) 782 goto free_ppi_active; 783 784 if (gic == &gic_data[0]) 785 cpu_pm_register_notifier(&gic_notifier_block); 786 787 return 0; 788 789 free_ppi_active: 790 free_percpu(gic->saved_ppi_active); 791 free_ppi_enable: 792 free_percpu(gic->saved_ppi_enable); 793 794 return -ENOMEM; 795 } 796 #else 797 static int gic_pm_init(struct gic_chip_data *gic) 798 { 799 return 0; 800 } 801 #endif 802 803 #ifdef CONFIG_SMP 804 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 805 { 806 int cpu; 807 unsigned long flags, map = 0; 808 809 if (unlikely(nr_cpu_ids == 1)) { 810 /* Only one CPU? let's do a self-IPI... */ 811 writel_relaxed(2 << 24 | irq, 812 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 813 return; 814 } 815 816 gic_lock_irqsave(flags); 817 818 /* Convert our logical CPU mask into a physical one. */ 819 for_each_cpu(cpu, mask) 820 map |= gic_cpu_map[cpu]; 821 822 /* 823 * Ensure that stores to Normal memory are visible to the 824 * other CPUs before they observe us issuing the IPI. 825 */ 826 dmb(ishst); 827 828 /* this always happens on GIC0 */ 829 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 830 831 gic_unlock_irqrestore(flags); 832 } 833 #endif 834 835 #ifdef CONFIG_BL_SWITCHER 836 /* 837 * gic_send_sgi - send a SGI directly to given CPU interface number 838 * 839 * cpu_id: the ID for the destination CPU interface 840 * irq: the IPI number to send a SGI for 841 */ 842 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 843 { 844 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 845 cpu_id = 1 << cpu_id; 846 /* this always happens on GIC0 */ 847 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 848 } 849 850 /* 851 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 852 * 853 * @cpu: the logical CPU number to get the GIC ID for. 854 * 855 * Return the CPU interface ID for the given logical CPU number, 856 * or -1 if the CPU number is too large or the interface ID is 857 * unknown (more than one bit set). 858 */ 859 int gic_get_cpu_id(unsigned int cpu) 860 { 861 unsigned int cpu_bit; 862 863 if (cpu >= NR_GIC_CPU_IF) 864 return -1; 865 cpu_bit = gic_cpu_map[cpu]; 866 if (cpu_bit & (cpu_bit - 1)) 867 return -1; 868 return __ffs(cpu_bit); 869 } 870 871 /* 872 * gic_migrate_target - migrate IRQs to another CPU interface 873 * 874 * @new_cpu_id: the CPU target ID to migrate IRQs to 875 * 876 * Migrate all peripheral interrupts with a target matching the current CPU 877 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 878 * is also updated. Targets to other CPU interfaces are unchanged. 879 * This must be called with IRQs locally disabled. 880 */ 881 void gic_migrate_target(unsigned int new_cpu_id) 882 { 883 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 884 void __iomem *dist_base; 885 int i, ror_val, cpu = smp_processor_id(); 886 u32 val, cur_target_mask, active_mask; 887 888 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 889 890 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 891 if (!dist_base) 892 return; 893 gic_irqs = gic_data[gic_nr].gic_irqs; 894 895 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 896 cur_target_mask = 0x01010101 << cur_cpu_id; 897 ror_val = (cur_cpu_id - new_cpu_id) & 31; 898 899 gic_lock(); 900 901 /* Update the target interface for this logical CPU */ 902 gic_cpu_map[cpu] = 1 << new_cpu_id; 903 904 /* 905 * Find all the peripheral interrupts targeting the current 906 * CPU interface and migrate them to the new CPU interface. 907 * We skip DIST_TARGET 0 to 7 as they are read-only. 908 */ 909 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 910 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 911 active_mask = val & cur_target_mask; 912 if (active_mask) { 913 val &= ~active_mask; 914 val |= ror32(active_mask, ror_val); 915 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 916 } 917 } 918 919 gic_unlock(); 920 921 /* 922 * Now let's migrate and clear any potential SGIs that might be 923 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 924 * is a banked register, we can only forward the SGI using 925 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 926 * doesn't use that information anyway. 927 * 928 * For the same reason we do not adjust SGI source information 929 * for previously sent SGIs by us to other CPUs either. 930 */ 931 for (i = 0; i < 16; i += 4) { 932 int j; 933 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 934 if (!val) 935 continue; 936 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 937 for (j = i; j < i + 4; j++) { 938 if (val & 0xff) 939 writel_relaxed((1 << (new_cpu_id + 16)) | j, 940 dist_base + GIC_DIST_SOFTINT); 941 val >>= 8; 942 } 943 } 944 } 945 946 /* 947 * gic_get_sgir_physaddr - get the physical address for the SGI register 948 * 949 * REturn the physical address of the SGI register to be used 950 * by some early assembly code when the kernel is not yet available. 951 */ 952 static unsigned long gic_dist_physaddr; 953 954 unsigned long gic_get_sgir_physaddr(void) 955 { 956 if (!gic_dist_physaddr) 957 return 0; 958 return gic_dist_physaddr + GIC_DIST_SOFTINT; 959 } 960 961 static void __init gic_init_physaddr(struct device_node *node) 962 { 963 struct resource res; 964 if (of_address_to_resource(node, 0, &res) == 0) { 965 gic_dist_physaddr = res.start; 966 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 967 } 968 } 969 970 #else 971 #define gic_init_physaddr(node) do { } while (0) 972 #endif 973 974 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 975 irq_hw_number_t hw) 976 { 977 struct gic_chip_data *gic = d->host_data; 978 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 979 980 if (hw < 32) { 981 irq_set_percpu_devid(irq); 982 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 983 handle_percpu_devid_irq, NULL, NULL); 984 } else { 985 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 986 handle_fasteoi_irq, NULL, NULL); 987 irq_set_probe(irq); 988 irqd_set_single_target(irqd); 989 } 990 991 /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 992 irqd_set_handle_enforce_irqctx(irqd); 993 return 0; 994 } 995 996 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 997 { 998 } 999 1000 static int gic_irq_domain_translate(struct irq_domain *d, 1001 struct irq_fwspec *fwspec, 1002 unsigned long *hwirq, 1003 unsigned int *type) 1004 { 1005 if (is_of_node(fwspec->fwnode)) { 1006 if (fwspec->param_count < 3) 1007 return -EINVAL; 1008 1009 /* Get the interrupt number and add 16 to skip over SGIs */ 1010 *hwirq = fwspec->param[1] + 16; 1011 1012 /* 1013 * For SPIs, we need to add 16 more to get the GIC irq 1014 * ID number 1015 */ 1016 if (!fwspec->param[0]) 1017 *hwirq += 16; 1018 1019 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1020 1021 /* Make it clear that broken DTs are... broken */ 1022 WARN_ON(*type == IRQ_TYPE_NONE); 1023 return 0; 1024 } 1025 1026 if (is_fwnode_irqchip(fwspec->fwnode)) { 1027 if(fwspec->param_count != 2) 1028 return -EINVAL; 1029 1030 *hwirq = fwspec->param[0]; 1031 *type = fwspec->param[1]; 1032 1033 WARN_ON(*type == IRQ_TYPE_NONE); 1034 return 0; 1035 } 1036 1037 return -EINVAL; 1038 } 1039 1040 static int gic_starting_cpu(unsigned int cpu) 1041 { 1042 gic_cpu_init(&gic_data[0]); 1043 return 0; 1044 } 1045 1046 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1047 unsigned int nr_irqs, void *arg) 1048 { 1049 int i, ret; 1050 irq_hw_number_t hwirq; 1051 unsigned int type = IRQ_TYPE_NONE; 1052 struct irq_fwspec *fwspec = arg; 1053 1054 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1055 if (ret) 1056 return ret; 1057 1058 for (i = 0; i < nr_irqs; i++) { 1059 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1060 if (ret) 1061 return ret; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1068 .translate = gic_irq_domain_translate, 1069 .alloc = gic_irq_domain_alloc, 1070 .free = irq_domain_free_irqs_top, 1071 }; 1072 1073 static const struct irq_domain_ops gic_irq_domain_ops = { 1074 .map = gic_irq_domain_map, 1075 .unmap = gic_irq_domain_unmap, 1076 }; 1077 1078 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1079 const char *name, bool use_eoimode1) 1080 { 1081 /* Initialize irq_chip */ 1082 gic->chip = gic_chip; 1083 gic->chip.name = name; 1084 gic->chip.parent_device = dev; 1085 1086 if (use_eoimode1) { 1087 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1088 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1089 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1090 } 1091 1092 #ifdef CONFIG_SMP 1093 if (gic == &gic_data[0]) 1094 gic->chip.irq_set_affinity = gic_set_affinity; 1095 #endif 1096 } 1097 1098 static int gic_init_bases(struct gic_chip_data *gic, 1099 struct fwnode_handle *handle) 1100 { 1101 int gic_irqs, ret; 1102 1103 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1104 /* Frankein-GIC without banked registers... */ 1105 unsigned int cpu; 1106 1107 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1108 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1109 if (WARN_ON(!gic->dist_base.percpu_base || 1110 !gic->cpu_base.percpu_base)) { 1111 ret = -ENOMEM; 1112 goto error; 1113 } 1114 1115 for_each_possible_cpu(cpu) { 1116 u32 mpidr = cpu_logical_map(cpu); 1117 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1118 unsigned long offset = gic->percpu_offset * core_id; 1119 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1120 gic->raw_dist_base + offset; 1121 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1122 gic->raw_cpu_base + offset; 1123 } 1124 1125 gic_set_base_accessor(gic, gic_get_percpu_base); 1126 } else { 1127 /* Normal, sane GIC... */ 1128 WARN(gic->percpu_offset, 1129 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1130 gic->percpu_offset); 1131 gic->dist_base.common_base = gic->raw_dist_base; 1132 gic->cpu_base.common_base = gic->raw_cpu_base; 1133 gic_set_base_accessor(gic, gic_get_common_base); 1134 } 1135 1136 /* 1137 * Find out how many interrupts are supported. 1138 * The GIC only supports up to 1020 interrupt sources. 1139 */ 1140 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1141 gic_irqs = (gic_irqs + 1) * 32; 1142 if (gic_irqs > 1020) 1143 gic_irqs = 1020; 1144 gic->gic_irqs = gic_irqs; 1145 1146 if (handle) { /* DT/ACPI */ 1147 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1148 &gic_irq_domain_hierarchy_ops, 1149 gic); 1150 } else { /* Legacy support */ 1151 /* 1152 * For primary GICs, skip over SGIs. 1153 * No secondary GIC support whatsoever. 1154 */ 1155 int irq_base; 1156 1157 gic_irqs -= 16; /* calculate # of irqs to allocate */ 1158 1159 irq_base = irq_alloc_descs(16, 16, gic_irqs, 1160 numa_node_id()); 1161 if (irq_base < 0) { 1162 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); 1163 irq_base = 16; 1164 } 1165 1166 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1167 16, &gic_irq_domain_ops, gic); 1168 } 1169 1170 if (WARN_ON(!gic->domain)) { 1171 ret = -ENODEV; 1172 goto error; 1173 } 1174 1175 gic_dist_init(gic); 1176 ret = gic_cpu_init(gic); 1177 if (ret) 1178 goto error; 1179 1180 ret = gic_pm_init(gic); 1181 if (ret) 1182 goto error; 1183 1184 return 0; 1185 1186 error: 1187 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1188 free_percpu(gic->dist_base.percpu_base); 1189 free_percpu(gic->cpu_base.percpu_base); 1190 } 1191 1192 return ret; 1193 } 1194 1195 static int __init __gic_init_bases(struct gic_chip_data *gic, 1196 struct fwnode_handle *handle) 1197 { 1198 char *name; 1199 int i, ret; 1200 1201 if (WARN_ON(!gic || gic->domain)) 1202 return -EINVAL; 1203 1204 if (gic == &gic_data[0]) { 1205 /* 1206 * Initialize the CPU interface map to all CPUs. 1207 * It will be refined as each CPU probes its ID. 1208 * This is only necessary for the primary GIC. 1209 */ 1210 for (i = 0; i < NR_GIC_CPU_IF; i++) 1211 gic_cpu_map[i] = 0xff; 1212 #ifdef CONFIG_SMP 1213 set_smp_cross_call(gic_raise_softirq); 1214 #endif 1215 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1216 "irqchip/arm/gic:starting", 1217 gic_starting_cpu, NULL); 1218 set_handle_irq(gic_handle_irq); 1219 if (static_branch_likely(&supports_deactivate_key)) 1220 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1221 } 1222 1223 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { 1224 name = kasprintf(GFP_KERNEL, "GICv2"); 1225 gic_init_chip(gic, NULL, name, true); 1226 } else { 1227 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1228 gic_init_chip(gic, NULL, name, false); 1229 } 1230 1231 ret = gic_init_bases(gic, handle); 1232 if (ret) 1233 kfree(name); 1234 1235 return ret; 1236 } 1237 1238 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) 1239 { 1240 struct gic_chip_data *gic; 1241 1242 /* 1243 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1244 * bother with these... 1245 */ 1246 static_branch_disable(&supports_deactivate_key); 1247 1248 gic = &gic_data[0]; 1249 gic->raw_dist_base = dist_base; 1250 gic->raw_cpu_base = cpu_base; 1251 1252 __gic_init_bases(gic, NULL); 1253 } 1254 1255 static void gic_teardown(struct gic_chip_data *gic) 1256 { 1257 if (WARN_ON(!gic)) 1258 return; 1259 1260 if (gic->raw_dist_base) 1261 iounmap(gic->raw_dist_base); 1262 if (gic->raw_cpu_base) 1263 iounmap(gic->raw_cpu_base); 1264 } 1265 1266 #ifdef CONFIG_OF 1267 static int gic_cnt __initdata; 1268 static bool gicv2_force_probe; 1269 1270 static int __init gicv2_force_probe_cfg(char *buf) 1271 { 1272 return strtobool(buf, &gicv2_force_probe); 1273 } 1274 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1275 1276 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1277 { 1278 struct resource cpuif_res; 1279 1280 of_address_to_resource(node, 1, &cpuif_res); 1281 1282 if (!is_hyp_mode_available()) 1283 return false; 1284 if (resource_size(&cpuif_res) < SZ_8K) { 1285 void __iomem *alt; 1286 /* 1287 * Check for a stupid firmware that only exposes the 1288 * first page of a GICv2. 1289 */ 1290 if (!gic_check_gicv2(*base)) 1291 return false; 1292 1293 if (!gicv2_force_probe) { 1294 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1295 return false; 1296 } 1297 1298 alt = ioremap(cpuif_res.start, SZ_8K); 1299 if (!alt) 1300 return false; 1301 if (!gic_check_gicv2(alt + SZ_4K)) { 1302 /* 1303 * The first page was that of a GICv2, and 1304 * the second was *something*. Let's trust it 1305 * to be a GICv2, and update the mapping. 1306 */ 1307 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1308 &cpuif_res.start); 1309 iounmap(*base); 1310 *base = alt; 1311 return true; 1312 } 1313 1314 /* 1315 * We detected *two* initial GICv2 pages in a 1316 * row. Could be a GICv2 aliased over two 64kB 1317 * pages. Update the resource, map the iospace, and 1318 * pray. 1319 */ 1320 iounmap(alt); 1321 alt = ioremap(cpuif_res.start, SZ_128K); 1322 if (!alt) 1323 return false; 1324 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1325 &cpuif_res.start); 1326 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1327 iounmap(*base); 1328 *base = alt; 1329 } 1330 if (resource_size(&cpuif_res) == SZ_128K) { 1331 /* 1332 * Verify that we have the first 4kB of a GICv2 1333 * aliased over the first 64kB by checking the 1334 * GICC_IIDR register on both ends. 1335 */ 1336 if (!gic_check_gicv2(*base) || 1337 !gic_check_gicv2(*base + 0xf000)) 1338 return false; 1339 1340 /* 1341 * Move the base up by 60kB, so that we have a 8kB 1342 * contiguous region, which allows us to use GICC_DIR 1343 * at its normal offset. Please pass me that bucket. 1344 */ 1345 *base += 0xf000; 1346 cpuif_res.start += 0xf000; 1347 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1348 &cpuif_res.start); 1349 } 1350 1351 return true; 1352 } 1353 1354 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1355 { 1356 if (!gic || !node) 1357 return -EINVAL; 1358 1359 gic->raw_dist_base = of_iomap(node, 0); 1360 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1361 goto error; 1362 1363 gic->raw_cpu_base = of_iomap(node, 1); 1364 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1365 goto error; 1366 1367 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1368 gic->percpu_offset = 0; 1369 1370 return 0; 1371 1372 error: 1373 gic_teardown(gic); 1374 1375 return -ENOMEM; 1376 } 1377 1378 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1379 { 1380 int ret; 1381 1382 if (!dev || !dev->of_node || !gic || !irq) 1383 return -EINVAL; 1384 1385 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1386 if (!*gic) 1387 return -ENOMEM; 1388 1389 gic_init_chip(*gic, dev, dev->of_node->name, false); 1390 1391 ret = gic_of_setup(*gic, dev->of_node); 1392 if (ret) 1393 return ret; 1394 1395 ret = gic_init_bases(*gic, &dev->of_node->fwnode); 1396 if (ret) { 1397 gic_teardown(*gic); 1398 return ret; 1399 } 1400 1401 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1402 1403 return 0; 1404 } 1405 1406 static void __init gic_of_setup_kvm_info(struct device_node *node) 1407 { 1408 int ret; 1409 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1410 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1411 1412 gic_v2_kvm_info.type = GIC_V2; 1413 1414 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1415 if (!gic_v2_kvm_info.maint_irq) 1416 return; 1417 1418 ret = of_address_to_resource(node, 2, vctrl_res); 1419 if (ret) 1420 return; 1421 1422 ret = of_address_to_resource(node, 3, vcpu_res); 1423 if (ret) 1424 return; 1425 1426 if (static_branch_likely(&supports_deactivate_key)) 1427 gic_set_kvm_info(&gic_v2_kvm_info); 1428 } 1429 1430 int __init 1431 gic_of_init(struct device_node *node, struct device_node *parent) 1432 { 1433 struct gic_chip_data *gic; 1434 int irq, ret; 1435 1436 if (WARN_ON(!node)) 1437 return -ENODEV; 1438 1439 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1440 return -EINVAL; 1441 1442 gic = &gic_data[gic_cnt]; 1443 1444 ret = gic_of_setup(gic, node); 1445 if (ret) 1446 return ret; 1447 1448 /* 1449 * Disable split EOI/Deactivate if either HYP is not available 1450 * or the CPU interface is too small. 1451 */ 1452 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1453 static_branch_disable(&supports_deactivate_key); 1454 1455 ret = __gic_init_bases(gic, &node->fwnode); 1456 if (ret) { 1457 gic_teardown(gic); 1458 return ret; 1459 } 1460 1461 if (!gic_cnt) { 1462 gic_init_physaddr(node); 1463 gic_of_setup_kvm_info(node); 1464 } 1465 1466 if (parent) { 1467 irq = irq_of_parse_and_map(node, 0); 1468 gic_cascade_irq(gic_cnt, irq); 1469 } 1470 1471 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1472 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1473 1474 gic_cnt++; 1475 return 0; 1476 } 1477 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1478 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1479 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1480 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1481 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1482 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1483 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1484 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1485 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1486 #else 1487 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1488 { 1489 return -ENOTSUPP; 1490 } 1491 #endif 1492 1493 #ifdef CONFIG_ACPI 1494 static struct 1495 { 1496 phys_addr_t cpu_phys_base; 1497 u32 maint_irq; 1498 int maint_irq_mode; 1499 phys_addr_t vctrl_base; 1500 phys_addr_t vcpu_base; 1501 } acpi_data __initdata; 1502 1503 static int __init 1504 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, 1505 const unsigned long end) 1506 { 1507 struct acpi_madt_generic_interrupt *processor; 1508 phys_addr_t gic_cpu_base; 1509 static int cpu_base_assigned; 1510 1511 processor = (struct acpi_madt_generic_interrupt *)header; 1512 1513 if (BAD_MADT_GICC_ENTRY(processor, end)) 1514 return -EINVAL; 1515 1516 /* 1517 * There is no support for non-banked GICv1/2 register in ACPI spec. 1518 * All CPU interface addresses have to be the same. 1519 */ 1520 gic_cpu_base = processor->base_address; 1521 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1522 return -EINVAL; 1523 1524 acpi_data.cpu_phys_base = gic_cpu_base; 1525 acpi_data.maint_irq = processor->vgic_interrupt; 1526 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1527 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1528 acpi_data.vctrl_base = processor->gich_base_address; 1529 acpi_data.vcpu_base = processor->gicv_base_address; 1530 1531 cpu_base_assigned = 1; 1532 return 0; 1533 } 1534 1535 /* The things you have to do to just *count* something... */ 1536 static int __init acpi_dummy_func(union acpi_subtable_headers *header, 1537 const unsigned long end) 1538 { 1539 return 0; 1540 } 1541 1542 static bool __init acpi_gic_redist_is_present(void) 1543 { 1544 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1545 acpi_dummy_func, 0) > 0; 1546 } 1547 1548 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1549 struct acpi_probe_entry *ape) 1550 { 1551 struct acpi_madt_generic_distributor *dist; 1552 dist = (struct acpi_madt_generic_distributor *)header; 1553 1554 return (dist->version == ape->driver_data && 1555 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1556 !acpi_gic_redist_is_present())); 1557 } 1558 1559 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1560 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1561 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1562 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1563 1564 static void __init gic_acpi_setup_kvm_info(void) 1565 { 1566 int irq; 1567 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1568 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1569 1570 gic_v2_kvm_info.type = GIC_V2; 1571 1572 if (!acpi_data.vctrl_base) 1573 return; 1574 1575 vctrl_res->flags = IORESOURCE_MEM; 1576 vctrl_res->start = acpi_data.vctrl_base; 1577 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1578 1579 if (!acpi_data.vcpu_base) 1580 return; 1581 1582 vcpu_res->flags = IORESOURCE_MEM; 1583 vcpu_res->start = acpi_data.vcpu_base; 1584 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1585 1586 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1587 acpi_data.maint_irq_mode, 1588 ACPI_ACTIVE_HIGH); 1589 if (irq <= 0) 1590 return; 1591 1592 gic_v2_kvm_info.maint_irq = irq; 1593 1594 gic_set_kvm_info(&gic_v2_kvm_info); 1595 } 1596 1597 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header, 1598 const unsigned long end) 1599 { 1600 struct acpi_madt_generic_distributor *dist; 1601 struct fwnode_handle *domain_handle; 1602 struct gic_chip_data *gic = &gic_data[0]; 1603 int count, ret; 1604 1605 /* Collect CPU base addresses */ 1606 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1607 gic_acpi_parse_madt_cpu, 0); 1608 if (count <= 0) { 1609 pr_err("No valid GICC entries exist\n"); 1610 return -EINVAL; 1611 } 1612 1613 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1614 if (!gic->raw_cpu_base) { 1615 pr_err("Unable to map GICC registers\n"); 1616 return -ENOMEM; 1617 } 1618 1619 dist = (struct acpi_madt_generic_distributor *)header; 1620 gic->raw_dist_base = ioremap(dist->base_address, 1621 ACPI_GICV2_DIST_MEM_SIZE); 1622 if (!gic->raw_dist_base) { 1623 pr_err("Unable to map GICD registers\n"); 1624 gic_teardown(gic); 1625 return -ENOMEM; 1626 } 1627 1628 /* 1629 * Disable split EOI/Deactivate if HYP is not available. ACPI 1630 * guarantees that we'll always have a GICv2, so the CPU 1631 * interface will always be the right size. 1632 */ 1633 if (!is_hyp_mode_available()) 1634 static_branch_disable(&supports_deactivate_key); 1635 1636 /* 1637 * Initialize GIC instance zero (no multi-GIC support). 1638 */ 1639 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 1640 if (!domain_handle) { 1641 pr_err("Unable to allocate domain handle\n"); 1642 gic_teardown(gic); 1643 return -ENOMEM; 1644 } 1645 1646 ret = __gic_init_bases(gic, domain_handle); 1647 if (ret) { 1648 pr_err("Failed to initialise GIC\n"); 1649 irq_domain_free_fwnode(domain_handle); 1650 gic_teardown(gic); 1651 return ret; 1652 } 1653 1654 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1655 1656 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1657 gicv2m_init(NULL, gic_data[0].domain); 1658 1659 if (static_branch_likely(&supports_deactivate_key)) 1660 gic_acpi_setup_kvm_info(); 1661 1662 return 0; 1663 } 1664 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1665 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1666 gic_v2_acpi_init); 1667 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1668 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1669 gic_v2_acpi_init); 1670 #endif 1671