1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021, Linaro Ltd. 6 * 7 */ 8 9 #include <dt-bindings/interconnect/qcom,qcm2290.h> 10 #include <linux/device.h> 11 #include <linux/interconnect-provider.h> 12 #include <linux/io.h> 13 #include <linux/mod_devicetable.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 19 #include "icc-rpm.h" 20 21 enum { 22 QCM2290_MASTER_APPSS_PROC = 1, 23 QCM2290_MASTER_SNOC_BIMC_RT, 24 QCM2290_MASTER_SNOC_BIMC_NRT, 25 QCM2290_MASTER_SNOC_BIMC, 26 QCM2290_MASTER_TCU_0, 27 QCM2290_MASTER_GFX3D, 28 QCM2290_MASTER_SNOC_CNOC, 29 QCM2290_MASTER_QDSS_DAP, 30 QCM2290_MASTER_CRYPTO_CORE0, 31 QCM2290_MASTER_SNOC_CFG, 32 QCM2290_MASTER_TIC, 33 QCM2290_MASTER_ANOC_SNOC, 34 QCM2290_MASTER_BIMC_SNOC, 35 QCM2290_MASTER_PIMEM, 36 QCM2290_MASTER_QDSS_BAM, 37 QCM2290_MASTER_QUP_0, 38 QCM2290_MASTER_IPA, 39 QCM2290_MASTER_QDSS_ETR, 40 QCM2290_MASTER_SDCC_1, 41 QCM2290_MASTER_SDCC_2, 42 QCM2290_MASTER_QPIC, 43 QCM2290_MASTER_USB3_0, 44 QCM2290_MASTER_QUP_CORE_0, 45 QCM2290_MASTER_CAMNOC_SF, 46 QCM2290_MASTER_VIDEO_P0, 47 QCM2290_MASTER_VIDEO_PROC, 48 QCM2290_MASTER_CAMNOC_HF, 49 QCM2290_MASTER_MDP0, 50 51 QCM2290_SLAVE_EBI1, 52 QCM2290_SLAVE_BIMC_SNOC, 53 QCM2290_SLAVE_BIMC_CFG, 54 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 55 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 56 QCM2290_SLAVE_CAMERA_CFG, 57 QCM2290_SLAVE_CLK_CTL, 58 QCM2290_SLAVE_CRYPTO_0_CFG, 59 QCM2290_SLAVE_DISPLAY_CFG, 60 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 61 QCM2290_SLAVE_GPU_CFG, 62 QCM2290_SLAVE_HWKM, 63 QCM2290_SLAVE_IMEM_CFG, 64 QCM2290_SLAVE_IPA_CFG, 65 QCM2290_SLAVE_LPASS, 66 QCM2290_SLAVE_MESSAGE_RAM, 67 QCM2290_SLAVE_PDM, 68 QCM2290_SLAVE_PIMEM_CFG, 69 QCM2290_SLAVE_PKA_WRAPPER, 70 QCM2290_SLAVE_PMIC_ARB, 71 QCM2290_SLAVE_PRNG, 72 QCM2290_SLAVE_QDSS_CFG, 73 QCM2290_SLAVE_QM_CFG, 74 QCM2290_SLAVE_QM_MPU_CFG, 75 QCM2290_SLAVE_QPIC, 76 QCM2290_SLAVE_QUP_0, 77 QCM2290_SLAVE_SDCC_1, 78 QCM2290_SLAVE_SDCC_2, 79 QCM2290_SLAVE_SNOC_CFG, 80 QCM2290_SLAVE_TCSR, 81 QCM2290_SLAVE_USB3, 82 QCM2290_SLAVE_VENUS_CFG, 83 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 84 QCM2290_SLAVE_VSENSE_CTRL_CFG, 85 QCM2290_SLAVE_SERVICE_CNOC, 86 QCM2290_SLAVE_APPSS, 87 QCM2290_SLAVE_SNOC_CNOC, 88 QCM2290_SLAVE_IMEM, 89 QCM2290_SLAVE_PIMEM, 90 QCM2290_SLAVE_SNOC_BIMC, 91 QCM2290_SLAVE_SERVICE_SNOC, 92 QCM2290_SLAVE_QDSS_STM, 93 QCM2290_SLAVE_TCU, 94 QCM2290_SLAVE_ANOC_SNOC, 95 QCM2290_SLAVE_QUP_CORE_0, 96 QCM2290_SLAVE_SNOC_BIMC_NRT, 97 QCM2290_SLAVE_SNOC_BIMC_RT, 98 }; 99 100 /* Master nodes */ 101 static const u16 mas_appss_proc_links[] = { 102 QCM2290_SLAVE_EBI1, 103 QCM2290_SLAVE_BIMC_SNOC, 104 }; 105 106 static struct qcom_icc_node mas_appss_proc = { 107 .id = QCM2290_MASTER_APPSS_PROC, 108 .name = "mas_apps_proc", 109 .buswidth = 16, 110 .qos.ap_owned = true, 111 .qos.qos_port = 0, 112 .qos.qos_mode = NOC_QOS_MODE_FIXED, 113 .qos.prio_level = 0, 114 .qos.areq_prio = 0, 115 .mas_rpm_id = 0, 116 .slv_rpm_id = -1, 117 .num_links = ARRAY_SIZE(mas_appss_proc_links), 118 .links = mas_appss_proc_links, 119 }; 120 121 static const u16 mas_snoc_bimc_rt_links[] = { 122 QCM2290_SLAVE_EBI1, 123 }; 124 125 static struct qcom_icc_node mas_snoc_bimc_rt = { 126 .id = QCM2290_MASTER_SNOC_BIMC_RT, 127 .name = "mas_snoc_bimc_rt", 128 .buswidth = 16, 129 .qos.ap_owned = true, 130 .qos.qos_port = 2, 131 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 132 .mas_rpm_id = 163, 133 .slv_rpm_id = -1, 134 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links), 135 .links = mas_snoc_bimc_rt_links, 136 }; 137 138 static const u16 mas_snoc_bimc_nrt_links[] = { 139 QCM2290_SLAVE_EBI1, 140 }; 141 142 static struct qcom_icc_node mas_snoc_bimc_nrt = { 143 .id = QCM2290_MASTER_SNOC_BIMC_NRT, 144 .name = "mas_snoc_bimc_nrt", 145 .buswidth = 16, 146 .qos.ap_owned = true, 147 .qos.qos_port = 3, 148 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 149 .mas_rpm_id = 164, 150 .slv_rpm_id = -1, 151 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links), 152 .links = mas_snoc_bimc_nrt_links, 153 }; 154 155 static const u16 mas_snoc_bimc_links[] = { 156 QCM2290_SLAVE_EBI1, 157 }; 158 159 static struct qcom_icc_node mas_snoc_bimc = { 160 .id = QCM2290_MASTER_SNOC_BIMC, 161 .name = "mas_snoc_bimc", 162 .buswidth = 16, 163 .qos.ap_owned = true, 164 .qos.qos_port = 6, 165 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 166 .mas_rpm_id = 164, 167 .slv_rpm_id = -1, 168 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 169 .links = mas_snoc_bimc_links, 170 }; 171 172 static const u16 mas_tcu_0_links[] = { 173 QCM2290_SLAVE_EBI1, 174 QCM2290_SLAVE_BIMC_SNOC, 175 }; 176 177 static struct qcom_icc_node mas_tcu_0 = { 178 .id = QCM2290_MASTER_TCU_0, 179 .name = "mas_tcu_0", 180 .buswidth = 8, 181 .qos.ap_owned = true, 182 .qos.qos_port = 4, 183 .qos.qos_mode = NOC_QOS_MODE_FIXED, 184 .qos.prio_level = 6, 185 .qos.areq_prio = 6, 186 .mas_rpm_id = 102, 187 .slv_rpm_id = -1, 188 .num_links = ARRAY_SIZE(mas_tcu_0_links), 189 .links = mas_tcu_0_links, 190 }; 191 192 static const u16 mas_snoc_cnoc_links[] = { 193 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 194 QCM2290_SLAVE_SDCC_2, 195 QCM2290_SLAVE_SDCC_1, 196 QCM2290_SLAVE_QM_CFG, 197 QCM2290_SLAVE_BIMC_CFG, 198 QCM2290_SLAVE_USB3, 199 QCM2290_SLAVE_QM_MPU_CFG, 200 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 201 QCM2290_SLAVE_QDSS_CFG, 202 QCM2290_SLAVE_PDM, 203 QCM2290_SLAVE_IPA_CFG, 204 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 205 QCM2290_SLAVE_TCSR, 206 QCM2290_SLAVE_MESSAGE_RAM, 207 QCM2290_SLAVE_PMIC_ARB, 208 QCM2290_SLAVE_LPASS, 209 QCM2290_SLAVE_DISPLAY_CFG, 210 QCM2290_SLAVE_VENUS_CFG, 211 QCM2290_SLAVE_GPU_CFG, 212 QCM2290_SLAVE_IMEM_CFG, 213 QCM2290_SLAVE_SNOC_CFG, 214 QCM2290_SLAVE_SERVICE_CNOC, 215 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 216 QCM2290_SLAVE_PKA_WRAPPER, 217 QCM2290_SLAVE_HWKM, 218 QCM2290_SLAVE_PRNG, 219 QCM2290_SLAVE_VSENSE_CTRL_CFG, 220 QCM2290_SLAVE_CRYPTO_0_CFG, 221 QCM2290_SLAVE_PIMEM_CFG, 222 QCM2290_SLAVE_QUP_0, 223 QCM2290_SLAVE_CAMERA_CFG, 224 QCM2290_SLAVE_CLK_CTL, 225 QCM2290_SLAVE_QPIC, 226 }; 227 228 static struct qcom_icc_node mas_snoc_cnoc = { 229 .id = QCM2290_MASTER_SNOC_CNOC, 230 .name = "mas_snoc_cnoc", 231 .buswidth = 8, 232 .qos.ap_owned = true, 233 .qos.qos_mode = NOC_QOS_MODE_INVALID, 234 .mas_rpm_id = 52, 235 .slv_rpm_id = -1, 236 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 237 .links = mas_snoc_cnoc_links, 238 }; 239 240 static const u16 mas_qdss_dap_links[] = { 241 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 242 QCM2290_SLAVE_SDCC_2, 243 QCM2290_SLAVE_SDCC_1, 244 QCM2290_SLAVE_QM_CFG, 245 QCM2290_SLAVE_BIMC_CFG, 246 QCM2290_SLAVE_USB3, 247 QCM2290_SLAVE_QM_MPU_CFG, 248 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 249 QCM2290_SLAVE_QDSS_CFG, 250 QCM2290_SLAVE_PDM, 251 QCM2290_SLAVE_IPA_CFG, 252 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 253 QCM2290_SLAVE_TCSR, 254 QCM2290_SLAVE_MESSAGE_RAM, 255 QCM2290_SLAVE_PMIC_ARB, 256 QCM2290_SLAVE_LPASS, 257 QCM2290_SLAVE_DISPLAY_CFG, 258 QCM2290_SLAVE_VENUS_CFG, 259 QCM2290_SLAVE_GPU_CFG, 260 QCM2290_SLAVE_IMEM_CFG, 261 QCM2290_SLAVE_SNOC_CFG, 262 QCM2290_SLAVE_SERVICE_CNOC, 263 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 264 QCM2290_SLAVE_PKA_WRAPPER, 265 QCM2290_SLAVE_HWKM, 266 QCM2290_SLAVE_PRNG, 267 QCM2290_SLAVE_VSENSE_CTRL_CFG, 268 QCM2290_SLAVE_CRYPTO_0_CFG, 269 QCM2290_SLAVE_PIMEM_CFG, 270 QCM2290_SLAVE_QUP_0, 271 QCM2290_SLAVE_CAMERA_CFG, 272 QCM2290_SLAVE_CLK_CTL, 273 QCM2290_SLAVE_QPIC, 274 }; 275 276 static struct qcom_icc_node mas_qdss_dap = { 277 .id = QCM2290_MASTER_QDSS_DAP, 278 .name = "mas_qdss_dap", 279 .buswidth = 8, 280 .qos.ap_owned = true, 281 .qos.qos_mode = NOC_QOS_MODE_INVALID, 282 .mas_rpm_id = 49, 283 .slv_rpm_id = -1, 284 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 285 .links = mas_qdss_dap_links, 286 }; 287 288 static const u16 mas_crypto_core0_links[] = { 289 QCM2290_SLAVE_ANOC_SNOC 290 }; 291 292 static struct qcom_icc_node mas_crypto_core0 = { 293 .id = QCM2290_MASTER_CRYPTO_CORE0, 294 .name = "mas_crypto_core0", 295 .buswidth = 8, 296 .qos.ap_owned = true, 297 .qos.qos_port = 22, 298 .qos.qos_mode = NOC_QOS_MODE_FIXED, 299 .qos.areq_prio = 2, 300 .mas_rpm_id = 23, 301 .slv_rpm_id = -1, 302 .num_links = ARRAY_SIZE(mas_crypto_core0_links), 303 .links = mas_crypto_core0_links, 304 }; 305 306 static const u16 mas_qup_core_0_links[] = { 307 QCM2290_SLAVE_QUP_CORE_0, 308 }; 309 310 static struct qcom_icc_node mas_qup_core_0 = { 311 .id = QCM2290_MASTER_QUP_CORE_0, 312 .name = "mas_qup_core_0", 313 .buswidth = 4, 314 .mas_rpm_id = 170, 315 .slv_rpm_id = -1, 316 .num_links = ARRAY_SIZE(mas_qup_core_0_links), 317 .links = mas_qup_core_0_links, 318 }; 319 320 static const u16 mas_camnoc_sf_links[] = { 321 QCM2290_SLAVE_SNOC_BIMC_NRT, 322 }; 323 324 static struct qcom_icc_node mas_camnoc_sf = { 325 .id = QCM2290_MASTER_CAMNOC_SF, 326 .name = "mas_camnoc_sf", 327 .buswidth = 32, 328 .qos.ap_owned = true, 329 .qos.qos_port = 4, 330 .qos.qos_mode = NOC_QOS_MODE_FIXED, 331 .qos.areq_prio = 3, 332 .mas_rpm_id = 172, 333 .slv_rpm_id = -1, 334 .num_links = ARRAY_SIZE(mas_camnoc_sf_links), 335 .links = mas_camnoc_sf_links, 336 }; 337 338 static const u16 mas_camnoc_hf_links[] = { 339 QCM2290_SLAVE_SNOC_BIMC_RT, 340 }; 341 342 static struct qcom_icc_node mas_camnoc_hf = { 343 .id = QCM2290_MASTER_CAMNOC_HF, 344 .name = "mas_camnoc_hf", 345 .buswidth = 32, 346 .qos.ap_owned = true, 347 .qos.qos_port = 10, 348 .qos.qos_mode = NOC_QOS_MODE_FIXED, 349 .qos.areq_prio = 3, 350 .qos.urg_fwd_en = true, 351 .mas_rpm_id = 173, 352 .slv_rpm_id = -1, 353 .num_links = ARRAY_SIZE(mas_camnoc_hf_links), 354 .links = mas_camnoc_hf_links, 355 }; 356 357 static const u16 mas_mdp0_links[] = { 358 QCM2290_SLAVE_SNOC_BIMC_RT, 359 }; 360 361 static struct qcom_icc_node mas_mdp0 = { 362 .id = QCM2290_MASTER_MDP0, 363 .name = "mas_mdp0", 364 .buswidth = 16, 365 .qos.ap_owned = true, 366 .qos.qos_port = 5, 367 .qos.qos_mode = NOC_QOS_MODE_FIXED, 368 .qos.areq_prio = 3, 369 .qos.urg_fwd_en = true, 370 .mas_rpm_id = 8, 371 .slv_rpm_id = -1, 372 .num_links = ARRAY_SIZE(mas_mdp0_links), 373 .links = mas_mdp0_links, 374 }; 375 376 static const u16 mas_video_p0_links[] = { 377 QCM2290_SLAVE_SNOC_BIMC_NRT, 378 }; 379 380 static struct qcom_icc_node mas_video_p0 = { 381 .id = QCM2290_MASTER_VIDEO_P0, 382 .name = "mas_video_p0", 383 .buswidth = 16, 384 .qos.ap_owned = true, 385 .qos.qos_port = 9, 386 .qos.qos_mode = NOC_QOS_MODE_FIXED, 387 .qos.areq_prio = 3, 388 .qos.urg_fwd_en = true, 389 .mas_rpm_id = 9, 390 .slv_rpm_id = -1, 391 .num_links = ARRAY_SIZE(mas_video_p0_links), 392 .links = mas_video_p0_links, 393 }; 394 395 static const u16 mas_video_proc_links[] = { 396 QCM2290_SLAVE_SNOC_BIMC_NRT, 397 }; 398 399 static struct qcom_icc_node mas_video_proc = { 400 .id = QCM2290_MASTER_VIDEO_PROC, 401 .name = "mas_video_proc", 402 .buswidth = 8, 403 .qos.ap_owned = true, 404 .qos.qos_port = 13, 405 .qos.qos_mode = NOC_QOS_MODE_FIXED, 406 .qos.areq_prio = 4, 407 .mas_rpm_id = 168, 408 .slv_rpm_id = -1, 409 .num_links = ARRAY_SIZE(mas_video_proc_links), 410 .links = mas_video_proc_links, 411 }; 412 413 static const u16 mas_snoc_cfg_links[] = { 414 QCM2290_SLAVE_SERVICE_SNOC, 415 }; 416 417 static struct qcom_icc_node mas_snoc_cfg = { 418 .id = QCM2290_MASTER_SNOC_CFG, 419 .name = "mas_snoc_cfg", 420 .buswidth = 4, 421 .qos.ap_owned = true, 422 .qos.qos_mode = NOC_QOS_MODE_INVALID, 423 .mas_rpm_id = 20, 424 .slv_rpm_id = -1, 425 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 426 .links = mas_snoc_cfg_links, 427 }; 428 429 static const u16 mas_tic_links[] = { 430 QCM2290_SLAVE_PIMEM, 431 QCM2290_SLAVE_IMEM, 432 QCM2290_SLAVE_APPSS, 433 QCM2290_SLAVE_SNOC_BIMC, 434 QCM2290_SLAVE_SNOC_CNOC, 435 QCM2290_SLAVE_TCU, 436 QCM2290_SLAVE_QDSS_STM, 437 }; 438 439 static struct qcom_icc_node mas_tic = { 440 .id = QCM2290_MASTER_TIC, 441 .name = "mas_tic", 442 .buswidth = 4, 443 .qos.ap_owned = true, 444 .qos.qos_port = 8, 445 .qos.qos_mode = NOC_QOS_MODE_FIXED, 446 .qos.areq_prio = 2, 447 .mas_rpm_id = 51, 448 .slv_rpm_id = -1, 449 .num_links = ARRAY_SIZE(mas_tic_links), 450 .links = mas_tic_links, 451 }; 452 453 static const u16 mas_anoc_snoc_links[] = { 454 QCM2290_SLAVE_PIMEM, 455 QCM2290_SLAVE_IMEM, 456 QCM2290_SLAVE_APPSS, 457 QCM2290_SLAVE_SNOC_BIMC, 458 QCM2290_SLAVE_SNOC_CNOC, 459 QCM2290_SLAVE_TCU, 460 QCM2290_SLAVE_QDSS_STM, 461 }; 462 463 static struct qcom_icc_node mas_anoc_snoc = { 464 .id = QCM2290_MASTER_ANOC_SNOC, 465 .name = "mas_anoc_snoc", 466 .buswidth = 16, 467 .mas_rpm_id = 110, 468 .slv_rpm_id = -1, 469 .num_links = ARRAY_SIZE(mas_anoc_snoc_links), 470 .links = mas_anoc_snoc_links, 471 }; 472 473 static const u16 mas_bimc_snoc_links[] = { 474 QCM2290_SLAVE_PIMEM, 475 QCM2290_SLAVE_IMEM, 476 QCM2290_SLAVE_APPSS, 477 QCM2290_SLAVE_SNOC_CNOC, 478 QCM2290_SLAVE_TCU, 479 QCM2290_SLAVE_QDSS_STM, 480 }; 481 482 static struct qcom_icc_node mas_bimc_snoc = { 483 .id = QCM2290_MASTER_BIMC_SNOC, 484 .name = "mas_bimc_snoc", 485 .buswidth = 8, 486 .mas_rpm_id = 21, 487 .slv_rpm_id = -1, 488 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 489 .links = mas_bimc_snoc_links, 490 }; 491 492 static const u16 mas_pimem_links[] = { 493 QCM2290_SLAVE_IMEM, 494 QCM2290_SLAVE_SNOC_BIMC, 495 }; 496 497 static struct qcom_icc_node mas_pimem = { 498 .id = QCM2290_MASTER_PIMEM, 499 .name = "mas_pimem", 500 .buswidth = 8, 501 .qos.ap_owned = true, 502 .qos.qos_port = 20, 503 .qos.qos_mode = NOC_QOS_MODE_FIXED, 504 .qos.areq_prio = 2, 505 .mas_rpm_id = 113, 506 .slv_rpm_id = -1, 507 .num_links = ARRAY_SIZE(mas_pimem_links), 508 .links = mas_pimem_links, 509 }; 510 511 static const u16 mas_qdss_bam_links[] = { 512 QCM2290_SLAVE_ANOC_SNOC, 513 }; 514 515 static struct qcom_icc_node mas_qdss_bam = { 516 .id = QCM2290_MASTER_QDSS_BAM, 517 .name = "mas_qdss_bam", 518 .buswidth = 4, 519 .qos.ap_owned = true, 520 .qos.qos_port = 2, 521 .qos.qos_mode = NOC_QOS_MODE_FIXED, 522 .qos.areq_prio = 2, 523 .mas_rpm_id = 19, 524 .slv_rpm_id = -1, 525 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 526 .links = mas_qdss_bam_links, 527 }; 528 529 static const u16 mas_qup_0_links[] = { 530 QCM2290_SLAVE_ANOC_SNOC, 531 }; 532 533 static struct qcom_icc_node mas_qup_0 = { 534 .id = QCM2290_MASTER_QUP_0, 535 .name = "mas_qup_0", 536 .buswidth = 4, 537 .qos.ap_owned = true, 538 .qos.qos_port = 0, 539 .qos.qos_mode = NOC_QOS_MODE_FIXED, 540 .qos.areq_prio = 2, 541 .mas_rpm_id = 166, 542 .slv_rpm_id = -1, 543 .num_links = ARRAY_SIZE(mas_qup_0_links), 544 .links = mas_qup_0_links, 545 }; 546 547 static const u16 mas_ipa_links[] = { 548 QCM2290_SLAVE_ANOC_SNOC, 549 }; 550 551 static struct qcom_icc_node mas_ipa = { 552 .id = QCM2290_MASTER_IPA, 553 .name = "mas_ipa", 554 .buswidth = 8, 555 .qos.ap_owned = true, 556 .qos.qos_port = 3, 557 .qos.qos_mode = NOC_QOS_MODE_FIXED, 558 .qos.areq_prio = 2, 559 .mas_rpm_id = 59, 560 .slv_rpm_id = -1, 561 .num_links = ARRAY_SIZE(mas_ipa_links), 562 .links = mas_ipa_links, 563 }; 564 565 static const u16 mas_qdss_etr_links[] = { 566 QCM2290_SLAVE_ANOC_SNOC, 567 }; 568 569 static struct qcom_icc_node mas_qdss_etr = { 570 .id = QCM2290_MASTER_QDSS_ETR, 571 .name = "mas_qdss_etr", 572 .buswidth = 8, 573 .qos.ap_owned = true, 574 .qos.qos_port = 12, 575 .qos.qos_mode = NOC_QOS_MODE_FIXED, 576 .qos.areq_prio = 2, 577 .mas_rpm_id = 31, 578 .slv_rpm_id = -1, 579 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 580 .links = mas_qdss_etr_links, 581 }; 582 583 static const u16 mas_sdcc_1_links[] = { 584 QCM2290_SLAVE_ANOC_SNOC, 585 }; 586 587 static struct qcom_icc_node mas_sdcc_1 = { 588 .id = QCM2290_MASTER_SDCC_1, 589 .name = "mas_sdcc_1", 590 .buswidth = 8, 591 .qos.ap_owned = true, 592 .qos.qos_port = 17, 593 .qos.qos_mode = NOC_QOS_MODE_FIXED, 594 .qos.areq_prio = 2, 595 .mas_rpm_id = 33, 596 .slv_rpm_id = -1, 597 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 598 .links = mas_sdcc_1_links, 599 }; 600 601 static const u16 mas_sdcc_2_links[] = { 602 QCM2290_SLAVE_ANOC_SNOC, 603 }; 604 605 static struct qcom_icc_node mas_sdcc_2 = { 606 .id = QCM2290_MASTER_SDCC_2, 607 .name = "mas_sdcc_2", 608 .buswidth = 8, 609 .qos.ap_owned = true, 610 .qos.qos_port = 23, 611 .qos.qos_mode = NOC_QOS_MODE_FIXED, 612 .qos.areq_prio = 2, 613 .mas_rpm_id = 35, 614 .slv_rpm_id = -1, 615 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 616 .links = mas_sdcc_2_links, 617 }; 618 619 static const u16 mas_qpic_links[] = { 620 QCM2290_SLAVE_ANOC_SNOC, 621 }; 622 623 static struct qcom_icc_node mas_qpic = { 624 .id = QCM2290_MASTER_QPIC, 625 .name = "mas_qpic", 626 .buswidth = 4, 627 .qos.ap_owned = true, 628 .qos.qos_port = 1, 629 .qos.qos_mode = NOC_QOS_MODE_FIXED, 630 .qos.areq_prio = 2, 631 .mas_rpm_id = 58, 632 .slv_rpm_id = -1, 633 .num_links = ARRAY_SIZE(mas_qpic_links), 634 .links = mas_qpic_links, 635 }; 636 637 static const u16 mas_usb3_0_links[] = { 638 QCM2290_SLAVE_ANOC_SNOC, 639 }; 640 641 static struct qcom_icc_node mas_usb3_0 = { 642 .id = QCM2290_MASTER_USB3_0, 643 .name = "mas_usb3_0", 644 .buswidth = 8, 645 .qos.ap_owned = true, 646 .qos.qos_port = 24, 647 .qos.qos_mode = NOC_QOS_MODE_FIXED, 648 .qos.areq_prio = 2, 649 .mas_rpm_id = 32, 650 .slv_rpm_id = -1, 651 .num_links = ARRAY_SIZE(mas_usb3_0_links), 652 .links = mas_usb3_0_links, 653 }; 654 655 static const u16 mas_gfx3d_links[] = { 656 QCM2290_SLAVE_EBI1, 657 }; 658 659 static struct qcom_icc_node mas_gfx3d = { 660 .id = QCM2290_MASTER_GFX3D, 661 .name = "mas_gfx3d", 662 .buswidth = 32, 663 .qos.ap_owned = true, 664 .qos.qos_port = 1, 665 .qos.qos_mode = NOC_QOS_MODE_FIXED, 666 .qos.prio_level = 0, 667 .qos.areq_prio = 0, 668 .mas_rpm_id = 6, 669 .slv_rpm_id = -1, 670 .num_links = ARRAY_SIZE(mas_gfx3d_links), 671 .links = mas_gfx3d_links, 672 }; 673 674 /* Slave nodes */ 675 static struct qcom_icc_node slv_ebi1 = { 676 .name = "slv_ebi1", 677 .id = QCM2290_SLAVE_EBI1, 678 .buswidth = 8, 679 .mas_rpm_id = -1, 680 .slv_rpm_id = 0, 681 }; 682 683 static const u16 slv_bimc_snoc_links[] = { 684 QCM2290_MASTER_BIMC_SNOC, 685 }; 686 687 static struct qcom_icc_node slv_bimc_snoc = { 688 .name = "slv_bimc_snoc", 689 .id = QCM2290_SLAVE_BIMC_SNOC, 690 .buswidth = 8, 691 .mas_rpm_id = -1, 692 .slv_rpm_id = 2, 693 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 694 .links = slv_bimc_snoc_links, 695 }; 696 697 static struct qcom_icc_node slv_bimc_cfg = { 698 .name = "slv_bimc_cfg", 699 .id = QCM2290_SLAVE_BIMC_CFG, 700 .buswidth = 4, 701 .qos.ap_owned = true, 702 .qos.qos_mode = NOC_QOS_MODE_INVALID, 703 .mas_rpm_id = -1, 704 .slv_rpm_id = 56, 705 }; 706 707 static struct qcom_icc_node slv_camera_nrt_throttle_cfg = { 708 .name = "slv_camera_nrt_throttle_cfg", 709 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 710 .buswidth = 4, 711 .qos.ap_owned = true, 712 .qos.qos_mode = NOC_QOS_MODE_INVALID, 713 .mas_rpm_id = -1, 714 .slv_rpm_id = 271, 715 }; 716 717 static struct qcom_icc_node slv_camera_rt_throttle_cfg = { 718 .name = "slv_camera_rt_throttle_cfg", 719 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 720 .buswidth = 4, 721 .qos.ap_owned = true, 722 .qos.qos_mode = NOC_QOS_MODE_INVALID, 723 .mas_rpm_id = -1, 724 .slv_rpm_id = 279, 725 }; 726 727 static struct qcom_icc_node slv_camera_cfg = { 728 .name = "slv_camera_cfg", 729 .id = QCM2290_SLAVE_CAMERA_CFG, 730 .buswidth = 4, 731 .qos.ap_owned = true, 732 .qos.qos_mode = NOC_QOS_MODE_INVALID, 733 .mas_rpm_id = -1, 734 .slv_rpm_id = 3, 735 }; 736 737 static struct qcom_icc_node slv_clk_ctl = { 738 .name = "slv_clk_ctl", 739 .id = QCM2290_SLAVE_CLK_CTL, 740 .buswidth = 4, 741 .qos.ap_owned = true, 742 .qos.qos_mode = NOC_QOS_MODE_INVALID, 743 .mas_rpm_id = -1, 744 .slv_rpm_id = 47, 745 }; 746 747 static struct qcom_icc_node slv_crypto_0_cfg = { 748 .name = "slv_crypto_0_cfg", 749 .id = QCM2290_SLAVE_CRYPTO_0_CFG, 750 .buswidth = 4, 751 .qos.ap_owned = true, 752 .qos.qos_mode = NOC_QOS_MODE_INVALID, 753 .mas_rpm_id = -1, 754 .slv_rpm_id = 52, 755 }; 756 757 static struct qcom_icc_node slv_display_cfg = { 758 .name = "slv_display_cfg", 759 .id = QCM2290_SLAVE_DISPLAY_CFG, 760 .buswidth = 4, 761 .qos.ap_owned = true, 762 .qos.qos_mode = NOC_QOS_MODE_INVALID, 763 .mas_rpm_id = -1, 764 .slv_rpm_id = 4, 765 }; 766 767 static struct qcom_icc_node slv_display_throttle_cfg = { 768 .name = "slv_display_throttle_cfg", 769 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 770 .buswidth = 4, 771 .qos.ap_owned = true, 772 .qos.qos_mode = NOC_QOS_MODE_INVALID, 773 .mas_rpm_id = -1, 774 .slv_rpm_id = 156, 775 }; 776 777 static struct qcom_icc_node slv_gpu_cfg = { 778 .name = "slv_gpu_cfg", 779 .id = QCM2290_SLAVE_GPU_CFG, 780 .buswidth = 8, 781 .qos.ap_owned = true, 782 .qos.qos_mode = NOC_QOS_MODE_INVALID, 783 .mas_rpm_id = -1, 784 .slv_rpm_id = 275, 785 }; 786 787 static struct qcom_icc_node slv_hwkm = { 788 .name = "slv_hwkm", 789 .id = QCM2290_SLAVE_HWKM, 790 .buswidth = 4, 791 .qos.ap_owned = true, 792 .qos.qos_mode = NOC_QOS_MODE_INVALID, 793 .mas_rpm_id = -1, 794 .slv_rpm_id = 280, 795 }; 796 797 static struct qcom_icc_node slv_imem_cfg = { 798 .name = "slv_imem_cfg", 799 .id = QCM2290_SLAVE_IMEM_CFG, 800 .buswidth = 4, 801 .qos.ap_owned = true, 802 .qos.qos_mode = NOC_QOS_MODE_INVALID, 803 .mas_rpm_id = -1, 804 .slv_rpm_id = 54, 805 }; 806 807 static struct qcom_icc_node slv_ipa_cfg = { 808 .name = "slv_ipa_cfg", 809 .id = QCM2290_SLAVE_IPA_CFG, 810 .buswidth = 4, 811 .qos.ap_owned = true, 812 .qos.qos_mode = NOC_QOS_MODE_INVALID, 813 .mas_rpm_id = -1, 814 .slv_rpm_id = 183, 815 }; 816 817 static struct qcom_icc_node slv_lpass = { 818 .name = "slv_lpass", 819 .id = QCM2290_SLAVE_LPASS, 820 .buswidth = 4, 821 .qos.ap_owned = true, 822 .qos.qos_mode = NOC_QOS_MODE_INVALID, 823 .mas_rpm_id = -1, 824 .slv_rpm_id = 21, 825 }; 826 827 static struct qcom_icc_node slv_message_ram = { 828 .name = "slv_message_ram", 829 .id = QCM2290_SLAVE_MESSAGE_RAM, 830 .buswidth = 4, 831 .qos.ap_owned = true, 832 .qos.qos_mode = NOC_QOS_MODE_INVALID, 833 .mas_rpm_id = -1, 834 .slv_rpm_id = 55, 835 }; 836 837 static struct qcom_icc_node slv_pdm = { 838 .name = "slv_pdm", 839 .id = QCM2290_SLAVE_PDM, 840 .buswidth = 4, 841 .qos.ap_owned = true, 842 .qos.qos_mode = NOC_QOS_MODE_INVALID, 843 .mas_rpm_id = -1, 844 .slv_rpm_id = 41, 845 }; 846 847 static struct qcom_icc_node slv_pimem_cfg = { 848 .name = "slv_pimem_cfg", 849 .id = QCM2290_SLAVE_PIMEM_CFG, 850 .buswidth = 4, 851 .qos.ap_owned = true, 852 .qos.qos_mode = NOC_QOS_MODE_INVALID, 853 .mas_rpm_id = -1, 854 .slv_rpm_id = 167, 855 }; 856 857 static struct qcom_icc_node slv_pka_wrapper = { 858 .name = "slv_pka_wrapper", 859 .id = QCM2290_SLAVE_PKA_WRAPPER, 860 .buswidth = 4, 861 .qos.ap_owned = true, 862 .qos.qos_mode = NOC_QOS_MODE_INVALID, 863 .mas_rpm_id = -1, 864 .slv_rpm_id = 281, 865 }; 866 867 static struct qcom_icc_node slv_pmic_arb = { 868 .name = "slv_pmic_arb", 869 .id = QCM2290_SLAVE_PMIC_ARB, 870 .buswidth = 4, 871 .qos.ap_owned = true, 872 .qos.qos_mode = NOC_QOS_MODE_INVALID, 873 .mas_rpm_id = -1, 874 .slv_rpm_id = 59, 875 }; 876 877 static struct qcom_icc_node slv_prng = { 878 .name = "slv_prng", 879 .id = QCM2290_SLAVE_PRNG, 880 .buswidth = 4, 881 .qos.ap_owned = true, 882 .qos.qos_mode = NOC_QOS_MODE_INVALID, 883 .mas_rpm_id = -1, 884 .slv_rpm_id = 44, 885 }; 886 887 static struct qcom_icc_node slv_qdss_cfg = { 888 .name = "slv_qdss_cfg", 889 .id = QCM2290_SLAVE_QDSS_CFG, 890 .buswidth = 4, 891 .qos.ap_owned = true, 892 .qos.qos_mode = NOC_QOS_MODE_INVALID, 893 .mas_rpm_id = -1, 894 .slv_rpm_id = 63, 895 }; 896 897 static struct qcom_icc_node slv_qm_cfg = { 898 .name = "slv_qm_cfg", 899 .id = QCM2290_SLAVE_QM_CFG, 900 .buswidth = 4, 901 .qos.ap_owned = true, 902 .qos.qos_mode = NOC_QOS_MODE_INVALID, 903 .mas_rpm_id = -1, 904 .slv_rpm_id = 212, 905 }; 906 907 static struct qcom_icc_node slv_qm_mpu_cfg = { 908 .name = "slv_qm_mpu_cfg", 909 .id = QCM2290_SLAVE_QM_MPU_CFG, 910 .buswidth = 4, 911 .qos.ap_owned = true, 912 .qos.qos_mode = NOC_QOS_MODE_INVALID, 913 .mas_rpm_id = -1, 914 .slv_rpm_id = 231, 915 }; 916 917 static struct qcom_icc_node slv_qpic = { 918 .name = "slv_qpic", 919 .id = QCM2290_SLAVE_QPIC, 920 .buswidth = 4, 921 .qos.ap_owned = true, 922 .qos.qos_mode = NOC_QOS_MODE_INVALID, 923 .mas_rpm_id = -1, 924 .slv_rpm_id = 80, 925 }; 926 927 static struct qcom_icc_node slv_qup_0 = { 928 .name = "slv_qup_0", 929 .id = QCM2290_SLAVE_QUP_0, 930 .buswidth = 4, 931 .qos.ap_owned = true, 932 .qos.qos_mode = NOC_QOS_MODE_INVALID, 933 .mas_rpm_id = -1, 934 .slv_rpm_id = 261, 935 }; 936 937 static struct qcom_icc_node slv_sdcc_1 = { 938 .name = "slv_sdcc_1", 939 .id = QCM2290_SLAVE_SDCC_1, 940 .buswidth = 4, 941 .qos.ap_owned = true, 942 .qos.qos_mode = NOC_QOS_MODE_INVALID, 943 .mas_rpm_id = -1, 944 .slv_rpm_id = 31, 945 }; 946 947 static struct qcom_icc_node slv_sdcc_2 = { 948 .name = "slv_sdcc_2", 949 .id = QCM2290_SLAVE_SDCC_2, 950 .buswidth = 4, 951 .qos.ap_owned = true, 952 .qos.qos_mode = NOC_QOS_MODE_INVALID, 953 .mas_rpm_id = -1, 954 .slv_rpm_id = 33, 955 }; 956 957 static const u16 slv_snoc_cfg_links[] = { 958 QCM2290_MASTER_SNOC_CFG, 959 }; 960 961 static struct qcom_icc_node slv_snoc_cfg = { 962 .name = "slv_snoc_cfg", 963 .id = QCM2290_SLAVE_SNOC_CFG, 964 .buswidth = 4, 965 .qos.ap_owned = true, 966 .qos.qos_mode = NOC_QOS_MODE_INVALID, 967 .mas_rpm_id = -1, 968 .slv_rpm_id = 70, 969 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 970 .links = slv_snoc_cfg_links, 971 }; 972 973 static struct qcom_icc_node slv_tcsr = { 974 .name = "slv_tcsr", 975 .id = QCM2290_SLAVE_TCSR, 976 .buswidth = 4, 977 .qos.ap_owned = true, 978 .qos.qos_mode = NOC_QOS_MODE_INVALID, 979 .mas_rpm_id = -1, 980 .slv_rpm_id = 50, 981 }; 982 983 static struct qcom_icc_node slv_usb3 = { 984 .name = "slv_usb3", 985 .id = QCM2290_SLAVE_USB3, 986 .buswidth = 4, 987 .qos.ap_owned = true, 988 .qos.qos_mode = NOC_QOS_MODE_INVALID, 989 .mas_rpm_id = -1, 990 .slv_rpm_id = 22, 991 }; 992 993 static struct qcom_icc_node slv_venus_cfg = { 994 .name = "slv_venus_cfg", 995 .id = QCM2290_SLAVE_VENUS_CFG, 996 .buswidth = 4, 997 .qos.ap_owned = true, 998 .qos.qos_mode = NOC_QOS_MODE_INVALID, 999 .mas_rpm_id = -1, 1000 .slv_rpm_id = 10, 1001 }; 1002 1003 static struct qcom_icc_node slv_venus_throttle_cfg = { 1004 .name = "slv_venus_throttle_cfg", 1005 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG, 1006 .buswidth = 4, 1007 .qos.ap_owned = true, 1008 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1009 .mas_rpm_id = -1, 1010 .slv_rpm_id = 178, 1011 }; 1012 1013 static struct qcom_icc_node slv_vsense_ctrl_cfg = { 1014 .name = "slv_vsense_ctrl_cfg", 1015 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG, 1016 .buswidth = 4, 1017 .qos.ap_owned = true, 1018 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1019 .mas_rpm_id = -1, 1020 .slv_rpm_id = 263, 1021 }; 1022 1023 static struct qcom_icc_node slv_service_cnoc = { 1024 .name = "slv_service_cnoc", 1025 .id = QCM2290_SLAVE_SERVICE_CNOC, 1026 .buswidth = 4, 1027 .qos.ap_owned = true, 1028 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1029 .mas_rpm_id = -1, 1030 .slv_rpm_id = 76, 1031 }; 1032 1033 static struct qcom_icc_node slv_qup_core_0 = { 1034 .name = "slv_qup_core_0", 1035 .id = QCM2290_SLAVE_QUP_CORE_0, 1036 .buswidth = 4, 1037 .qos.ap_owned = true, 1038 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1039 .mas_rpm_id = -1, 1040 .slv_rpm_id = 264, 1041 }; 1042 1043 static const u16 slv_snoc_bimc_nrt_links[] = { 1044 QCM2290_MASTER_SNOC_BIMC_NRT, 1045 }; 1046 1047 static struct qcom_icc_node slv_snoc_bimc_nrt = { 1048 .name = "slv_snoc_bimc_nrt", 1049 .id = QCM2290_SLAVE_SNOC_BIMC_NRT, 1050 .buswidth = 16, 1051 .qos.ap_owned = true, 1052 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1053 .mas_rpm_id = -1, 1054 .slv_rpm_id = 259, 1055 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1056 .links = slv_snoc_bimc_nrt_links, 1057 }; 1058 1059 static const u16 slv_snoc_bimc_rt_links[] = { 1060 QCM2290_MASTER_SNOC_BIMC_RT, 1061 }; 1062 1063 static struct qcom_icc_node slv_snoc_bimc_rt = { 1064 .name = "slv_snoc_bimc_rt", 1065 .id = QCM2290_SLAVE_SNOC_BIMC_RT, 1066 .buswidth = 16, 1067 .qos.ap_owned = true, 1068 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1069 .mas_rpm_id = -1, 1070 .slv_rpm_id = 260, 1071 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1072 .links = slv_snoc_bimc_rt_links, 1073 }; 1074 1075 static struct qcom_icc_node slv_appss = { 1076 .name = "slv_appss", 1077 .id = QCM2290_SLAVE_APPSS, 1078 .buswidth = 8, 1079 .qos.ap_owned = true, 1080 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1081 .mas_rpm_id = -1, 1082 .slv_rpm_id = 20, 1083 }; 1084 1085 static const u16 slv_snoc_cnoc_links[] = { 1086 QCM2290_MASTER_SNOC_CNOC, 1087 }; 1088 1089 static struct qcom_icc_node slv_snoc_cnoc = { 1090 .name = "slv_snoc_cnoc", 1091 .id = QCM2290_SLAVE_SNOC_CNOC, 1092 .buswidth = 8, 1093 .mas_rpm_id = -1, 1094 .slv_rpm_id = 25, 1095 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1096 .links = slv_snoc_cnoc_links, 1097 }; 1098 1099 static struct qcom_icc_node slv_imem = { 1100 .name = "slv_imem", 1101 .id = QCM2290_SLAVE_IMEM, 1102 .buswidth = 8, 1103 .mas_rpm_id = -1, 1104 .slv_rpm_id = 26, 1105 }; 1106 1107 static struct qcom_icc_node slv_pimem = { 1108 .name = "slv_pimem", 1109 .id = QCM2290_SLAVE_PIMEM, 1110 .buswidth = 8, 1111 .qos.ap_owned = true, 1112 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1113 .mas_rpm_id = -1, 1114 .slv_rpm_id = 166, 1115 }; 1116 1117 static const u16 slv_snoc_bimc_links[] = { 1118 QCM2290_MASTER_SNOC_BIMC, 1119 }; 1120 1121 static struct qcom_icc_node slv_snoc_bimc = { 1122 .name = "slv_snoc_bimc", 1123 .id = QCM2290_SLAVE_SNOC_BIMC, 1124 .buswidth = 16, 1125 .mas_rpm_id = -1, 1126 .slv_rpm_id = 24, 1127 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1128 .links = slv_snoc_bimc_links, 1129 }; 1130 1131 static struct qcom_icc_node slv_service_snoc = { 1132 .name = "slv_service_snoc", 1133 .id = QCM2290_SLAVE_SERVICE_SNOC, 1134 .buswidth = 4, 1135 .qos.ap_owned = true, 1136 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1137 .mas_rpm_id = -1, 1138 .slv_rpm_id = 29, 1139 }; 1140 1141 static struct qcom_icc_node slv_qdss_stm = { 1142 .name = "slv_qdss_stm", 1143 .id = QCM2290_SLAVE_QDSS_STM, 1144 .buswidth = 4, 1145 .mas_rpm_id = -1, 1146 .slv_rpm_id = 30, 1147 }; 1148 1149 static struct qcom_icc_node slv_tcu = { 1150 .name = "slv_tcu", 1151 .id = QCM2290_SLAVE_TCU, 1152 .buswidth = 8, 1153 .qos.ap_owned = true, 1154 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1155 .mas_rpm_id = -1, 1156 .slv_rpm_id = 133, 1157 }; 1158 1159 static const u16 slv_anoc_snoc_links[] = { 1160 QCM2290_MASTER_ANOC_SNOC, 1161 }; 1162 1163 static struct qcom_icc_node slv_anoc_snoc = { 1164 .name = "slv_anoc_snoc", 1165 .id = QCM2290_SLAVE_ANOC_SNOC, 1166 .buswidth = 16, 1167 .mas_rpm_id = -1, 1168 .slv_rpm_id = 141, 1169 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1170 .links = slv_anoc_snoc_links, 1171 }; 1172 1173 /* NoC descriptors */ 1174 static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { 1175 [MASTER_APPSS_PROC] = &mas_appss_proc, 1176 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1177 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1178 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1179 [MASTER_TCU_0] = &mas_tcu_0, 1180 [MASTER_GFX3D] = &mas_gfx3d, 1181 [SLAVE_EBI1] = &slv_ebi1, 1182 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1183 }; 1184 1185 static const struct regmap_config qcm2290_bimc_regmap_config = { 1186 .reg_bits = 32, 1187 .reg_stride = 4, 1188 .val_bits = 32, 1189 .max_register = 0x80000, 1190 .fast_io = true, 1191 }; 1192 1193 static const struct qcom_icc_desc qcm2290_bimc = { 1194 .type = QCOM_ICC_BIMC, 1195 .nodes = qcm2290_bimc_nodes, 1196 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), 1197 .bus_clk_desc = &bimc_clk, 1198 .regmap_cfg = &qcm2290_bimc_regmap_config, 1199 .keep_alive = true, 1200 /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ 1201 .qos_offset = 0x8000, 1202 }; 1203 1204 static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { 1205 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1206 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1207 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1208 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg, 1209 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg, 1210 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1211 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1212 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1213 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1214 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1215 [SLAVE_GPU_CFG] = &slv_gpu_cfg, 1216 [SLAVE_HWKM] = &slv_hwkm, 1217 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1218 [SLAVE_IPA_CFG] = &slv_ipa_cfg, 1219 [SLAVE_LPASS] = &slv_lpass, 1220 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1221 [SLAVE_PDM] = &slv_pdm, 1222 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1223 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper, 1224 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1225 [SLAVE_PRNG] = &slv_prng, 1226 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1227 [SLAVE_QM_CFG] = &slv_qm_cfg, 1228 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg, 1229 [SLAVE_QPIC] = &slv_qpic, 1230 [SLAVE_QUP_0] = &slv_qup_0, 1231 [SLAVE_SDCC_1] = &slv_sdcc_1, 1232 [SLAVE_SDCC_2] = &slv_sdcc_2, 1233 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1234 [SLAVE_TCSR] = &slv_tcsr, 1235 [SLAVE_USB3] = &slv_usb3, 1236 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1237 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1238 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg, 1239 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc, 1240 }; 1241 1242 static const struct regmap_config qcm2290_cnoc_regmap_config = { 1243 .reg_bits = 32, 1244 .reg_stride = 4, 1245 .val_bits = 32, 1246 .max_register = 0x8200, 1247 .fast_io = true, 1248 }; 1249 1250 static const struct qcom_icc_desc qcm2290_cnoc = { 1251 .type = QCOM_ICC_NOC, 1252 .nodes = qcm2290_cnoc_nodes, 1253 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), 1254 .bus_clk_desc = &bus_1_clk, 1255 .regmap_cfg = &qcm2290_cnoc_regmap_config, 1256 .keep_alive = true, 1257 }; 1258 1259 static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { 1260 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, 1261 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1262 [MASTER_TIC] = &mas_tic, 1263 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1264 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1265 [MASTER_PIMEM] = &mas_pimem, 1266 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1267 [MASTER_QUP_0] = &mas_qup_0, 1268 [MASTER_IPA] = &mas_ipa, 1269 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1270 [MASTER_SDCC_1] = &mas_sdcc_1, 1271 [MASTER_SDCC_2] = &mas_sdcc_2, 1272 [MASTER_QPIC] = &mas_qpic, 1273 [MASTER_USB3_0] = &mas_usb3_0, 1274 [SLAVE_APPSS] = &slv_appss, 1275 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1276 [SLAVE_IMEM] = &slv_imem, 1277 [SLAVE_PIMEM] = &slv_pimem, 1278 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1279 [SLAVE_SERVICE_SNOC] = &slv_service_snoc, 1280 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1281 [SLAVE_TCU] = &slv_tcu, 1282 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1283 }; 1284 1285 static const struct regmap_config qcm2290_snoc_regmap_config = { 1286 .reg_bits = 32, 1287 .reg_stride = 4, 1288 .val_bits = 32, 1289 .max_register = 0x60200, 1290 .fast_io = true, 1291 }; 1292 1293 static const struct qcom_icc_desc qcm2290_snoc = { 1294 .type = QCOM_ICC_QNOC, 1295 .nodes = qcm2290_snoc_nodes, 1296 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), 1297 .bus_clk_desc = &bus_2_clk, 1298 .regmap_cfg = &qcm2290_snoc_regmap_config, 1299 .keep_alive = true, 1300 /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ 1301 .qos_offset = 0x15000, 1302 }; 1303 1304 static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { 1305 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1306 [SLAVE_QUP_CORE_0] = &slv_qup_core_0 1307 }; 1308 1309 static const struct qcom_icc_desc qcm2290_qup_virt = { 1310 .type = QCOM_ICC_QNOC, 1311 .nodes = qcm2290_qup_virt_nodes, 1312 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), 1313 .bus_clk_desc = &qup_clk, 1314 .keep_alive = true, 1315 }; 1316 1317 static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { 1318 [MASTER_CAMNOC_SF] = &mas_camnoc_sf, 1319 [MASTER_VIDEO_P0] = &mas_video_p0, 1320 [MASTER_VIDEO_PROC] = &mas_video_proc, 1321 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1322 }; 1323 1324 static const struct qcom_icc_desc qcm2290_mmnrt_virt = { 1325 .type = QCOM_ICC_QNOC, 1326 .nodes = qcm2290_mmnrt_virt_nodes, 1327 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), 1328 .bus_clk_desc = &mmaxi_0_clk, 1329 .regmap_cfg = &qcm2290_snoc_regmap_config, 1330 .keep_alive = true, 1331 .qos_offset = 0x15000, 1332 }; 1333 1334 static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { 1335 [MASTER_CAMNOC_HF] = &mas_camnoc_hf, 1336 [MASTER_MDP0] = &mas_mdp0, 1337 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1338 }; 1339 1340 static const struct qcom_icc_desc qcm2290_mmrt_virt = { 1341 .type = QCOM_ICC_QNOC, 1342 .nodes = qcm2290_mmrt_virt_nodes, 1343 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), 1344 .bus_clk_desc = &mmaxi_1_clk, 1345 .regmap_cfg = &qcm2290_snoc_regmap_config, 1346 .keep_alive = true, 1347 .qos_offset = 0x15000, 1348 }; 1349 1350 static const struct of_device_id qcm2290_noc_of_match[] = { 1351 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc }, 1352 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc }, 1353 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc }, 1354 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt }, 1355 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt }, 1356 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt }, 1357 { }, 1358 }; 1359 MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); 1360 1361 static struct platform_driver qcm2290_noc_driver = { 1362 .probe = qnoc_probe, 1363 .remove = qnoc_remove, 1364 .driver = { 1365 .name = "qnoc-qcm2290", 1366 .of_match_table = qcm2290_noc_of_match, 1367 .sync_state = icc_sync_state, 1368 }, 1369 }; 1370 module_platform_driver(qcm2290_noc_driver); 1371 1372 MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver"); 1373 MODULE_LICENSE("GPL v2"); 1374