xref: /openbmc/linux/drivers/input/mouse/cyapa.h (revision 3cd47869)
1 /*
2  * Cypress APA trackpad with I2C interface
3  *
4  * Author: Dudley Du <dudl@cypress.com>
5  *
6  * Copyright (C) 2014-2015 Cypress Semiconductor, Inc.
7  *
8  * This file is subject to the terms and conditions of the GNU General Public
9  * License.  See the file COPYING in the main directory of this archive for
10  * more details.
11  */
12 
13 #ifndef _CYAPA_H
14 #define _CYAPA_H
15 
16 #include <linux/firmware.h>
17 
18 /* APA trackpad firmware generation number. */
19 #define CYAPA_GEN_UNKNOWN   0x00   /* unknown protocol. */
20 #define CYAPA_GEN3   0x03   /* support MT-protocol B with tracking ID. */
21 #define CYAPA_GEN5   0x05   /* support TrueTouch GEN5 trackpad device. */
22 #define CYAPA_GEN6   0x06   /* support TrueTouch GEN6 trackpad device. */
23 
24 #define CYAPA_NAME   "Cypress APA Trackpad (cyapa)"
25 
26 /*
27  * Macros for SMBus communication
28  */
29 #define SMBUS_READ  0x01
30 #define SMBUS_WRITE 0x00
31 #define SMBUS_ENCODE_IDX(cmd, idx) ((cmd) | (((idx) & 0x03) << 1))
32 #define SMBUS_ENCODE_RW(cmd, rw) ((cmd) | ((rw) & 0x01))
33 #define SMBUS_BYTE_BLOCK_CMD_MASK 0x80
34 #define SMBUS_GROUP_BLOCK_CMD_MASK 0x40
35 
36 /* Commands for read/write registers of Cypress trackpad */
37 #define CYAPA_CMD_SOFT_RESET       0x00
38 #define CYAPA_CMD_POWER_MODE       0x01
39 #define CYAPA_CMD_DEV_STATUS       0x02
40 #define CYAPA_CMD_GROUP_DATA       0x03
41 #define CYAPA_CMD_GROUP_CMD        0x04
42 #define CYAPA_CMD_GROUP_QUERY      0x05
43 #define CYAPA_CMD_BL_STATUS        0x06
44 #define CYAPA_CMD_BL_HEAD          0x07
45 #define CYAPA_CMD_BL_CMD           0x08
46 #define CYAPA_CMD_BL_DATA          0x09
47 #define CYAPA_CMD_BL_ALL           0x0a
48 #define CYAPA_CMD_BLK_PRODUCT_ID   0x0b
49 #define CYAPA_CMD_BLK_HEAD         0x0c
50 #define CYAPA_CMD_MAX_BASELINE     0x0d
51 #define CYAPA_CMD_MIN_BASELINE     0x0e
52 
53 #define BL_HEAD_OFFSET 0x00
54 #define BL_DATA_OFFSET 0x10
55 
56 #define BL_STATUS_SIZE  3  /* Length of gen3 bootloader status registers */
57 #define CYAPA_REG_MAP_SIZE  256
58 
59 /*
60  * Gen3 Operational Device Status Register
61  *
62  * bit 7: Valid interrupt source
63  * bit 6 - 4: Reserved
64  * bit 3 - 2: Power status
65  * bit 1 - 0: Device status
66  */
67 #define REG_OP_STATUS     0x00
68 #define OP_STATUS_SRC     0x80
69 #define OP_STATUS_POWER   0x0c
70 #define OP_STATUS_DEV     0x03
71 #define OP_STATUS_MASK (OP_STATUS_SRC | OP_STATUS_POWER | OP_STATUS_DEV)
72 
73 /*
74  * Operational Finger Count/Button Flags Register
75  *
76  * bit 7 - 4: Number of touched finger
77  * bit 3: Valid data
78  * bit 2: Middle Physical Button
79  * bit 1: Right Physical Button
80  * bit 0: Left physical Button
81  */
82 #define REG_OP_DATA1       0x01
83 #define OP_DATA_VALID      0x08
84 #define OP_DATA_MIDDLE_BTN 0x04
85 #define OP_DATA_RIGHT_BTN  0x02
86 #define OP_DATA_LEFT_BTN   0x01
87 #define OP_DATA_BTN_MASK (OP_DATA_MIDDLE_BTN | OP_DATA_RIGHT_BTN | \
88 			  OP_DATA_LEFT_BTN)
89 
90 /*
91  * Write-only command file register used to issue commands and
92  * parameters to the bootloader.
93  * The default value read from it is always 0x00.
94  */
95 #define REG_BL_FILE	0x00
96 #define BL_FILE		0x00
97 
98 /*
99  * Bootloader Status Register
100  *
101  * bit 7: Busy
102  * bit 6 - 5: Reserved
103  * bit 4: Bootloader running
104  * bit 3 - 2: Reserved
105  * bit 1: Watchdog Reset
106  * bit 0: Checksum valid
107  */
108 #define REG_BL_STATUS        0x01
109 #define BL_STATUS_REV_6_5    0x60
110 #define BL_STATUS_BUSY       0x80
111 #define BL_STATUS_RUNNING    0x10
112 #define BL_STATUS_REV_3_2    0x0c
113 #define BL_STATUS_WATCHDOG   0x02
114 #define BL_STATUS_CSUM_VALID 0x01
115 #define BL_STATUS_REV_MASK (BL_STATUS_WATCHDOG | BL_STATUS_REV_3_2 | \
116 			    BL_STATUS_REV_6_5)
117 
118 /*
119  * Bootloader Error Register
120  *
121  * bit 7: Invalid
122  * bit 6: Invalid security key
123  * bit 5: Bootloading
124  * bit 4: Command checksum
125  * bit 3: Flash protection error
126  * bit 2: Flash checksum error
127  * bit 1 - 0: Reserved
128  */
129 #define REG_BL_ERROR         0x02
130 #define BL_ERROR_INVALID     0x80
131 #define BL_ERROR_INVALID_KEY 0x40
132 #define BL_ERROR_BOOTLOADING 0x20
133 #define BL_ERROR_CMD_CSUM    0x10
134 #define BL_ERROR_FLASH_PROT  0x08
135 #define BL_ERROR_FLASH_CSUM  0x04
136 #define BL_ERROR_RESERVED    0x03
137 #define BL_ERROR_NO_ERR_IDLE    0x00
138 #define BL_ERROR_NO_ERR_ACTIVE  (BL_ERROR_BOOTLOADING)
139 
140 #define CAPABILITY_BTN_SHIFT            3
141 #define CAPABILITY_LEFT_BTN_MASK	(0x01 << 3)
142 #define CAPABILITY_RIGHT_BTN_MASK	(0x01 << 4)
143 #define CAPABILITY_MIDDLE_BTN_MASK	(0x01 << 5)
144 #define CAPABILITY_BTN_MASK  (CAPABILITY_LEFT_BTN_MASK | \
145 			      CAPABILITY_RIGHT_BTN_MASK | \
146 			      CAPABILITY_MIDDLE_BTN_MASK)
147 
148 #define PWR_MODE_MASK   0xfc
149 #define PWR_MODE_FULL_ACTIVE (0x3f << 2)
150 #define PWR_MODE_IDLE        (0x03 << 2) /* Default rt suspend scanrate: 30ms */
151 #define PWR_MODE_SLEEP       (0x05 << 2) /* Default suspend scanrate: 50ms */
152 #define PWR_MODE_BTN_ONLY    (0x01 << 2)
153 #define PWR_MODE_OFF         (0x00 << 2)
154 
155 #define PWR_STATUS_MASK      0x0c
156 #define PWR_STATUS_ACTIVE    (0x03 << 2)
157 #define PWR_STATUS_IDLE      (0x02 << 2)
158 #define PWR_STATUS_BTN_ONLY  (0x01 << 2)
159 #define PWR_STATUS_OFF       (0x00 << 2)
160 
161 #define AUTOSUSPEND_DELAY   2000 /* unit : ms */
162 
163 #define BTN_ONLY_MODE_NAME   "buttononly"
164 #define OFF_MODE_NAME        "off"
165 
166 /* Common macros for PIP interface. */
167 #define PIP_HID_DESCRIPTOR_ADDR		0x0001
168 #define PIP_REPORT_DESCRIPTOR_ADDR	0x0002
169 #define PIP_INPUT_REPORT_ADDR		0x0003
170 #define PIP_OUTPUT_REPORT_ADDR		0x0004
171 #define PIP_CMD_DATA_ADDR		0x0006
172 
173 #define PIP_RETRIEVE_DATA_STRUCTURE	0x24
174 #define PIP_CMD_CALIBRATE		0x28
175 #define PIP_BL_CMD_VERIFY_APP_INTEGRITY	0x31
176 #define PIP_BL_CMD_GET_BL_INFO		0x38
177 #define PIP_BL_CMD_PROGRAM_VERIFY_ROW	0x39
178 #define PIP_BL_CMD_LAUNCH_APP		0x3b
179 #define PIP_BL_CMD_INITIATE_BL		0x48
180 #define PIP_INVALID_CMD			0xff
181 
182 #define PIP_HID_DESCRIPTOR_SIZE		32
183 #define PIP_HID_APP_REPORT_ID		0xf7
184 #define PIP_HID_BL_REPORT_ID		0xff
185 
186 #define PIP_BL_CMD_REPORT_ID		0x40
187 #define PIP_BL_RESP_REPORT_ID		0x30
188 #define PIP_APP_CMD_REPORT_ID		0x2f
189 #define PIP_APP_RESP_REPORT_ID		0x1f
190 
191 #define PIP_READ_SYS_INFO_CMD_LENGTH	7
192 #define PIP_BL_READ_APP_INFO_CMD_LENGTH	13
193 #define PIP_MIN_BL_CMD_LENGTH		13
194 #define PIP_MIN_BL_RESP_LENGTH		11
195 #define PIP_MIN_APP_CMD_LENGTH		7
196 #define PIP_MIN_APP_RESP_LENGTH		5
197 #define PIP_UNSUPPORTED_CMD_RESP_LENGTH	6
198 #define PIP_READ_SYS_INFO_RESP_LENGTH	71
199 #define PIP_BL_APP_INFO_RESP_LENGTH	30
200 #define PIP_BL_GET_INFO_RESP_LENGTH	19
201 
202 #define PIP_BL_PLATFORM_VER_SHIFT	4
203 #define PIP_BL_PLATFORM_VER_MASK	0x0f
204 
205 #define PIP_PRODUCT_FAMILY_MASK		0xf000
206 #define PIP_PRODUCT_FAMILY_TRACKPAD	0x1000
207 
208 #define PIP_DEEP_SLEEP_STATE_ON		0x00
209 #define PIP_DEEP_SLEEP_STATE_OFF	0x01
210 #define PIP_DEEP_SLEEP_STATE_MASK	0x03
211 #define PIP_APP_DEEP_SLEEP_REPORT_ID	0xf0
212 #define PIP_DEEP_SLEEP_RESP_LENGTH	5
213 #define PIP_DEEP_SLEEP_OPCODE		0x08
214 #define PIP_DEEP_SLEEP_OPCODE_MASK	0x0f
215 
216 #define PIP_RESP_LENGTH_OFFSET		0
217 #define	    PIP_RESP_LENGTH_SIZE	2
218 #define PIP_RESP_REPORT_ID_OFFSET	2
219 #define PIP_RESP_RSVD_OFFSET		3
220 #define     PIP_RESP_RSVD_KEY		0x00
221 #define PIP_RESP_BL_SOP_OFFSET		4
222 #define     PIP_SOP_KEY			0x01  /* Start of Packet */
223 #define     PIP_EOP_KEY			0x17  /* End of Packet */
224 #define PIP_RESP_APP_CMD_OFFSET		4
225 #define     GET_PIP_CMD_CODE(reg)	((reg) & 0x7f)
226 #define PIP_RESP_STATUS_OFFSET		5
227 
228 #define VALID_CMD_RESP_HEADER(resp, cmd)				  \
229 	(((resp)[PIP_RESP_REPORT_ID_OFFSET] == PIP_APP_RESP_REPORT_ID) && \
230 	((resp)[PIP_RESP_RSVD_OFFSET] == PIP_RESP_RSVD_KEY) &&		  \
231 	(GET_PIP_CMD_CODE((resp)[PIP_RESP_APP_CMD_OFFSET]) == (cmd)))
232 
233 #define PIP_CMD_COMPLETE_SUCCESS(resp_data) \
234 	((resp_data)[PIP_RESP_STATUS_OFFSET] == 0x00)
235 
236 /* Variables to record latest gen5 trackpad power states. */
237 #define UNINIT_SLEEP_TIME	0xffff
238 #define UNINIT_PWR_MODE		0xff
239 #define PIP_DEV_SET_PWR_STATE(cyapa, s)		((cyapa)->dev_pwr_mode = (s))
240 #define PIP_DEV_GET_PWR_STATE(cyapa)		((cyapa)->dev_pwr_mode)
241 #define PIP_DEV_SET_SLEEP_TIME(cyapa, t)	((cyapa)->dev_sleep_time = (t))
242 #define PIP_DEV_GET_SLEEP_TIME(cyapa)		((cyapa)->dev_sleep_time)
243 #define PIP_DEV_UNINIT_SLEEP_TIME(cyapa)	\
244 		(((cyapa)->dev_sleep_time) == UNINIT_SLEEP_TIME)
245 
246 /* The touch.id is used as the MT slot id, thus max MT slot is 15 */
247 #define CYAPA_MAX_MT_SLOTS  15
248 
249 struct cyapa;
250 
251 typedef bool (*cb_sort)(struct cyapa *, u8 *, int);
252 
253 enum cyapa_pm_stage {
254 	CYAPA_PM_DEACTIVE,
255 	CYAPA_PM_ACTIVE,
256 	CYAPA_PM_SUSPEND,
257 	CYAPA_PM_RESUME,
258 	CYAPA_PM_RUNTIME_SUSPEND,
259 	CYAPA_PM_RUNTIME_RESUME,
260 };
261 
262 struct cyapa_dev_ops {
263 	int (*check_fw)(struct cyapa *, const struct firmware *);
264 	int (*bl_enter)(struct cyapa *);
265 	int (*bl_activate)(struct cyapa *);
266 	int (*bl_initiate)(struct cyapa *, const struct firmware *);
267 	int (*update_fw)(struct cyapa *, const struct firmware *);
268 	int (*bl_deactivate)(struct cyapa *);
269 
270 	ssize_t (*show_baseline)(struct device *,
271 			struct device_attribute *, char *);
272 	ssize_t (*calibrate_store)(struct device *,
273 			struct device_attribute *, const char *, size_t);
274 
275 	int (*initialize)(struct cyapa *cyapa);
276 
277 	int (*state_parse)(struct cyapa *cyapa, u8 *reg_status, int len);
278 	int (*operational_check)(struct cyapa *cyapa);
279 
280 	int (*irq_handler)(struct cyapa *);
281 	bool (*irq_cmd_handler)(struct cyapa *);
282 	int (*sort_empty_output_data)(struct cyapa *,
283 			u8 *, int *, cb_sort);
284 
285 	int (*set_power_mode)(struct cyapa *, u8, u16, enum cyapa_pm_stage);
286 
287 	int (*set_proximity)(struct cyapa *, bool);
288 };
289 
290 struct cyapa_pip_cmd_states {
291 	struct mutex cmd_lock;
292 	struct completion cmd_ready;
293 	atomic_t cmd_issued;
294 	u8 in_progress_cmd;
295 	bool is_irq_mode;
296 
297 	cb_sort resp_sort_func;
298 	u8 *resp_data;
299 	int *resp_len;
300 
301 	enum cyapa_pm_stage pm_stage;
302 	struct mutex pm_stage_lock;
303 
304 	u8 irq_cmd_buf[CYAPA_REG_MAP_SIZE];
305 	u8 empty_buf[CYAPA_REG_MAP_SIZE];
306 };
307 
308 union cyapa_cmd_states {
309 	struct cyapa_pip_cmd_states pip;
310 };
311 
312 enum cyapa_state {
313 	CYAPA_STATE_NO_DEVICE,
314 	CYAPA_STATE_BL_BUSY,
315 	CYAPA_STATE_BL_IDLE,
316 	CYAPA_STATE_BL_ACTIVE,
317 	CYAPA_STATE_OP,
318 	CYAPA_STATE_GEN5_BL,
319 	CYAPA_STATE_GEN5_APP,
320 	CYAPA_STATE_GEN6_BL,
321 	CYAPA_STATE_GEN6_APP,
322 };
323 
324 struct gen6_interval_setting {
325 	u16 active_interval;
326 	u16 lp1_interval;
327 	u16 lp2_interval;
328 };
329 
330 /* The main device structure */
331 struct cyapa {
332 	enum cyapa_state state;
333 	u8 status[BL_STATUS_SIZE];
334 	bool operational; /* true: ready for data reporting; false: not. */
335 
336 	struct regulator *vcc;
337 	struct i2c_client *client;
338 	struct input_dev *input;
339 	char phys[32];	/* Device physical location */
340 	bool irq_wake;  /* Irq wake is enabled */
341 	bool smbus;
342 
343 	/* power mode settings */
344 	u8 suspend_power_mode;
345 	u16 suspend_sleep_time;
346 	u8 runtime_suspend_power_mode;
347 	u16 runtime_suspend_sleep_time;
348 	u8 dev_pwr_mode;
349 	u16 dev_sleep_time;
350 	struct gen6_interval_setting gen6_interval_setting;
351 
352 	/* Read from query data region. */
353 	char product_id[16];
354 	u8 platform_ver;  /* Platform version. */
355 	u8 fw_maj_ver;  /* Firmware major version. */
356 	u8 fw_min_ver;  /* Firmware minor version. */
357 	u8 btn_capability;
358 	u8 gen;
359 	int max_abs_x;
360 	int max_abs_y;
361 	int physical_size_x;
362 	int physical_size_y;
363 
364 	/* Used in ttsp and truetouch based trackpad devices. */
365 	u8 x_origin;  /* X Axis Origin: 0 = left side; 1 = right side. */
366 	u8 y_origin;  /* Y Axis Origin: 0 = top; 1 = bottom. */
367 	int electrodes_x;  /* Number of electrodes on the X Axis*/
368 	int electrodes_y;  /* Number of electrodes on the Y Axis*/
369 	int electrodes_rx;  /* Number of Rx electrodes */
370 	int aligned_electrodes_rx;  /* 4 aligned */
371 	int max_z;
372 
373 	/*
374 	 * Used to synchronize the access or update the device state.
375 	 * And since update firmware and read firmware image process will take
376 	 * quite long time, maybe more than 10 seconds, so use mutex_lock
377 	 * to sync and wait other interface and detecting are done or ready.
378 	 */
379 	struct mutex state_sync_lock;
380 
381 	const struct cyapa_dev_ops *ops;
382 
383 	union cyapa_cmd_states cmd_states;
384 };
385 
386 
387 ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len,
388 				 u8 *values);
389 ssize_t cyapa_smbus_read_block(struct cyapa *cyapa, u8 cmd, size_t len,
390 			       u8 *values);
391 
392 ssize_t cyapa_read_block(struct cyapa *cyapa, u8 cmd_idx, u8 *values);
393 
394 int cyapa_poll_state(struct cyapa *cyapa, unsigned int timeout);
395 
396 u8 cyapa_sleep_time_to_pwr_cmd(u16 sleep_time);
397 u16 cyapa_pwr_cmd_to_sleep_time(u8 pwr_mode);
398 
399 ssize_t cyapa_i2c_pip_read(struct cyapa *cyapa, u8 *buf, size_t size);
400 ssize_t cyapa_i2c_pip_write(struct cyapa *cyapa, u8 *buf, size_t size);
401 int cyapa_empty_pip_output_data(struct cyapa *cyapa,
402 				u8 *buf, int *len, cb_sort func);
403 int cyapa_i2c_pip_cmd_irq_sync(struct cyapa *cyapa,
404 			       u8 *cmd, int cmd_len,
405 			       u8 *resp_data, int *resp_len,
406 			       unsigned long timeout,
407 			       cb_sort func,
408 			       bool irq_mode);
409 int cyapa_pip_state_parse(struct cyapa *cyapa, u8 *reg_data, int len);
410 bool cyapa_pip_sort_system_info_data(struct cyapa *cyapa, u8 *buf, int len);
411 bool cyapa_sort_tsg_pip_bl_resp_data(struct cyapa *cyapa, u8 *data, int len);
412 int cyapa_pip_deep_sleep(struct cyapa *cyapa, u8 state);
413 bool cyapa_sort_tsg_pip_app_resp_data(struct cyapa *cyapa, u8 *data, int len);
414 int cyapa_pip_bl_exit(struct cyapa *cyapa);
415 int cyapa_pip_bl_enter(struct cyapa *cyapa);
416 
417 
418 bool cyapa_is_pip_bl_mode(struct cyapa *cyapa);
419 bool cyapa_is_pip_app_mode(struct cyapa *cyapa);
420 int cyapa_pip_cmd_state_initialize(struct cyapa *cyapa);
421 
422 int cyapa_pip_resume_scanning(struct cyapa *cyapa);
423 int cyapa_pip_suspend_scanning(struct cyapa *cyapa);
424 
425 int cyapa_pip_check_fw(struct cyapa *cyapa, const struct firmware *fw);
426 int cyapa_pip_bl_initiate(struct cyapa *cyapa, const struct firmware *fw);
427 int cyapa_pip_do_fw_update(struct cyapa *cyapa, const struct firmware *fw);
428 int cyapa_pip_bl_activate(struct cyapa *cyapa);
429 int cyapa_pip_bl_deactivate(struct cyapa *cyapa);
430 ssize_t cyapa_pip_do_calibrate(struct device *dev,
431 			       struct device_attribute *attr,
432 			       const char *buf, size_t count);
433 int cyapa_pip_set_proximity(struct cyapa *cyapa, bool enable);
434 
435 bool cyapa_pip_irq_cmd_handler(struct cyapa *cyapa);
436 int cyapa_pip_irq_handler(struct cyapa *cyapa);
437 
438 
439 extern u8 pip_read_sys_info[];
440 extern u8 pip_bl_read_app_info[];
441 extern const char product_id[];
442 extern const struct cyapa_dev_ops cyapa_gen3_ops;
443 extern const struct cyapa_dev_ops cyapa_gen5_ops;
444 extern const struct cyapa_dev_ops cyapa_gen6_ops;
445 
446 #endif
447