1 /* 2 * Texas Instruments ADS7950 SPI ADC driver 3 * 4 * Copyright 2016 David Lechner <david@lechnology.com> 5 * 6 * Based on iio/ad7923.c: 7 * Copyright 2011 Analog Devices Inc 8 * Copyright 2012 CS Systemes d'Information 9 * 10 * And also on hwmon/ads79xx.c 11 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 12 * Nishanth Menon 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation version 2. 17 * 18 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 19 * kind, whether express or implied; without even the implied warranty 20 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 */ 23 24 #include <linux/bitops.h> 25 #include <linux/device.h> 26 #include <linux/err.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 #include <linux/spi/spi.h> 33 34 #include <linux/iio/buffer.h> 35 #include <linux/iio/iio.h> 36 #include <linux/iio/sysfs.h> 37 #include <linux/iio/trigger_consumer.h> 38 #include <linux/iio/triggered_buffer.h> 39 40 #define TI_ADS7950_CR_MANUAL BIT(12) 41 #define TI_ADS7950_CR_WRITE BIT(11) 42 #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7) 43 #define TI_ADS7950_CR_RANGE_5V BIT(6) 44 45 #define TI_ADS7950_MAX_CHAN 16 46 47 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16)) 48 49 /* val = value, dec = left shift, bits = number of bits of the mask */ 50 #define TI_ADS7950_EXTRACT(val, dec, bits) \ 51 (((val) >> (dec)) & ((1 << (bits)) - 1)) 52 53 struct ti_ads7950_state { 54 struct spi_device *spi; 55 struct spi_transfer ring_xfer[TI_ADS7950_MAX_CHAN + 2]; 56 struct spi_transfer scan_single_xfer[3]; 57 struct spi_message ring_msg; 58 struct spi_message scan_single_msg; 59 60 struct regulator *reg; 61 62 unsigned int settings; 63 64 /* 65 * DMA (thus cache coherency maintenance) requires the 66 * transfer buffers to live in their own cache lines. 67 */ 68 __be16 rx_buf[TI_ADS7950_MAX_CHAN + TI_ADS7950_TIMESTAMP_SIZE] 69 ____cacheline_aligned; 70 __be16 tx_buf[TI_ADS7950_MAX_CHAN]; 71 }; 72 73 struct ti_ads7950_chip_info { 74 const struct iio_chan_spec *channels; 75 unsigned int num_channels; 76 }; 77 78 enum ti_ads7950_id { 79 TI_ADS7950, 80 TI_ADS7951, 81 TI_ADS7952, 82 TI_ADS7953, 83 TI_ADS7954, 84 TI_ADS7955, 85 TI_ADS7956, 86 TI_ADS7957, 87 TI_ADS7958, 88 TI_ADS7959, 89 TI_ADS7960, 90 TI_ADS7961, 91 }; 92 93 #define TI_ADS7950_V_CHAN(index, bits) \ 94 { \ 95 .type = IIO_VOLTAGE, \ 96 .indexed = 1, \ 97 .channel = index, \ 98 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 99 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 100 .address = index, \ 101 .datasheet_name = "CH##index", \ 102 .scan_index = index, \ 103 .scan_type = { \ 104 .sign = 'u', \ 105 .realbits = bits, \ 106 .storagebits = 16, \ 107 .shift = 12 - (bits), \ 108 .endianness = IIO_BE, \ 109 }, \ 110 } 111 112 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \ 113 const struct iio_chan_spec name ## _channels[] = { \ 114 TI_ADS7950_V_CHAN(0, bits), \ 115 TI_ADS7950_V_CHAN(1, bits), \ 116 TI_ADS7950_V_CHAN(2, bits), \ 117 TI_ADS7950_V_CHAN(3, bits), \ 118 IIO_CHAN_SOFT_TIMESTAMP(4), \ 119 } 120 121 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \ 122 const struct iio_chan_spec name ## _channels[] = { \ 123 TI_ADS7950_V_CHAN(0, bits), \ 124 TI_ADS7950_V_CHAN(1, bits), \ 125 TI_ADS7950_V_CHAN(2, bits), \ 126 TI_ADS7950_V_CHAN(3, bits), \ 127 TI_ADS7950_V_CHAN(4, bits), \ 128 TI_ADS7950_V_CHAN(5, bits), \ 129 TI_ADS7950_V_CHAN(6, bits), \ 130 TI_ADS7950_V_CHAN(7, bits), \ 131 IIO_CHAN_SOFT_TIMESTAMP(8), \ 132 } 133 134 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \ 135 const struct iio_chan_spec name ## _channels[] = { \ 136 TI_ADS7950_V_CHAN(0, bits), \ 137 TI_ADS7950_V_CHAN(1, bits), \ 138 TI_ADS7950_V_CHAN(2, bits), \ 139 TI_ADS7950_V_CHAN(3, bits), \ 140 TI_ADS7950_V_CHAN(4, bits), \ 141 TI_ADS7950_V_CHAN(5, bits), \ 142 TI_ADS7950_V_CHAN(6, bits), \ 143 TI_ADS7950_V_CHAN(7, bits), \ 144 TI_ADS7950_V_CHAN(8, bits), \ 145 TI_ADS7950_V_CHAN(9, bits), \ 146 TI_ADS7950_V_CHAN(10, bits), \ 147 TI_ADS7950_V_CHAN(11, bits), \ 148 IIO_CHAN_SOFT_TIMESTAMP(12), \ 149 } 150 151 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \ 152 const struct iio_chan_spec name ## _channels[] = { \ 153 TI_ADS7950_V_CHAN(0, bits), \ 154 TI_ADS7950_V_CHAN(1, bits), \ 155 TI_ADS7950_V_CHAN(2, bits), \ 156 TI_ADS7950_V_CHAN(3, bits), \ 157 TI_ADS7950_V_CHAN(4, bits), \ 158 TI_ADS7950_V_CHAN(5, bits), \ 159 TI_ADS7950_V_CHAN(6, bits), \ 160 TI_ADS7950_V_CHAN(7, bits), \ 161 TI_ADS7950_V_CHAN(8, bits), \ 162 TI_ADS7950_V_CHAN(9, bits), \ 163 TI_ADS7950_V_CHAN(10, bits), \ 164 TI_ADS7950_V_CHAN(11, bits), \ 165 TI_ADS7950_V_CHAN(12, bits), \ 166 TI_ADS7950_V_CHAN(13, bits), \ 167 TI_ADS7950_V_CHAN(14, bits), \ 168 TI_ADS7950_V_CHAN(15, bits), \ 169 IIO_CHAN_SOFT_TIMESTAMP(16), \ 170 } 171 172 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12); 173 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12); 174 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12); 175 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12); 176 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10); 177 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10); 178 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10); 179 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10); 180 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8); 181 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8); 182 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8); 183 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8); 184 185 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = { 186 [TI_ADS7950] = { 187 .channels = ti_ads7950_channels, 188 .num_channels = ARRAY_SIZE(ti_ads7950_channels), 189 }, 190 [TI_ADS7951] = { 191 .channels = ti_ads7951_channels, 192 .num_channels = ARRAY_SIZE(ti_ads7951_channels), 193 }, 194 [TI_ADS7952] = { 195 .channels = ti_ads7952_channels, 196 .num_channels = ARRAY_SIZE(ti_ads7952_channels), 197 }, 198 [TI_ADS7953] = { 199 .channels = ti_ads7953_channels, 200 .num_channels = ARRAY_SIZE(ti_ads7953_channels), 201 }, 202 [TI_ADS7954] = { 203 .channels = ti_ads7954_channels, 204 .num_channels = ARRAY_SIZE(ti_ads7954_channels), 205 }, 206 [TI_ADS7955] = { 207 .channels = ti_ads7955_channels, 208 .num_channels = ARRAY_SIZE(ti_ads7955_channels), 209 }, 210 [TI_ADS7956] = { 211 .channels = ti_ads7956_channels, 212 .num_channels = ARRAY_SIZE(ti_ads7956_channels), 213 }, 214 [TI_ADS7957] = { 215 .channels = ti_ads7957_channels, 216 .num_channels = ARRAY_SIZE(ti_ads7957_channels), 217 }, 218 [TI_ADS7958] = { 219 .channels = ti_ads7958_channels, 220 .num_channels = ARRAY_SIZE(ti_ads7958_channels), 221 }, 222 [TI_ADS7959] = { 223 .channels = ti_ads7959_channels, 224 .num_channels = ARRAY_SIZE(ti_ads7959_channels), 225 }, 226 [TI_ADS7960] = { 227 .channels = ti_ads7960_channels, 228 .num_channels = ARRAY_SIZE(ti_ads7960_channels), 229 }, 230 [TI_ADS7961] = { 231 .channels = ti_ads7961_channels, 232 .num_channels = ARRAY_SIZE(ti_ads7961_channels), 233 }, 234 }; 235 236 /* 237 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new 238 * scan mask 239 */ 240 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev, 241 const unsigned long *active_scan_mask) 242 { 243 struct ti_ads7950_state *st = iio_priv(indio_dev); 244 int i, cmd, len; 245 246 len = 0; 247 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) { 248 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings; 249 st->tx_buf[len++] = cpu_to_be16(cmd); 250 } 251 252 /* Data for the 1st channel is not returned until the 3rd transfer */ 253 len += 2; 254 for (i = 0; i < len; i++) { 255 if ((i + 2) < len) 256 st->ring_xfer[i].tx_buf = &st->tx_buf[i]; 257 if (i >= 2) 258 st->ring_xfer[i].rx_buf = &st->rx_buf[i - 2]; 259 st->ring_xfer[i].len = 2; 260 st->ring_xfer[i].cs_change = 1; 261 } 262 /* make sure last transfer's cs_change is not set */ 263 st->ring_xfer[len - 1].cs_change = 0; 264 265 spi_message_init_with_transfers(&st->ring_msg, st->ring_xfer, len); 266 267 return 0; 268 } 269 270 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p) 271 { 272 struct iio_poll_func *pf = p; 273 struct iio_dev *indio_dev = pf->indio_dev; 274 struct ti_ads7950_state *st = iio_priv(indio_dev); 275 int ret; 276 277 ret = spi_sync(st->spi, &st->ring_msg); 278 if (ret < 0) 279 goto out; 280 281 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf, 282 iio_get_time_ns(indio_dev)); 283 284 out: 285 iio_trigger_notify_done(indio_dev->trig); 286 287 return IRQ_HANDLED; 288 } 289 290 static int ti_ads7950_scan_direct(struct ti_ads7950_state *st, unsigned int ch) 291 { 292 int ret, cmd; 293 294 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings; 295 st->tx_buf[0] = cpu_to_be16(cmd); 296 297 ret = spi_sync(st->spi, &st->scan_single_msg); 298 if (ret) 299 return ret; 300 301 return be16_to_cpu(st->rx_buf[0]); 302 } 303 304 static int ti_ads7950_get_range(struct ti_ads7950_state *st) 305 { 306 int vref; 307 308 vref = regulator_get_voltage(st->reg); 309 if (vref < 0) 310 return vref; 311 312 vref /= 1000; 313 314 if (st->settings & TI_ADS7950_CR_RANGE_5V) 315 vref *= 2; 316 317 return vref; 318 } 319 320 static int ti_ads7950_read_raw(struct iio_dev *indio_dev, 321 struct iio_chan_spec const *chan, 322 int *val, int *val2, long m) 323 { 324 struct ti_ads7950_state *st = iio_priv(indio_dev); 325 int ret; 326 327 switch (m) { 328 case IIO_CHAN_INFO_RAW: 329 330 ret = iio_device_claim_direct_mode(indio_dev); 331 if (ret < 0) 332 return ret; 333 334 ret = ti_ads7950_scan_direct(st, chan->address); 335 iio_device_release_direct_mode(indio_dev); 336 if (ret < 0) 337 return ret; 338 339 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4)) 340 return -EIO; 341 342 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift, 343 chan->scan_type.realbits); 344 345 return IIO_VAL_INT; 346 case IIO_CHAN_INFO_SCALE: 347 ret = ti_ads7950_get_range(st); 348 if (ret < 0) 349 return ret; 350 351 *val = ret; 352 *val2 = (1 << chan->scan_type.realbits) - 1; 353 354 return IIO_VAL_FRACTIONAL; 355 } 356 357 return -EINVAL; 358 } 359 360 static const struct iio_info ti_ads7950_info = { 361 .read_raw = &ti_ads7950_read_raw, 362 .update_scan_mode = ti_ads7950_update_scan_mode, 363 .driver_module = THIS_MODULE, 364 }; 365 366 static int ti_ads7950_probe(struct spi_device *spi) 367 { 368 struct ti_ads7950_state *st; 369 struct iio_dev *indio_dev; 370 const struct ti_ads7950_chip_info *info; 371 int ret; 372 373 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 374 if (!indio_dev) 375 return -ENOMEM; 376 377 st = iio_priv(indio_dev); 378 379 spi_set_drvdata(spi, indio_dev); 380 381 st->spi = spi; 382 st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V; 383 384 info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data]; 385 386 indio_dev->name = spi_get_device_id(spi)->name; 387 indio_dev->dev.parent = &spi->dev; 388 indio_dev->modes = INDIO_DIRECT_MODE; 389 indio_dev->channels = info->channels; 390 indio_dev->num_channels = info->num_channels; 391 indio_dev->info = &ti_ads7950_info; 392 393 /* 394 * Setup default message. The sample is read at the end of the first 395 * transfer, then it takes one full cycle to convert the sample and one 396 * more cycle to send the value. The conversion process is driven by 397 * the SPI clock, which is why we have 3 transfers. The middle one is 398 * just dummy data sent while the chip is converting the sample that 399 * was read at the end of the first transfer. 400 */ 401 402 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0]; 403 st->scan_single_xfer[0].len = 2; 404 st->scan_single_xfer[0].cs_change = 1; 405 st->scan_single_xfer[1].tx_buf = &st->tx_buf[0]; 406 st->scan_single_xfer[1].len = 2; 407 st->scan_single_xfer[1].cs_change = 1; 408 st->scan_single_xfer[2].rx_buf = &st->rx_buf[0]; 409 st->scan_single_xfer[2].len = 2; 410 411 spi_message_init_with_transfers(&st->scan_single_msg, 412 st->scan_single_xfer, 3); 413 414 st->reg = devm_regulator_get(&spi->dev, "vref"); 415 if (IS_ERR(st->reg)) { 416 dev_err(&spi->dev, "Failed get get regulator \"vref\"\n"); 417 return PTR_ERR(st->reg); 418 } 419 420 ret = regulator_enable(st->reg); 421 if (ret) { 422 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n"); 423 return ret; 424 } 425 426 ret = iio_triggered_buffer_setup(indio_dev, NULL, 427 &ti_ads7950_trigger_handler, NULL); 428 if (ret) { 429 dev_err(&spi->dev, "Failed to setup triggered buffer\n"); 430 goto error_disable_reg; 431 } 432 433 ret = iio_device_register(indio_dev); 434 if (ret) { 435 dev_err(&spi->dev, "Failed to register iio device\n"); 436 goto error_cleanup_ring; 437 } 438 439 return 0; 440 441 error_cleanup_ring: 442 iio_triggered_buffer_cleanup(indio_dev); 443 error_disable_reg: 444 regulator_disable(st->reg); 445 446 return ret; 447 } 448 449 static int ti_ads7950_remove(struct spi_device *spi) 450 { 451 struct iio_dev *indio_dev = spi_get_drvdata(spi); 452 struct ti_ads7950_state *st = iio_priv(indio_dev); 453 454 iio_device_unregister(indio_dev); 455 iio_triggered_buffer_cleanup(indio_dev); 456 regulator_disable(st->reg); 457 458 return 0; 459 } 460 461 static const struct spi_device_id ti_ads7950_id[] = { 462 { "ads7950", TI_ADS7950 }, 463 { "ads7951", TI_ADS7951 }, 464 { "ads7952", TI_ADS7952 }, 465 { "ads7953", TI_ADS7953 }, 466 { "ads7954", TI_ADS7954 }, 467 { "ads7955", TI_ADS7955 }, 468 { "ads7956", TI_ADS7956 }, 469 { "ads7957", TI_ADS7957 }, 470 { "ads7958", TI_ADS7958 }, 471 { "ads7959", TI_ADS7959 }, 472 { "ads7960", TI_ADS7960 }, 473 { "ads7961", TI_ADS7961 }, 474 { } 475 }; 476 MODULE_DEVICE_TABLE(spi, ti_ads7950_id); 477 478 static struct spi_driver ti_ads7950_driver = { 479 .driver = { 480 .name = "ads7950", 481 }, 482 .probe = ti_ads7950_probe, 483 .remove = ti_ads7950_remove, 484 .id_table = ti_ads7950_id, 485 }; 486 module_spi_driver(ti_ads7950_driver); 487 488 MODULE_AUTHOR("David Lechner <david@lechnology.com>"); 489 MODULE_DESCRIPTION("TI TI_ADS7950 ADC"); 490 MODULE_LICENSE("GPL v2"); 491