1 /* 2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/i2c.h> 24 #include <linux/fs.h> 25 #include <linux/io.h> 26 #include <linux/types.h> 27 #include <linux/interrupt.h> 28 #include <linux/jiffies.h> 29 #include <linux/pci.h> 30 #include <linux/mutex.h> 31 #include <linux/ktime.h> 32 33 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ 34 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ 35 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */ 36 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ 37 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ 38 39 #define PCH_I2CSADR 0x00 /* I2C slave address register */ 40 #define PCH_I2CCTL 0x04 /* I2C control register */ 41 #define PCH_I2CSR 0x08 /* I2C status register */ 42 #define PCH_I2CDR 0x0C /* I2C data register */ 43 #define PCH_I2CMON 0x10 /* I2C bus monitor register */ 44 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */ 45 #define PCH_I2CMOD 0x18 /* I2C mode register */ 46 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */ 47 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */ 48 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */ 49 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */ 50 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */ 51 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */ 52 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */ 53 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */ 54 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */ 55 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */ 56 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */ 57 #define PCH_I2CTMR 0x48 /* I2C timer register */ 58 #define PCH_I2CSRST 0xFC /* I2C reset register */ 59 #define PCH_I2CNF 0xF8 /* I2C noise filter register */ 60 61 #define BUS_IDLE_TIMEOUT 20 62 #define PCH_I2CCTL_I2CMEN 0x0080 63 #define TEN_BIT_ADDR_DEFAULT 0xF000 64 #define TEN_BIT_ADDR_MASK 0xF0 65 #define PCH_START 0x0020 66 #define PCH_ESR_START 0x0001 67 #define PCH_BUFF_START 0x1 68 #define PCH_REPSTART 0x0004 69 #define PCH_ACK 0x0008 70 #define PCH_GETACK 0x0001 71 #define CLR_REG 0x0 72 #define I2C_RD 0x1 73 #define I2CMCF_BIT 0x0080 74 #define I2CMIF_BIT 0x0002 75 #define I2CMAL_BIT 0x0010 76 #define I2CBMFI_BIT 0x0001 77 #define I2CBMAL_BIT 0x0002 78 #define I2CBMNA_BIT 0x0004 79 #define I2CBMTO_BIT 0x0008 80 #define I2CBMIS_BIT 0x0010 81 #define I2CESRFI_BIT 0X0001 82 #define I2CESRTO_BIT 0x0002 83 #define I2CESRFIIE_BIT 0x1 84 #define I2CESRTOIE_BIT 0x2 85 #define I2CBMDZ_BIT 0x0040 86 #define I2CBMAG_BIT 0x0020 87 #define I2CMBB_BIT 0x0020 88 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \ 89 I2CBMTO_BIT | I2CBMIS_BIT) 90 #define I2C_ADDR_MSK 0xFF 91 #define I2C_MSB_2B_MSK 0x300 92 #define FAST_MODE_CLK 400 93 #define FAST_MODE_EN 0x0001 94 #define SUB_ADDR_LEN_MAX 4 95 #define BUF_LEN_MAX 32 96 #define PCH_BUFFER_MODE 0x1 97 #define EEPROM_SW_RST_MODE 0x0002 98 #define NORMAL_INTR_ENBL 0x0300 99 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT) 100 #define EEPROM_RST_INTR_DISBL 0x0 101 #define BUFFER_MODE_INTR_ENBL 0x001F 102 #define BUFFER_MODE_INTR_DISBL 0x0 103 #define NORMAL_MODE 0x0 104 #define BUFFER_MODE 0x1 105 #define EEPROM_SR_MODE 0x2 106 #define I2C_TX_MODE 0x0010 107 #define PCH_BUF_TX 0xFFF7 108 #define PCH_BUF_RD 0x0008 109 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \ 110 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT) 111 #define I2CMAL_EVENT 0x0001 112 #define I2CMCF_EVENT 0x0002 113 #define I2CBMFI_EVENT 0x0004 114 #define I2CBMAL_EVENT 0x0008 115 #define I2CBMNA_EVENT 0x0010 116 #define I2CBMTO_EVENT 0x0020 117 #define I2CBMIS_EVENT 0x0040 118 #define I2CESRFI_EVENT 0x0080 119 #define I2CESRTO_EVENT 0x0100 120 #define PCI_DEVICE_ID_PCH_I2C 0x8817 121 122 #define pch_dbg(adap, fmt, arg...) \ 123 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 124 125 #define pch_err(adap, fmt, arg...) \ 126 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 127 128 #define pch_pci_err(pdev, fmt, arg...) \ 129 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg) 130 131 #define pch_pci_dbg(pdev, fmt, arg...) \ 132 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg) 133 134 /** 135 * struct i2c_algo_pch_data - for I2C driver functionalities 136 * @pch_adapter: stores the reference to i2c_adapter structure 137 * @p_adapter_info: stores the reference to adapter_info structure 138 * @pch_base_address: specifies the remapped base address 139 * @pch_buff_mode_en: specifies if buffer mode is enabled 140 * @pch_event_flag: specifies occurrence of interrupt events 141 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed 142 */ 143 struct i2c_algo_pch_data { 144 struct i2c_adapter pch_adapter; 145 struct adapter_info *p_adapter_info; 146 void __iomem *pch_base_address; 147 int pch_buff_mode_en; 148 u32 pch_event_flag; 149 bool pch_i2c_xfer_in_progress; 150 }; 151 152 /** 153 * struct adapter_info - This structure holds the adapter information for the 154 PCH i2c controller 155 * @pch_data: stores a list of i2c_algo_pch_data 156 * @pch_i2c_suspended: specifies whether the system is suspended or not 157 * perhaps with more lines and words. 158 * 159 * pch_data has as many elements as maximum I2C channels 160 */ 161 struct adapter_info { 162 struct i2c_algo_pch_data pch_data; 163 bool pch_i2c_suspended; 164 }; 165 166 167 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */ 168 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */ 169 static wait_queue_head_t pch_event; 170 static DEFINE_MUTEX(pch_mutex); 171 172 static struct pci_device_id __devinitdata pch_pcidev_id[] = { 173 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)}, 174 {0,} 175 }; 176 177 static irqreturn_t pch_i2c_handler(int irq, void *pData); 178 179 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask) 180 { 181 u32 val; 182 val = ioread32(addr + offset); 183 val |= bitmask; 184 iowrite32(val, addr + offset); 185 } 186 187 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask) 188 { 189 u32 val; 190 val = ioread32(addr + offset); 191 val &= (~bitmask); 192 iowrite32(val, addr + offset); 193 } 194 195 /** 196 * pch_i2c_init() - hardware initialization of I2C module 197 * @adap: Pointer to struct i2c_algo_pch_data. 198 */ 199 static void pch_i2c_init(struct i2c_algo_pch_data *adap) 200 { 201 void __iomem *p = adap->pch_base_address; 202 u32 pch_i2cbc; 203 u32 pch_i2ctmr; 204 u32 reg_value; 205 206 /* reset I2C controller */ 207 iowrite32(0x01, p + PCH_I2CSRST); 208 msleep(20); 209 iowrite32(0x0, p + PCH_I2CSRST); 210 211 /* Initialize I2C registers */ 212 iowrite32(0x21, p + PCH_I2CNF); 213 214 pch_setbit(adap->pch_base_address, PCH_I2CCTL, 215 PCH_I2CCTL_I2CMEN); 216 217 if (pch_i2c_speed != 400) 218 pch_i2c_speed = 100; 219 220 reg_value = PCH_I2CCTL_I2CMEN; 221 if (pch_i2c_speed == FAST_MODE_CLK) { 222 reg_value |= FAST_MODE_EN; 223 pch_dbg(adap, "Fast mode enabled\n"); 224 } 225 226 if (pch_clk > PCH_MAX_CLK) 227 pch_clk = 62500; 228 229 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8; 230 /* Set transfer speed in I2CBC */ 231 iowrite32(pch_i2cbc, p + PCH_I2CBC); 232 233 pch_i2ctmr = (pch_clk) / 8; 234 iowrite32(pch_i2ctmr, p + PCH_I2CTMR); 235 236 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */ 237 iowrite32(reg_value, p + PCH_I2CCTL); 238 239 pch_dbg(adap, 240 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n", 241 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr); 242 243 init_waitqueue_head(&pch_event); 244 } 245 246 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2) 247 { 248 return cmp1.tv64 < cmp2.tv64; 249 } 250 251 /** 252 * pch_i2c_wait_for_bus_idle() - check the status of bus. 253 * @adap: Pointer to struct i2c_algo_pch_data. 254 * @timeout: waiting time counter (us). 255 */ 256 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, 257 s32 timeout) 258 { 259 void __iomem *p = adap->pch_base_address; 260 261 /* MAX timeout value is timeout*1000*1000nsec */ 262 ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); 263 do { 264 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) 265 break; 266 msleep(20); 267 } while (ktime_lt(ktime_get(), ns_val)); 268 269 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 270 271 if (timeout == 0) { 272 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME); 273 return -ETIME; 274 } 275 276 return 0; 277 } 278 279 /** 280 * pch_i2c_start() - Generate I2C start condition in normal mode. 281 * @adap: Pointer to struct i2c_algo_pch_data. 282 * 283 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1. 284 */ 285 static void pch_i2c_start(struct i2c_algo_pch_data *adap) 286 { 287 void __iomem *p = adap->pch_base_address; 288 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 289 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 290 } 291 292 /** 293 * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event 294 * @adap: Pointer to struct i2c_algo_pch_data. 295 */ 296 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap) 297 { 298 s32 ret; 299 ret = wait_event_timeout(pch_event, 300 (adap->pch_event_flag != 0), msecs_to_jiffies(50)); 301 if (ret < 0) { 302 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 303 return ret; 304 } 305 306 if (ret == 0) { 307 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 308 return -ETIMEDOUT; 309 } 310 311 if (adap->pch_event_flag & I2C_ERROR_MASK) { 312 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag); 313 return -EIO; 314 } 315 316 adap->pch_event_flag = 0; 317 318 return 0; 319 } 320 321 /** 322 * pch_i2c_getack() - to confirm ACK/NACK 323 * @adap: Pointer to struct i2c_algo_pch_data. 324 */ 325 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap) 326 { 327 u32 reg_val; 328 void __iomem *p = adap->pch_base_address; 329 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK; 330 331 if (reg_val != 0) { 332 pch_err(adap, "return%d\n", -EPROTO); 333 return -EPROTO; 334 } 335 336 return 0; 337 } 338 339 /** 340 * pch_i2c_stop() - generate stop condition in normal mode. 341 * @adap: Pointer to struct i2c_algo_pch_data. 342 */ 343 static void pch_i2c_stop(struct i2c_algo_pch_data *adap) 344 { 345 void __iomem *p = adap->pch_base_address; 346 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 347 /* clear the start bit */ 348 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 349 } 350 351 /** 352 * pch_i2c_repstart() - generate repeated start condition in normal mode 353 * @adap: Pointer to struct i2c_algo_pch_data. 354 */ 355 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap) 356 { 357 void __iomem *p = adap->pch_base_address; 358 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 359 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART); 360 } 361 362 /** 363 * pch_i2c_writebytes() - write data to I2C bus in normal mode 364 * @i2c_adap: Pointer to the struct i2c_adapter. 365 * @last: specifies whether last message or not. 366 * In the case of compound mode it will be 1 for last message, 367 * otherwise 0. 368 * @first: specifies whether first message or not. 369 * 1 for first message otherwise 0. 370 */ 371 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, 372 struct i2c_msg *msgs, u32 last, u32 first) 373 { 374 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 375 u8 *buf; 376 u32 length; 377 u32 addr; 378 u32 addr_2_msb; 379 u32 addr_8_lsb; 380 s32 wrcount; 381 void __iomem *p = adap->pch_base_address; 382 383 length = msgs->len; 384 buf = msgs->buf; 385 addr = msgs->addr; 386 387 /* enable master tx */ 388 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 389 390 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL), 391 length); 392 393 if (first) { 394 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 395 return -ETIME; 396 } 397 398 if (msgs->flags & I2C_M_TEN) { 399 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); 400 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 401 if (first) 402 pch_i2c_start(adap); 403 if (pch_i2c_wait_for_xfer_complete(adap) == 0 && 404 pch_i2c_getack(adap) == 0) { 405 addr_8_lsb = (addr & I2C_ADDR_MSK); 406 iowrite32(addr_8_lsb, p + PCH_I2CDR); 407 } else { 408 pch_i2c_stop(adap); 409 return -ETIME; 410 } 411 } else { 412 /* set 7 bit slave address and R/W bit as 0 */ 413 iowrite32(addr << 1, p + PCH_I2CDR); 414 if (first) 415 pch_i2c_start(adap); 416 } 417 418 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 419 (pch_i2c_getack(adap) == 0)) { 420 for (wrcount = 0; wrcount < length; ++wrcount) { 421 /* write buffer value to I2C data register */ 422 iowrite32(buf[wrcount], p + PCH_I2CDR); 423 pch_dbg(adap, "writing %x to Data register\n", 424 buf[wrcount]); 425 426 if (pch_i2c_wait_for_xfer_complete(adap) != 0) 427 return -ETIME; 428 429 if (pch_i2c_getack(adap)) 430 return -EIO; 431 } 432 433 /* check if this is the last message */ 434 if (last) 435 pch_i2c_stop(adap); 436 else 437 pch_i2c_repstart(adap); 438 } else { 439 pch_i2c_stop(adap); 440 return -EIO; 441 } 442 443 pch_dbg(adap, "return=%d\n", wrcount); 444 445 return wrcount; 446 } 447 448 /** 449 * pch_i2c_sendack() - send ACK 450 * @adap: Pointer to struct i2c_algo_pch_data. 451 */ 452 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap) 453 { 454 void __iomem *p = adap->pch_base_address; 455 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 456 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 457 } 458 459 /** 460 * pch_i2c_sendnack() - send NACK 461 * @adap: Pointer to struct i2c_algo_pch_data. 462 */ 463 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap) 464 { 465 void __iomem *p = adap->pch_base_address; 466 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 467 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 468 } 469 470 /** 471 * pch_i2c_readbytes() - read data from I2C bus in normal mode. 472 * @i2c_adap: Pointer to the struct i2c_adapter. 473 * @msgs: Pointer to i2c_msg structure. 474 * @last: specifies whether last message or not. 475 * @first: specifies whether first message or not. 476 */ 477 s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 478 u32 last, u32 first) 479 { 480 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 481 482 u8 *buf; 483 u32 count; 484 u32 length; 485 u32 addr; 486 u32 addr_2_msb; 487 void __iomem *p = adap->pch_base_address; 488 489 length = msgs->len; 490 buf = msgs->buf; 491 addr = msgs->addr; 492 493 /* enable master reception */ 494 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 495 496 if (first) { 497 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 498 return -ETIME; 499 } 500 501 if (msgs->flags & I2C_M_TEN) { 502 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD)); 503 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 504 505 } else { 506 /* 7 address bits + R/W bit */ 507 addr = (((addr) << 1) | (I2C_RD)); 508 iowrite32(addr, p + PCH_I2CDR); 509 } 510 511 /* check if it is the first message */ 512 if (first) 513 pch_i2c_start(adap); 514 515 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 516 (pch_i2c_getack(adap) == 0)) { 517 pch_dbg(adap, "return %d\n", 0); 518 519 if (length == 0) { 520 pch_i2c_stop(adap); 521 ioread32(p + PCH_I2CDR); /* Dummy read needs */ 522 523 count = length; 524 } else { 525 int read_index; 526 int loop; 527 pch_i2c_sendack(adap); 528 529 /* Dummy read */ 530 for (loop = 1, read_index = 0; loop < length; loop++) { 531 buf[read_index] = ioread32(p + PCH_I2CDR); 532 533 if (loop != 1) 534 read_index++; 535 536 if (pch_i2c_wait_for_xfer_complete(adap) != 0) { 537 pch_i2c_stop(adap); 538 return -ETIME; 539 } 540 } /* end for */ 541 542 pch_i2c_sendnack(adap); 543 544 buf[read_index] = ioread32(p + PCH_I2CDR); 545 546 if (length != 1) 547 read_index++; 548 549 if (pch_i2c_wait_for_xfer_complete(adap) == 0) { 550 if (last) 551 pch_i2c_stop(adap); 552 else 553 pch_i2c_repstart(adap); 554 555 buf[read_index++] = ioread32(p + PCH_I2CDR); 556 count = read_index; 557 } else { 558 count = -ETIME; 559 } 560 561 } 562 } else { 563 count = -ETIME; 564 pch_i2c_stop(adap); 565 } 566 567 return count; 568 } 569 570 /** 571 * pch_i2c_cb_ch0() - Interrupt handler Call back function 572 * @adap: Pointer to struct i2c_algo_pch_data. 573 */ 574 static void pch_i2c_cb_ch0(struct i2c_algo_pch_data *adap) 575 { 576 u32 sts; 577 void __iomem *p = adap->pch_base_address; 578 579 sts = ioread32(p + PCH_I2CSR); 580 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT); 581 if (sts & I2CMAL_BIT) 582 adap->pch_event_flag |= I2CMAL_EVENT; 583 584 if (sts & I2CMCF_BIT) 585 adap->pch_event_flag |= I2CMCF_EVENT; 586 587 /* clear the applicable bits */ 588 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts); 589 590 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 591 592 wake_up(&pch_event); 593 } 594 595 /** 596 * pch_i2c_handler() - interrupt handler for the PCH I2C controller 597 * @irq: irq number. 598 * @pData: cookie passed back to the handler function. 599 */ 600 static irqreturn_t pch_i2c_handler(int irq, void *pData) 601 { 602 s32 reg_val; 603 604 struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData; 605 void __iomem *p = adap_data->pch_base_address; 606 u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE); 607 608 if (mode != NORMAL_MODE) { 609 pch_err(adap_data, "I2C mode is not supported\n"); 610 return IRQ_NONE; 611 } 612 613 reg_val = ioread32(p + PCH_I2CSR); 614 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) 615 pch_i2c_cb_ch0(adap_data); 616 else 617 return IRQ_NONE; 618 619 return IRQ_HANDLED; 620 } 621 622 /** 623 * pch_i2c_xfer() - Reading adnd writing data through I2C bus 624 * @i2c_adap: Pointer to the struct i2c_adapter. 625 * @msgs: Pointer to i2c_msg structure. 626 * @num: number of messages. 627 */ 628 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap, 629 struct i2c_msg *msgs, s32 num) 630 { 631 struct i2c_msg *pmsg; 632 u32 i = 0; 633 u32 status; 634 u32 msglen; 635 u32 subaddrlen; 636 s32 ret; 637 638 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 639 640 ret = mutex_lock_interruptible(&pch_mutex); 641 if (ret) 642 return -ERESTARTSYS; 643 644 if (adap->p_adapter_info->pch_i2c_suspended) { 645 mutex_unlock(&pch_mutex); 646 return -EBUSY; 647 } 648 649 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n", 650 adap->p_adapter_info->pch_i2c_suspended); 651 /* transfer not completed */ 652 adap->pch_i2c_xfer_in_progress = true; 653 654 pmsg = &msgs[0]; 655 pmsg->flags |= adap->pch_buff_mode_en; 656 status = pmsg->flags; 657 pch_dbg(adap, 658 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status); 659 /* calculate sub address length and message length */ 660 /* these are applicable only for buffer mode */ 661 subaddrlen = pmsg->buf[0]; 662 /* calculate actual message length excluding 663 * the sub address fields */ 664 msglen = (pmsg->len) - (subaddrlen + 1); 665 if (status & (I2C_M_RD)) { 666 pch_dbg(adap, "invoking pch_i2c_readbytes\n"); 667 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num), 668 (i == 0)); 669 } else { 670 pch_dbg(adap, "invoking pch_i2c_writebytes\n"); 671 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num), 672 (i == 0)); 673 } 674 675 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */ 676 677 mutex_unlock(&pch_mutex); 678 679 return ret; 680 } 681 682 /** 683 * pch_i2c_func() - return the functionality of the I2C driver 684 * @adap: Pointer to struct i2c_algo_pch_data. 685 */ 686 static u32 pch_i2c_func(struct i2c_adapter *adap) 687 { 688 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 689 } 690 691 static struct i2c_algorithm pch_algorithm = { 692 .master_xfer = pch_i2c_xfer, 693 .functionality = pch_i2c_func 694 }; 695 696 /** 697 * pch_i2c_disbl_int() - Disable PCH I2C interrupts 698 * @adap: Pointer to struct i2c_algo_pch_data. 699 */ 700 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap) 701 { 702 void __iomem *p = adap->pch_base_address; 703 704 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL); 705 706 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK); 707 708 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK); 709 } 710 711 static int __devinit pch_i2c_probe(struct pci_dev *pdev, 712 const struct pci_device_id *id) 713 { 714 void __iomem *base_addr; 715 s32 ret; 716 struct adapter_info *adap_info; 717 718 pch_pci_dbg(pdev, "Entered.\n"); 719 720 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL); 721 if (adap_info == NULL) { 722 pch_pci_err(pdev, "Memory allocation FAILED\n"); 723 return -ENOMEM; 724 } 725 726 ret = pci_enable_device(pdev); 727 if (ret) { 728 pch_pci_err(pdev, "pci_enable_device FAILED\n"); 729 goto err_pci_enable; 730 } 731 732 ret = pci_request_regions(pdev, KBUILD_MODNAME); 733 if (ret) { 734 pch_pci_err(pdev, "pci_request_regions FAILED\n"); 735 goto err_pci_req; 736 } 737 738 base_addr = pci_iomap(pdev, 1, 0); 739 740 if (base_addr == NULL) { 741 pch_pci_err(pdev, "pci_iomap FAILED\n"); 742 ret = -ENOMEM; 743 goto err_pci_iomap; 744 } 745 746 adap_info->pch_i2c_suspended = false; 747 748 adap_info->pch_data.p_adapter_info = adap_info; 749 750 adap_info->pch_data.pch_adapter.owner = THIS_MODULE; 751 adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON; 752 strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME); 753 adap_info->pch_data.pch_adapter.algo = &pch_algorithm; 754 adap_info->pch_data.pch_adapter.algo_data = 755 &adap_info->pch_data; 756 757 /* (i * 0x80) + base_addr; */ 758 adap_info->pch_data.pch_base_address = base_addr; 759 760 adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev; 761 762 ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter)); 763 764 if (ret) { 765 pch_pci_err(pdev, "i2c_add_adapter FAILED\n"); 766 goto err_i2c_add_adapter; 767 } 768 769 pch_i2c_init(&adap_info->pch_data); 770 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED, 771 KBUILD_MODNAME, &adap_info->pch_data); 772 if (ret) { 773 pch_pci_err(pdev, "request_irq FAILED\n"); 774 goto err_request_irq; 775 } 776 777 pci_set_drvdata(pdev, adap_info); 778 pch_pci_dbg(pdev, "returns %d.\n", ret); 779 return 0; 780 781 err_request_irq: 782 i2c_del_adapter(&(adap_info->pch_data.pch_adapter)); 783 err_i2c_add_adapter: 784 pci_iounmap(pdev, base_addr); 785 err_pci_iomap: 786 pci_release_regions(pdev); 787 err_pci_req: 788 pci_disable_device(pdev); 789 err_pci_enable: 790 kfree(adap_info); 791 return ret; 792 } 793 794 static void __devexit pch_i2c_remove(struct pci_dev *pdev) 795 { 796 struct adapter_info *adap_info = pci_get_drvdata(pdev); 797 798 pch_i2c_disbl_int(&adap_info->pch_data); 799 free_irq(pdev->irq, &adap_info->pch_data); 800 i2c_del_adapter(&(adap_info->pch_data.pch_adapter)); 801 802 if (adap_info->pch_data.pch_base_address) { 803 pci_iounmap(pdev, adap_info->pch_data.pch_base_address); 804 adap_info->pch_data.pch_base_address = 0; 805 } 806 807 pci_set_drvdata(pdev, NULL); 808 809 pci_release_regions(pdev); 810 811 pci_disable_device(pdev); 812 kfree(adap_info); 813 } 814 815 #ifdef CONFIG_PM 816 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state) 817 { 818 int ret; 819 struct adapter_info *adap_info = pci_get_drvdata(pdev); 820 void __iomem *p = adap_info->pch_data.pch_base_address; 821 822 adap_info->pch_i2c_suspended = true; 823 824 while ((adap_info->pch_data.pch_i2c_xfer_in_progress)) { 825 /* Wait until all channel transfers are completed */ 826 msleep(20); 827 } 828 /* Disable the i2c interrupts */ 829 pch_i2c_disbl_int(&adap_info->pch_data); 830 831 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x " 832 "invoked function pch_i2c_disbl_int successfully\n", 833 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA), 834 ioread32(p + PCH_I2CESRSTA)); 835 836 ret = pci_save_state(pdev); 837 838 if (ret) { 839 pch_pci_err(pdev, "pci_save_state\n"); 840 return ret; 841 } 842 843 pci_enable_wake(pdev, PCI_D3hot, 0); 844 pci_disable_device(pdev); 845 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 846 847 return 0; 848 } 849 850 static int pch_i2c_resume(struct pci_dev *pdev) 851 { 852 struct adapter_info *adap_info = pci_get_drvdata(pdev); 853 854 pci_set_power_state(pdev, PCI_D0); 855 pci_restore_state(pdev); 856 857 if (pci_enable_device(pdev) < 0) { 858 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n"); 859 return -EIO; 860 } 861 862 pci_enable_wake(pdev, PCI_D3hot, 0); 863 864 pch_i2c_init(&adap_info->pch_data); 865 866 adap_info->pch_i2c_suspended = false; 867 868 return 0; 869 } 870 #else 871 #define pch_i2c_suspend NULL 872 #define pch_i2c_resume NULL 873 #endif 874 875 static struct pci_driver pch_pcidriver = { 876 .name = KBUILD_MODNAME, 877 .id_table = pch_pcidev_id, 878 .probe = pch_i2c_probe, 879 .remove = __devexit_p(pch_i2c_remove), 880 .suspend = pch_i2c_suspend, 881 .resume = pch_i2c_resume 882 }; 883 884 static int __init pch_pci_init(void) 885 { 886 return pci_register_driver(&pch_pcidriver); 887 } 888 module_init(pch_pci_init); 889 890 static void __exit pch_pci_exit(void) 891 { 892 pci_unregister_driver(&pch_pcidriver); 893 } 894 module_exit(pch_pci_exit); 895 896 MODULE_DESCRIPTION("PCH I2C PCI Driver"); 897 MODULE_LICENSE("GPL"); 898 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>"); 899 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR)); 900 module_param(pch_clk, int, (S_IRUSR | S_IWUSR)); 901