xref: /openbmc/linux/drivers/i2c/busses/i2c-eg20t.c (revision ea1558ce)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/i2c.h>
11 #include <linux/fs.h>
12 #include <linux/io.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/pci.h>
17 #include <linux/mutex.h>
18 #include <linux/ktime.h>
19 #include <linux/slab.h>
20 
21 #define PCH_EVENT_SET	0	/* I2C Interrupt Event Set Status */
22 #define PCH_EVENT_NONE	1	/* I2C Interrupt Event Clear Status */
23 #define PCH_MAX_CLK		100000	/* Maximum Clock speed in MHz */
24 #define PCH_BUFFER_MODE_ENABLE	0x0002	/* flag for Buffer mode enable */
25 #define PCH_EEPROM_SW_RST_MODE_ENABLE	0x0008	/* EEPROM SW RST enable flag */
26 
27 #define PCH_I2CSADR	0x00	/* I2C slave address register */
28 #define PCH_I2CCTL	0x04	/* I2C control register */
29 #define PCH_I2CSR	0x08	/* I2C status register */
30 #define PCH_I2CDR	0x0C	/* I2C data register */
31 #define PCH_I2CMON	0x10	/* I2C bus monitor register */
32 #define PCH_I2CBC	0x14	/* I2C bus transfer rate setup counter */
33 #define PCH_I2CMOD	0x18	/* I2C mode register */
34 #define PCH_I2CBUFSLV	0x1C	/* I2C buffer mode slave address register */
35 #define PCH_I2CBUFSUB	0x20	/* I2C buffer mode subaddress register */
36 #define PCH_I2CBUFFOR	0x24	/* I2C buffer mode format register */
37 #define PCH_I2CBUFCTL	0x28	/* I2C buffer mode control register */
38 #define PCH_I2CBUFMSK	0x2C	/* I2C buffer mode interrupt mask register */
39 #define PCH_I2CBUFSTA	0x30	/* I2C buffer mode status register */
40 #define PCH_I2CBUFLEV	0x34	/* I2C buffer mode level register */
41 #define PCH_I2CESRFOR	0x38	/* EEPROM software reset mode format register */
42 #define PCH_I2CESRCTL	0x3C	/* EEPROM software reset mode ctrl register */
43 #define PCH_I2CESRMSK	0x40	/* EEPROM software reset mode */
44 #define PCH_I2CESRSTA	0x44	/* EEPROM software reset mode status register */
45 #define PCH_I2CTMR	0x48	/* I2C timer register */
46 #define PCH_I2CSRST	0xFC	/* I2C reset register */
47 #define PCH_I2CNF	0xF8	/* I2C noise filter register */
48 
49 #define BUS_IDLE_TIMEOUT	20
50 #define PCH_I2CCTL_I2CMEN	0x0080
51 #define TEN_BIT_ADDR_DEFAULT	0xF000
52 #define TEN_BIT_ADDR_MASK	0xF0
53 #define PCH_START		0x0020
54 #define PCH_RESTART		0x0004
55 #define PCH_ESR_START		0x0001
56 #define PCH_BUFF_START		0x1
57 #define PCH_REPSTART		0x0004
58 #define PCH_ACK			0x0008
59 #define PCH_GETACK		0x0001
60 #define CLR_REG			0x0
61 #define I2C_RD			0x1
62 #define I2CMCF_BIT		0x0080
63 #define I2CMIF_BIT		0x0002
64 #define I2CMAL_BIT		0x0010
65 #define I2CBMFI_BIT		0x0001
66 #define I2CBMAL_BIT		0x0002
67 #define I2CBMNA_BIT		0x0004
68 #define I2CBMTO_BIT		0x0008
69 #define I2CBMIS_BIT		0x0010
70 #define I2CESRFI_BIT		0X0001
71 #define I2CESRTO_BIT		0x0002
72 #define I2CESRFIIE_BIT		0x1
73 #define I2CESRTOIE_BIT		0x2
74 #define I2CBMDZ_BIT		0x0040
75 #define I2CBMAG_BIT		0x0020
76 #define I2CMBB_BIT		0x0020
77 #define BUFFER_MODE_MASK	(I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
78 				I2CBMTO_BIT | I2CBMIS_BIT)
79 #define I2C_ADDR_MSK		0xFF
80 #define I2C_MSB_2B_MSK		0x300
81 #define FAST_MODE_CLK		400
82 #define FAST_MODE_EN		0x0001
83 #define SUB_ADDR_LEN_MAX	4
84 #define BUF_LEN_MAX		32
85 #define PCH_BUFFER_MODE		0x1
86 #define EEPROM_SW_RST_MODE	0x0002
87 #define NORMAL_INTR_ENBL	0x0300
88 #define EEPROM_RST_INTR_ENBL	(I2CESRFIIE_BIT | I2CESRTOIE_BIT)
89 #define EEPROM_RST_INTR_DISBL	0x0
90 #define BUFFER_MODE_INTR_ENBL	0x001F
91 #define BUFFER_MODE_INTR_DISBL	0x0
92 #define NORMAL_MODE		0x0
93 #define BUFFER_MODE		0x1
94 #define EEPROM_SR_MODE		0x2
95 #define I2C_TX_MODE		0x0010
96 #define PCH_BUF_TX		0xFFF7
97 #define PCH_BUF_RD		0x0008
98 #define I2C_ERROR_MASK	(I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
99 			I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
100 #define I2CMAL_EVENT		0x0001
101 #define I2CMCF_EVENT		0x0002
102 #define I2CBMFI_EVENT		0x0004
103 #define I2CBMAL_EVENT		0x0008
104 #define I2CBMNA_EVENT		0x0010
105 #define I2CBMTO_EVENT		0x0020
106 #define I2CBMIS_EVENT		0x0040
107 #define I2CESRFI_EVENT		0x0080
108 #define I2CESRTO_EVENT		0x0100
109 #define PCI_DEVICE_ID_PCH_I2C	0x8817
110 
111 #define pch_dbg(adap, fmt, arg...)  \
112 	dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
113 
114 #define pch_err(adap, fmt, arg...)  \
115 	dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
116 
117 #define pch_pci_err(pdev, fmt, arg...)  \
118 	dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
119 
120 #define pch_pci_dbg(pdev, fmt, arg...)  \
121 	dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
122 
123 /*
124 Set the number of I2C instance max
125 Intel EG20T PCH :		1ch
126 LAPIS Semiconductor ML7213 IOH :	2ch
127 LAPIS Semiconductor ML7831 IOH :	1ch
128 */
129 #define PCH_I2C_MAX_DEV			2
130 
131 /**
132  * struct i2c_algo_pch_data - for I2C driver functionalities
133  * @pch_adapter:		stores the reference to i2c_adapter structure
134  * @p_adapter_info:		stores the reference to adapter_info structure
135  * @pch_base_address:		specifies the remapped base address
136  * @pch_buff_mode_en:		specifies if buffer mode is enabled
137  * @pch_event_flag:		specifies occurrence of interrupt events
138  * @pch_i2c_xfer_in_progress:	specifies whether the transfer is completed
139  */
140 struct i2c_algo_pch_data {
141 	struct i2c_adapter pch_adapter;
142 	struct adapter_info *p_adapter_info;
143 	void __iomem *pch_base_address;
144 	int pch_buff_mode_en;
145 	u32 pch_event_flag;
146 	bool pch_i2c_xfer_in_progress;
147 };
148 
149 /**
150  * struct adapter_info - This structure holds the adapter information for the
151  *			 PCH i2c controller
152  * @pch_data:		stores a list of i2c_algo_pch_data
153  * @pch_i2c_suspended:	specifies whether the system is suspended or not
154  *			perhaps with more lines and words.
155  * @ch_num:		specifies the number of i2c instance
156  *
157  * pch_data has as many elements as maximum I2C channels
158  */
159 struct adapter_info {
160 	struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
161 	bool pch_i2c_suspended;
162 	int ch_num;
163 };
164 
165 
166 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
167 static int pch_clk = 50000;	/* specifies I2C clock speed in KHz */
168 static wait_queue_head_t pch_event;
169 static DEFINE_MUTEX(pch_mutex);
170 
171 /* Definition for ML7213 by LAPIS Semiconductor */
172 #define PCI_DEVICE_ID_ML7213_I2C	0x802D
173 #define PCI_DEVICE_ID_ML7223_I2C	0x8010
174 #define PCI_DEVICE_ID_ML7831_I2C	0x8817
175 
176 static const struct pci_device_id pch_pcidev_id[] = {
177 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
178 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
179 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
180 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
181 	{0,}
182 };
183 MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
184 
185 static irqreturn_t pch_i2c_handler(int irq, void *pData);
186 
pch_setbit(void __iomem * addr,u32 offset,u32 bitmask)187 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
188 {
189 	u32 val;
190 	val = ioread32(addr + offset);
191 	val |= bitmask;
192 	iowrite32(val, addr + offset);
193 }
194 
pch_clrbit(void __iomem * addr,u32 offset,u32 bitmask)195 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
196 {
197 	u32 val;
198 	val = ioread32(addr + offset);
199 	val &= (~bitmask);
200 	iowrite32(val, addr + offset);
201 }
202 
203 /**
204  * pch_i2c_init() - hardware initialization of I2C module
205  * @adap:	Pointer to struct i2c_algo_pch_data.
206  */
pch_i2c_init(struct i2c_algo_pch_data * adap)207 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
208 {
209 	void __iomem *p = adap->pch_base_address;
210 	u32 pch_i2cbc;
211 	u32 pch_i2ctmr;
212 	u32 reg_value;
213 
214 	/* reset I2C controller */
215 	iowrite32(0x01, p + PCH_I2CSRST);
216 	msleep(20);
217 	iowrite32(0x0, p + PCH_I2CSRST);
218 
219 	/* Initialize I2C registers */
220 	iowrite32(0x21, p + PCH_I2CNF);
221 
222 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
223 
224 	if (pch_i2c_speed != 400)
225 		pch_i2c_speed = 100;
226 
227 	reg_value = PCH_I2CCTL_I2CMEN;
228 	if (pch_i2c_speed == FAST_MODE_CLK) {
229 		reg_value |= FAST_MODE_EN;
230 		pch_dbg(adap, "Fast mode enabled\n");
231 	}
232 
233 	if (pch_clk > PCH_MAX_CLK)
234 		pch_clk = 62500;
235 
236 	pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
237 	/* Set transfer speed in I2CBC */
238 	iowrite32(pch_i2cbc, p + PCH_I2CBC);
239 
240 	pch_i2ctmr = (pch_clk) / 8;
241 	iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
242 
243 	reg_value |= NORMAL_INTR_ENBL;	/* Enable interrupts in normal mode */
244 	iowrite32(reg_value, p + PCH_I2CCTL);
245 
246 	pch_dbg(adap,
247 		"I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
248 		ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
249 
250 	init_waitqueue_head(&pch_event);
251 }
252 
253 /**
254  * pch_i2c_wait_for_bus_idle() - check the status of bus.
255  * @adap:	Pointer to struct i2c_algo_pch_data.
256  * @timeout:	waiting time counter (ms).
257  */
pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data * adap,s32 timeout)258 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
259 				     s32 timeout)
260 {
261 	void __iomem *p = adap->pch_base_address;
262 	int schedule = 0;
263 	unsigned long end = jiffies + msecs_to_jiffies(timeout);
264 
265 	while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
266 		if (time_after(jiffies, end)) {
267 			pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
268 			pch_err(adap, "%s: Timeout Error.return%d\n",
269 					__func__, -ETIME);
270 			pch_i2c_init(adap);
271 
272 			return -ETIME;
273 		}
274 
275 		if (!schedule)
276 			/* Retry after some usecs */
277 			udelay(5);
278 		else
279 			/* Wait a bit more without consuming CPU */
280 			usleep_range(20, 1000);
281 
282 		schedule = 1;
283 	}
284 
285 	return 0;
286 }
287 
288 /**
289  * pch_i2c_start() - Generate I2C start condition in normal mode.
290  * @adap:	Pointer to struct i2c_algo_pch_data.
291  *
292  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
293  */
pch_i2c_start(struct i2c_algo_pch_data * adap)294 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
295 {
296 	void __iomem *p = adap->pch_base_address;
297 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
298 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
299 }
300 
301 /**
302  * pch_i2c_stop() - generate stop condition in normal mode.
303  * @adap:	Pointer to struct i2c_algo_pch_data.
304  */
pch_i2c_stop(struct i2c_algo_pch_data * adap)305 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
306 {
307 	void __iomem *p = adap->pch_base_address;
308 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
309 	/* clear the start bit */
310 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
311 }
312 
pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data * adap)313 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
314 {
315 	long ret;
316 	void __iomem *p = adap->pch_base_address;
317 
318 	ret = wait_event_timeout(pch_event,
319 			(adap->pch_event_flag != 0), msecs_to_jiffies(1000));
320 	if (!ret) {
321 		pch_err(adap, "%s:wait-event timeout\n", __func__);
322 		adap->pch_event_flag = 0;
323 		pch_i2c_stop(adap);
324 		pch_i2c_init(adap);
325 		return -ETIMEDOUT;
326 	}
327 
328 	if (adap->pch_event_flag & I2C_ERROR_MASK) {
329 		pch_err(adap, "Lost Arbitration\n");
330 		adap->pch_event_flag = 0;
331 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
332 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
333 		pch_i2c_init(adap);
334 		return -EAGAIN;
335 	}
336 
337 	adap->pch_event_flag = 0;
338 
339 	if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
340 		pch_dbg(adap, "Receive NACK for slave address setting\n");
341 		return -ENXIO;
342 	}
343 
344 	return 0;
345 }
346 
347 /**
348  * pch_i2c_repstart() - generate repeated start condition in normal mode
349  * @adap:	Pointer to struct i2c_algo_pch_data.
350  */
pch_i2c_repstart(struct i2c_algo_pch_data * adap)351 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
352 {
353 	void __iomem *p = adap->pch_base_address;
354 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
355 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
356 }
357 
358 /**
359  * pch_i2c_writebytes() - write data to I2C bus in normal mode
360  * @i2c_adap:	Pointer to the struct i2c_adapter.
361  * @msgs:	Pointer to the i2c message structure.
362  * @last:	specifies whether last message or not.
363  *		In the case of compound mode it will be 1 for last message,
364  *		otherwise 0.
365  * @first:	specifies whether first message or not.
366  *		1 for first message otherwise 0.
367  */
pch_i2c_writebytes(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,u32 last,u32 first)368 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
369 			      struct i2c_msg *msgs, u32 last, u32 first)
370 {
371 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
372 	u8 *buf;
373 	u32 length;
374 	u32 addr;
375 	u32 addr_2_msb;
376 	u32 addr_8_lsb;
377 	s32 wrcount;
378 	s32 rtn;
379 	void __iomem *p = adap->pch_base_address;
380 
381 	length = msgs->len;
382 	buf = msgs->buf;
383 	addr = msgs->addr;
384 
385 	/* enable master tx */
386 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
387 
388 	pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
389 		length);
390 
391 	if (first) {
392 		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
393 			return -ETIME;
394 	}
395 
396 	if (msgs->flags & I2C_M_TEN) {
397 		addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
398 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
399 		if (first)
400 			pch_i2c_start(adap);
401 
402 		rtn = pch_i2c_wait_for_check_xfer(adap);
403 		if (rtn)
404 			return rtn;
405 
406 		addr_8_lsb = (addr & I2C_ADDR_MSK);
407 		iowrite32(addr_8_lsb, p + PCH_I2CDR);
408 	} else {
409 		/* set 7 bit slave address and R/W bit as 0 */
410 		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
411 		if (first)
412 			pch_i2c_start(adap);
413 	}
414 
415 	rtn = pch_i2c_wait_for_check_xfer(adap);
416 	if (rtn)
417 		return rtn;
418 
419 	for (wrcount = 0; wrcount < length; ++wrcount) {
420 		/* write buffer value to I2C data register */
421 		iowrite32(buf[wrcount], p + PCH_I2CDR);
422 		pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
423 
424 		rtn = pch_i2c_wait_for_check_xfer(adap);
425 		if (rtn)
426 			return rtn;
427 
428 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
429 		pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
430 	}
431 
432 	/* check if this is the last message */
433 	if (last)
434 		pch_i2c_stop(adap);
435 	else
436 		pch_i2c_repstart(adap);
437 
438 	pch_dbg(adap, "return=%d\n", wrcount);
439 
440 	return wrcount;
441 }
442 
443 /**
444  * pch_i2c_sendack() - send ACK
445  * @adap:	Pointer to struct i2c_algo_pch_data.
446  */
pch_i2c_sendack(struct i2c_algo_pch_data * adap)447 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
448 {
449 	void __iomem *p = adap->pch_base_address;
450 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
451 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
452 }
453 
454 /**
455  * pch_i2c_sendnack() - send NACK
456  * @adap:	Pointer to struct i2c_algo_pch_data.
457  */
pch_i2c_sendnack(struct i2c_algo_pch_data * adap)458 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
459 {
460 	void __iomem *p = adap->pch_base_address;
461 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
462 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
463 }
464 
465 /**
466  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
467  * @adap:	Pointer to struct i2c_algo_pch_data.
468  *
469  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
470  */
pch_i2c_restart(struct i2c_algo_pch_data * adap)471 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
472 {
473 	void __iomem *p = adap->pch_base_address;
474 	pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
475 	pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
476 }
477 
478 /**
479  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
480  * @i2c_adap:	Pointer to the struct i2c_adapter.
481  * @msgs:	Pointer to i2c_msg structure.
482  * @last:	specifies whether last message or not.
483  * @first:	specifies whether first message or not.
484  */
pch_i2c_readbytes(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,u32 last,u32 first)485 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
486 			     u32 last, u32 first)
487 {
488 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
489 
490 	u8 *buf;
491 	u32 count;
492 	u32 length;
493 	u32 addr;
494 	u32 addr_2_msb;
495 	u32 addr_8_lsb;
496 	void __iomem *p = adap->pch_base_address;
497 	s32 rtn;
498 
499 	length = msgs->len;
500 	buf = msgs->buf;
501 	addr = msgs->addr;
502 
503 	/* enable master reception */
504 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
505 
506 	if (first) {
507 		if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
508 			return -ETIME;
509 	}
510 
511 	if (msgs->flags & I2C_M_TEN) {
512 		addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
513 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
514 		if (first)
515 			pch_i2c_start(adap);
516 
517 		rtn = pch_i2c_wait_for_check_xfer(adap);
518 		if (rtn)
519 			return rtn;
520 
521 		addr_8_lsb = (addr & I2C_ADDR_MSK);
522 		iowrite32(addr_8_lsb, p + PCH_I2CDR);
523 
524 		pch_i2c_restart(adap);
525 
526 		rtn = pch_i2c_wait_for_check_xfer(adap);
527 		if (rtn)
528 			return rtn;
529 
530 		addr_2_msb |= I2C_RD;
531 		iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
532 	} else {
533 		/* 7 address bits + R/W bit */
534 		iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
535 	}
536 
537 	/* check if it is the first message */
538 	if (first)
539 		pch_i2c_start(adap);
540 
541 	rtn = pch_i2c_wait_for_check_xfer(adap);
542 	if (rtn)
543 		return rtn;
544 
545 	if (length == 0) {
546 		pch_i2c_stop(adap);
547 		ioread32(p + PCH_I2CDR); /* Dummy read needs */
548 
549 		count = length;
550 	} else {
551 		int read_index;
552 		int loop;
553 		pch_i2c_sendack(adap);
554 
555 		/* Dummy read */
556 		for (loop = 1, read_index = 0; loop < length; loop++) {
557 			buf[read_index] = ioread32(p + PCH_I2CDR);
558 
559 			if (loop != 1)
560 				read_index++;
561 
562 			rtn = pch_i2c_wait_for_check_xfer(adap);
563 			if (rtn)
564 				return rtn;
565 		}	/* end for */
566 
567 		pch_i2c_sendnack(adap);
568 
569 		buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
570 
571 		if (length != 1)
572 			read_index++;
573 
574 		rtn = pch_i2c_wait_for_check_xfer(adap);
575 		if (rtn)
576 			return rtn;
577 
578 		if (last)
579 			pch_i2c_stop(adap);
580 		else
581 			pch_i2c_repstart(adap);
582 
583 		buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
584 		count = read_index;
585 	}
586 
587 	return count;
588 }
589 
590 /**
591  * pch_i2c_cb() - Interrupt handler Call back function
592  * @adap:	Pointer to struct i2c_algo_pch_data.
593  */
pch_i2c_cb(struct i2c_algo_pch_data * adap)594 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
595 {
596 	u32 sts;
597 	void __iomem *p = adap->pch_base_address;
598 
599 	sts = ioread32(p + PCH_I2CSR);
600 	sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
601 	if (sts & I2CMAL_BIT)
602 		adap->pch_event_flag |= I2CMAL_EVENT;
603 
604 	if (sts & I2CMCF_BIT)
605 		adap->pch_event_flag |= I2CMCF_EVENT;
606 
607 	/* clear the applicable bits */
608 	pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
609 
610 	pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
611 
612 	wake_up(&pch_event);
613 }
614 
615 /**
616  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
617  * @irq:	irq number.
618  * @pData:	cookie passed back to the handler function.
619  */
pch_i2c_handler(int irq,void * pData)620 static irqreturn_t pch_i2c_handler(int irq, void *pData)
621 {
622 	u32 reg_val;
623 	int flag;
624 	int i;
625 	struct adapter_info *adap_info = pData;
626 	void __iomem *p;
627 	u32 mode;
628 
629 	for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
630 		p = adap_info->pch_data[i].pch_base_address;
631 		mode = ioread32(p + PCH_I2CMOD);
632 		mode &= BUFFER_MODE | EEPROM_SR_MODE;
633 		if (mode != NORMAL_MODE) {
634 			pch_err(adap_info->pch_data,
635 				"I2C-%d mode(%d) is not supported\n", mode, i);
636 			continue;
637 		}
638 		reg_val = ioread32(p + PCH_I2CSR);
639 		if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
640 			pch_i2c_cb(&adap_info->pch_data[i]);
641 			flag = 1;
642 		}
643 	}
644 
645 	return flag ? IRQ_HANDLED : IRQ_NONE;
646 }
647 
648 /**
649  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
650  * @i2c_adap:	Pointer to the struct i2c_adapter.
651  * @msgs:	Pointer to i2c_msg structure.
652  * @num:	number of messages.
653  */
pch_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,s32 num)654 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
655 			struct i2c_msg *msgs, s32 num)
656 {
657 	struct i2c_msg *pmsg;
658 	u32 i = 0;
659 	u32 status;
660 	s32 ret;
661 
662 	struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
663 
664 	ret = mutex_lock_interruptible(&pch_mutex);
665 	if (ret)
666 		return ret;
667 
668 	if (adap->p_adapter_info->pch_i2c_suspended) {
669 		mutex_unlock(&pch_mutex);
670 		return -EBUSY;
671 	}
672 
673 	pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
674 		adap->p_adapter_info->pch_i2c_suspended);
675 	/* transfer not completed */
676 	adap->pch_i2c_xfer_in_progress = true;
677 
678 	for (i = 0; i < num && ret >= 0; i++) {
679 		pmsg = &msgs[i];
680 		pmsg->flags |= adap->pch_buff_mode_en;
681 		status = pmsg->flags;
682 		pch_dbg(adap,
683 			"After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
684 
685 		if ((status & (I2C_M_RD)) != false) {
686 			ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
687 						(i == 0));
688 		} else {
689 			ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
690 						 (i == 0));
691 		}
692 	}
693 
694 	adap->pch_i2c_xfer_in_progress = false;	/* transfer completed */
695 
696 	mutex_unlock(&pch_mutex);
697 
698 	return (ret < 0) ? ret : num;
699 }
700 
701 /**
702  * pch_i2c_func() - return the functionality of the I2C driver
703  * @adap:	Pointer to struct i2c_algo_pch_data.
704  */
pch_i2c_func(struct i2c_adapter * adap)705 static u32 pch_i2c_func(struct i2c_adapter *adap)
706 {
707 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
708 }
709 
710 static const struct i2c_algorithm pch_algorithm = {
711 	.master_xfer = pch_i2c_xfer,
712 	.functionality = pch_i2c_func
713 };
714 
715 /**
716  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
717  * @adap:	Pointer to struct i2c_algo_pch_data.
718  */
pch_i2c_disbl_int(struct i2c_algo_pch_data * adap)719 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
720 {
721 	void __iomem *p = adap->pch_base_address;
722 
723 	pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
724 
725 	iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
726 
727 	iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
728 }
729 
pch_i2c_probe(struct pci_dev * pdev,const struct pci_device_id * id)730 static int pch_i2c_probe(struct pci_dev *pdev,
731 				   const struct pci_device_id *id)
732 {
733 	void __iomem *base_addr;
734 	int ret;
735 	int i, j;
736 	struct adapter_info *adap_info;
737 	struct i2c_adapter *pch_adap;
738 
739 	pch_pci_dbg(pdev, "Entered.\n");
740 
741 	adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
742 	if (adap_info == NULL)
743 		return -ENOMEM;
744 
745 	ret = pci_enable_device(pdev);
746 	if (ret) {
747 		pch_pci_err(pdev, "pci_enable_device FAILED\n");
748 		goto err_pci_enable;
749 	}
750 
751 	ret = pci_request_regions(pdev, KBUILD_MODNAME);
752 	if (ret) {
753 		pch_pci_err(pdev, "pci_request_regions FAILED\n");
754 		goto err_pci_req;
755 	}
756 
757 	base_addr = pci_iomap(pdev, 1, 0);
758 
759 	if (base_addr == NULL) {
760 		pch_pci_err(pdev, "pci_iomap FAILED\n");
761 		ret = -ENOMEM;
762 		goto err_pci_iomap;
763 	}
764 
765 	/* Set the number of I2C channel instance */
766 	adap_info->ch_num = id->driver_data;
767 
768 	for (i = 0; i < adap_info->ch_num; i++) {
769 		pch_adap = &adap_info->pch_data[i].pch_adapter;
770 		adap_info->pch_i2c_suspended = false;
771 
772 		adap_info->pch_data[i].p_adapter_info = adap_info;
773 
774 		pch_adap->owner = THIS_MODULE;
775 		pch_adap->class = I2C_CLASS_HWMON;
776 		strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
777 		pch_adap->algo = &pch_algorithm;
778 		pch_adap->algo_data = &adap_info->pch_data[i];
779 
780 		/* base_addr + offset; */
781 		adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
782 
783 		pch_adap->dev.of_node = pdev->dev.of_node;
784 		pch_adap->dev.parent = &pdev->dev;
785 	}
786 
787 	ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
788 		  KBUILD_MODNAME, adap_info);
789 	if (ret) {
790 		pch_pci_err(pdev, "request_irq FAILED\n");
791 		goto err_request_irq;
792 	}
793 
794 	for (i = 0; i < adap_info->ch_num; i++) {
795 		pch_adap = &adap_info->pch_data[i].pch_adapter;
796 
797 		pch_i2c_init(&adap_info->pch_data[i]);
798 
799 		pch_adap->nr = i;
800 		ret = i2c_add_numbered_adapter(pch_adap);
801 		if (ret) {
802 			pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
803 			goto err_add_adapter;
804 		}
805 	}
806 
807 	pci_set_drvdata(pdev, adap_info);
808 	pch_pci_dbg(pdev, "returns %d.\n", ret);
809 	return 0;
810 
811 err_add_adapter:
812 	for (j = 0; j < i; j++)
813 		i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
814 	free_irq(pdev->irq, adap_info);
815 err_request_irq:
816 	pci_iounmap(pdev, base_addr);
817 err_pci_iomap:
818 	pci_release_regions(pdev);
819 err_pci_req:
820 	pci_disable_device(pdev);
821 err_pci_enable:
822 	kfree(adap_info);
823 	return ret;
824 }
825 
pch_i2c_remove(struct pci_dev * pdev)826 static void pch_i2c_remove(struct pci_dev *pdev)
827 {
828 	int i;
829 	struct adapter_info *adap_info = pci_get_drvdata(pdev);
830 
831 	free_irq(pdev->irq, adap_info);
832 
833 	for (i = 0; i < adap_info->ch_num; i++) {
834 		pch_i2c_disbl_int(&adap_info->pch_data[i]);
835 		i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
836 	}
837 
838 	if (adap_info->pch_data[0].pch_base_address)
839 		pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
840 
841 	for (i = 0; i < adap_info->ch_num; i++)
842 		adap_info->pch_data[i].pch_base_address = NULL;
843 
844 	pci_release_regions(pdev);
845 
846 	pci_disable_device(pdev);
847 	kfree(adap_info);
848 }
849 
pch_i2c_suspend(struct device * dev)850 static int __maybe_unused pch_i2c_suspend(struct device *dev)
851 {
852 	int i;
853 	struct pci_dev *pdev = to_pci_dev(dev);
854 	struct adapter_info *adap_info = pci_get_drvdata(pdev);
855 	void __iomem *p = adap_info->pch_data[0].pch_base_address;
856 
857 	adap_info->pch_i2c_suspended = true;
858 
859 	for (i = 0; i < adap_info->ch_num; i++) {
860 		while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
861 			/* Wait until all channel transfers are completed */
862 			msleep(20);
863 		}
864 	}
865 
866 	/* Disable the i2c interrupts */
867 	for (i = 0; i < adap_info->ch_num; i++)
868 		pch_i2c_disbl_int(&adap_info->pch_data[i]);
869 
870 	pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
871 		"invoked function pch_i2c_disbl_int successfully\n",
872 		ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
873 		ioread32(p + PCH_I2CESRSTA));
874 
875 	return 0;
876 }
877 
pch_i2c_resume(struct device * dev)878 static int __maybe_unused pch_i2c_resume(struct device *dev)
879 {
880 	int i;
881 	struct adapter_info *adap_info = dev_get_drvdata(dev);
882 
883 	for (i = 0; i < adap_info->ch_num; i++)
884 		pch_i2c_init(&adap_info->pch_data[i]);
885 
886 	adap_info->pch_i2c_suspended = false;
887 
888 	return 0;
889 }
890 
891 static SIMPLE_DEV_PM_OPS(pch_i2c_pm_ops, pch_i2c_suspend, pch_i2c_resume);
892 
893 static struct pci_driver pch_pcidriver = {
894 	.name = KBUILD_MODNAME,
895 	.id_table = pch_pcidev_id,
896 	.probe = pch_i2c_probe,
897 	.remove = pch_i2c_remove,
898 	.driver.pm = &pch_i2c_pm_ops,
899 };
900 
901 module_pci_driver(pch_pcidriver);
902 
903 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
904 MODULE_LICENSE("GPL");
905 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
906 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
907 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
908