1 /* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/delay.h> 17 #include <linux/errno.h> 18 #include <linux/i2c.h> 19 #include <linux/fs.h> 20 #include <linux/io.h> 21 #include <linux/types.h> 22 #include <linux/interrupt.h> 23 #include <linux/jiffies.h> 24 #include <linux/pci.h> 25 #include <linux/mutex.h> 26 #include <linux/ktime.h> 27 #include <linux/slab.h> 28 29 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ 30 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ 31 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */ 32 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ 33 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ 34 35 #define PCH_I2CSADR 0x00 /* I2C slave address register */ 36 #define PCH_I2CCTL 0x04 /* I2C control register */ 37 #define PCH_I2CSR 0x08 /* I2C status register */ 38 #define PCH_I2CDR 0x0C /* I2C data register */ 39 #define PCH_I2CMON 0x10 /* I2C bus monitor register */ 40 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */ 41 #define PCH_I2CMOD 0x18 /* I2C mode register */ 42 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */ 43 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */ 44 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */ 45 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */ 46 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */ 47 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */ 48 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */ 49 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */ 50 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */ 51 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */ 52 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */ 53 #define PCH_I2CTMR 0x48 /* I2C timer register */ 54 #define PCH_I2CSRST 0xFC /* I2C reset register */ 55 #define PCH_I2CNF 0xF8 /* I2C noise filter register */ 56 57 #define BUS_IDLE_TIMEOUT 20 58 #define PCH_I2CCTL_I2CMEN 0x0080 59 #define TEN_BIT_ADDR_DEFAULT 0xF000 60 #define TEN_BIT_ADDR_MASK 0xF0 61 #define PCH_START 0x0020 62 #define PCH_RESTART 0x0004 63 #define PCH_ESR_START 0x0001 64 #define PCH_BUFF_START 0x1 65 #define PCH_REPSTART 0x0004 66 #define PCH_ACK 0x0008 67 #define PCH_GETACK 0x0001 68 #define CLR_REG 0x0 69 #define I2C_RD 0x1 70 #define I2CMCF_BIT 0x0080 71 #define I2CMIF_BIT 0x0002 72 #define I2CMAL_BIT 0x0010 73 #define I2CBMFI_BIT 0x0001 74 #define I2CBMAL_BIT 0x0002 75 #define I2CBMNA_BIT 0x0004 76 #define I2CBMTO_BIT 0x0008 77 #define I2CBMIS_BIT 0x0010 78 #define I2CESRFI_BIT 0X0001 79 #define I2CESRTO_BIT 0x0002 80 #define I2CESRFIIE_BIT 0x1 81 #define I2CESRTOIE_BIT 0x2 82 #define I2CBMDZ_BIT 0x0040 83 #define I2CBMAG_BIT 0x0020 84 #define I2CMBB_BIT 0x0020 85 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \ 86 I2CBMTO_BIT | I2CBMIS_BIT) 87 #define I2C_ADDR_MSK 0xFF 88 #define I2C_MSB_2B_MSK 0x300 89 #define FAST_MODE_CLK 400 90 #define FAST_MODE_EN 0x0001 91 #define SUB_ADDR_LEN_MAX 4 92 #define BUF_LEN_MAX 32 93 #define PCH_BUFFER_MODE 0x1 94 #define EEPROM_SW_RST_MODE 0x0002 95 #define NORMAL_INTR_ENBL 0x0300 96 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT) 97 #define EEPROM_RST_INTR_DISBL 0x0 98 #define BUFFER_MODE_INTR_ENBL 0x001F 99 #define BUFFER_MODE_INTR_DISBL 0x0 100 #define NORMAL_MODE 0x0 101 #define BUFFER_MODE 0x1 102 #define EEPROM_SR_MODE 0x2 103 #define I2C_TX_MODE 0x0010 104 #define PCH_BUF_TX 0xFFF7 105 #define PCH_BUF_RD 0x0008 106 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \ 107 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT) 108 #define I2CMAL_EVENT 0x0001 109 #define I2CMCF_EVENT 0x0002 110 #define I2CBMFI_EVENT 0x0004 111 #define I2CBMAL_EVENT 0x0008 112 #define I2CBMNA_EVENT 0x0010 113 #define I2CBMTO_EVENT 0x0020 114 #define I2CBMIS_EVENT 0x0040 115 #define I2CESRFI_EVENT 0x0080 116 #define I2CESRTO_EVENT 0x0100 117 #define PCI_DEVICE_ID_PCH_I2C 0x8817 118 119 #define pch_dbg(adap, fmt, arg...) \ 120 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 121 122 #define pch_err(adap, fmt, arg...) \ 123 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 124 125 #define pch_pci_err(pdev, fmt, arg...) \ 126 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg) 127 128 #define pch_pci_dbg(pdev, fmt, arg...) \ 129 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg) 130 131 /* 132 Set the number of I2C instance max 133 Intel EG20T PCH : 1ch 134 LAPIS Semiconductor ML7213 IOH : 2ch 135 LAPIS Semiconductor ML7831 IOH : 1ch 136 */ 137 #define PCH_I2C_MAX_DEV 2 138 139 /** 140 * struct i2c_algo_pch_data - for I2C driver functionalities 141 * @pch_adapter: stores the reference to i2c_adapter structure 142 * @p_adapter_info: stores the reference to adapter_info structure 143 * @pch_base_address: specifies the remapped base address 144 * @pch_buff_mode_en: specifies if buffer mode is enabled 145 * @pch_event_flag: specifies occurrence of interrupt events 146 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed 147 */ 148 struct i2c_algo_pch_data { 149 struct i2c_adapter pch_adapter; 150 struct adapter_info *p_adapter_info; 151 void __iomem *pch_base_address; 152 int pch_buff_mode_en; 153 u32 pch_event_flag; 154 bool pch_i2c_xfer_in_progress; 155 }; 156 157 /** 158 * struct adapter_info - This structure holds the adapter information for the 159 PCH i2c controller 160 * @pch_data: stores a list of i2c_algo_pch_data 161 * @pch_i2c_suspended: specifies whether the system is suspended or not 162 * perhaps with more lines and words. 163 * @ch_num: specifies the number of i2c instance 164 * 165 * pch_data has as many elements as maximum I2C channels 166 */ 167 struct adapter_info { 168 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV]; 169 bool pch_i2c_suspended; 170 int ch_num; 171 }; 172 173 174 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */ 175 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */ 176 static wait_queue_head_t pch_event; 177 static DEFINE_MUTEX(pch_mutex); 178 179 /* Definition for ML7213 by LAPIS Semiconductor */ 180 #define PCI_DEVICE_ID_ML7213_I2C 0x802D 181 #define PCI_DEVICE_ID_ML7223_I2C 0x8010 182 #define PCI_DEVICE_ID_ML7831_I2C 0x8817 183 184 static const struct pci_device_id pch_pcidev_id[] = { 185 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, }, 186 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, }, 187 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, }, 188 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, }, 189 {0,} 190 }; 191 192 static irqreturn_t pch_i2c_handler(int irq, void *pData); 193 194 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask) 195 { 196 u32 val; 197 val = ioread32(addr + offset); 198 val |= bitmask; 199 iowrite32(val, addr + offset); 200 } 201 202 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask) 203 { 204 u32 val; 205 val = ioread32(addr + offset); 206 val &= (~bitmask); 207 iowrite32(val, addr + offset); 208 } 209 210 /** 211 * pch_i2c_init() - hardware initialization of I2C module 212 * @adap: Pointer to struct i2c_algo_pch_data. 213 */ 214 static void pch_i2c_init(struct i2c_algo_pch_data *adap) 215 { 216 void __iomem *p = adap->pch_base_address; 217 u32 pch_i2cbc; 218 u32 pch_i2ctmr; 219 u32 reg_value; 220 221 /* reset I2C controller */ 222 iowrite32(0x01, p + PCH_I2CSRST); 223 msleep(20); 224 iowrite32(0x0, p + PCH_I2CSRST); 225 226 /* Initialize I2C registers */ 227 iowrite32(0x21, p + PCH_I2CNF); 228 229 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN); 230 231 if (pch_i2c_speed != 400) 232 pch_i2c_speed = 100; 233 234 reg_value = PCH_I2CCTL_I2CMEN; 235 if (pch_i2c_speed == FAST_MODE_CLK) { 236 reg_value |= FAST_MODE_EN; 237 pch_dbg(adap, "Fast mode enabled\n"); 238 } 239 240 if (pch_clk > PCH_MAX_CLK) 241 pch_clk = 62500; 242 243 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8); 244 /* Set transfer speed in I2CBC */ 245 iowrite32(pch_i2cbc, p + PCH_I2CBC); 246 247 pch_i2ctmr = (pch_clk) / 8; 248 iowrite32(pch_i2ctmr, p + PCH_I2CTMR); 249 250 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */ 251 iowrite32(reg_value, p + PCH_I2CCTL); 252 253 pch_dbg(adap, 254 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n", 255 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr); 256 257 init_waitqueue_head(&pch_event); 258 } 259 260 /** 261 * pch_i2c_wait_for_bus_idle() - check the status of bus. 262 * @adap: Pointer to struct i2c_algo_pch_data. 263 * @timeout: waiting time counter (ms). 264 */ 265 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, 266 s32 timeout) 267 { 268 void __iomem *p = adap->pch_base_address; 269 int schedule = 0; 270 unsigned long end = jiffies + msecs_to_jiffies(timeout); 271 272 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) { 273 if (time_after(jiffies, end)) { 274 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 275 pch_err(adap, "%s: Timeout Error.return%d\n", 276 __func__, -ETIME); 277 pch_i2c_init(adap); 278 279 return -ETIME; 280 } 281 282 if (!schedule) 283 /* Retry after some usecs */ 284 udelay(5); 285 else 286 /* Wait a bit more without consuming CPU */ 287 usleep_range(20, 1000); 288 289 schedule = 1; 290 } 291 292 return 0; 293 } 294 295 /** 296 * pch_i2c_start() - Generate I2C start condition in normal mode. 297 * @adap: Pointer to struct i2c_algo_pch_data. 298 * 299 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1. 300 */ 301 static void pch_i2c_start(struct i2c_algo_pch_data *adap) 302 { 303 void __iomem *p = adap->pch_base_address; 304 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 305 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 306 } 307 308 /** 309 * pch_i2c_stop() - generate stop condition in normal mode. 310 * @adap: Pointer to struct i2c_algo_pch_data. 311 */ 312 static void pch_i2c_stop(struct i2c_algo_pch_data *adap) 313 { 314 void __iomem *p = adap->pch_base_address; 315 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 316 /* clear the start bit */ 317 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 318 } 319 320 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap) 321 { 322 long ret; 323 void __iomem *p = adap->pch_base_address; 324 325 ret = wait_event_timeout(pch_event, 326 (adap->pch_event_flag != 0), msecs_to_jiffies(1000)); 327 if (!ret) { 328 pch_err(adap, "%s:wait-event timeout\n", __func__); 329 adap->pch_event_flag = 0; 330 pch_i2c_stop(adap); 331 pch_i2c_init(adap); 332 return -ETIMEDOUT; 333 } 334 335 if (adap->pch_event_flag & I2C_ERROR_MASK) { 336 pch_err(adap, "Lost Arbitration\n"); 337 adap->pch_event_flag = 0; 338 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT); 339 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); 340 pch_i2c_init(adap); 341 return -EAGAIN; 342 } 343 344 adap->pch_event_flag = 0; 345 346 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) { 347 pch_dbg(adap, "Receive NACK for slave address setting\n"); 348 return -ENXIO; 349 } 350 351 return 0; 352 } 353 354 /** 355 * pch_i2c_repstart() - generate repeated start condition in normal mode 356 * @adap: Pointer to struct i2c_algo_pch_data. 357 */ 358 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap) 359 { 360 void __iomem *p = adap->pch_base_address; 361 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 362 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART); 363 } 364 365 /** 366 * pch_i2c_writebytes() - write data to I2C bus in normal mode 367 * @i2c_adap: Pointer to the struct i2c_adapter. 368 * @last: specifies whether last message or not. 369 * In the case of compound mode it will be 1 for last message, 370 * otherwise 0. 371 * @first: specifies whether first message or not. 372 * 1 for first message otherwise 0. 373 */ 374 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, 375 struct i2c_msg *msgs, u32 last, u32 first) 376 { 377 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 378 u8 *buf; 379 u32 length; 380 u32 addr; 381 u32 addr_2_msb; 382 u32 addr_8_lsb; 383 s32 wrcount; 384 s32 rtn; 385 void __iomem *p = adap->pch_base_address; 386 387 length = msgs->len; 388 buf = msgs->buf; 389 addr = msgs->addr; 390 391 /* enable master tx */ 392 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 393 394 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL), 395 length); 396 397 if (first) { 398 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 399 return -ETIME; 400 } 401 402 if (msgs->flags & I2C_M_TEN) { 403 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06; 404 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 405 if (first) 406 pch_i2c_start(adap); 407 408 rtn = pch_i2c_wait_for_check_xfer(adap); 409 if (rtn) 410 return rtn; 411 412 addr_8_lsb = (addr & I2C_ADDR_MSK); 413 iowrite32(addr_8_lsb, p + PCH_I2CDR); 414 } else { 415 /* set 7 bit slave address and R/W bit as 0 */ 416 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR); 417 if (first) 418 pch_i2c_start(adap); 419 } 420 421 rtn = pch_i2c_wait_for_check_xfer(adap); 422 if (rtn) 423 return rtn; 424 425 for (wrcount = 0; wrcount < length; ++wrcount) { 426 /* write buffer value to I2C data register */ 427 iowrite32(buf[wrcount], p + PCH_I2CDR); 428 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]); 429 430 rtn = pch_i2c_wait_for_check_xfer(adap); 431 if (rtn) 432 return rtn; 433 434 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT); 435 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); 436 } 437 438 /* check if this is the last message */ 439 if (last) 440 pch_i2c_stop(adap); 441 else 442 pch_i2c_repstart(adap); 443 444 pch_dbg(adap, "return=%d\n", wrcount); 445 446 return wrcount; 447 } 448 449 /** 450 * pch_i2c_sendack() - send ACK 451 * @adap: Pointer to struct i2c_algo_pch_data. 452 */ 453 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap) 454 { 455 void __iomem *p = adap->pch_base_address; 456 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 457 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 458 } 459 460 /** 461 * pch_i2c_sendnack() - send NACK 462 * @adap: Pointer to struct i2c_algo_pch_data. 463 */ 464 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap) 465 { 466 void __iomem *p = adap->pch_base_address; 467 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 468 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 469 } 470 471 /** 472 * pch_i2c_restart() - Generate I2C restart condition in normal mode. 473 * @adap: Pointer to struct i2c_algo_pch_data. 474 * 475 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA. 476 */ 477 static void pch_i2c_restart(struct i2c_algo_pch_data *adap) 478 { 479 void __iomem *p = adap->pch_base_address; 480 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 481 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART); 482 } 483 484 /** 485 * pch_i2c_readbytes() - read data from I2C bus in normal mode. 486 * @i2c_adap: Pointer to the struct i2c_adapter. 487 * @msgs: Pointer to i2c_msg structure. 488 * @last: specifies whether last message or not. 489 * @first: specifies whether first message or not. 490 */ 491 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 492 u32 last, u32 first) 493 { 494 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 495 496 u8 *buf; 497 u32 count; 498 u32 length; 499 u32 addr; 500 u32 addr_2_msb; 501 u32 addr_8_lsb; 502 void __iomem *p = adap->pch_base_address; 503 s32 rtn; 504 505 length = msgs->len; 506 buf = msgs->buf; 507 addr = msgs->addr; 508 509 /* enable master reception */ 510 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 511 512 if (first) { 513 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 514 return -ETIME; 515 } 516 517 if (msgs->flags & I2C_M_TEN) { 518 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); 519 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 520 if (first) 521 pch_i2c_start(adap); 522 523 rtn = pch_i2c_wait_for_check_xfer(adap); 524 if (rtn) 525 return rtn; 526 527 addr_8_lsb = (addr & I2C_ADDR_MSK); 528 iowrite32(addr_8_lsb, p + PCH_I2CDR); 529 530 pch_i2c_restart(adap); 531 532 rtn = pch_i2c_wait_for_check_xfer(adap); 533 if (rtn) 534 return rtn; 535 536 addr_2_msb |= I2C_RD; 537 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 538 } else { 539 /* 7 address bits + R/W bit */ 540 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR); 541 } 542 543 /* check if it is the first message */ 544 if (first) 545 pch_i2c_start(adap); 546 547 rtn = pch_i2c_wait_for_check_xfer(adap); 548 if (rtn) 549 return rtn; 550 551 if (length == 0) { 552 pch_i2c_stop(adap); 553 ioread32(p + PCH_I2CDR); /* Dummy read needs */ 554 555 count = length; 556 } else { 557 int read_index; 558 int loop; 559 pch_i2c_sendack(adap); 560 561 /* Dummy read */ 562 for (loop = 1, read_index = 0; loop < length; loop++) { 563 buf[read_index] = ioread32(p + PCH_I2CDR); 564 565 if (loop != 1) 566 read_index++; 567 568 rtn = pch_i2c_wait_for_check_xfer(adap); 569 if (rtn) 570 return rtn; 571 } /* end for */ 572 573 pch_i2c_sendnack(adap); 574 575 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */ 576 577 if (length != 1) 578 read_index++; 579 580 rtn = pch_i2c_wait_for_check_xfer(adap); 581 if (rtn) 582 return rtn; 583 584 if (last) 585 pch_i2c_stop(adap); 586 else 587 pch_i2c_repstart(adap); 588 589 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */ 590 count = read_index; 591 } 592 593 return count; 594 } 595 596 /** 597 * pch_i2c_cb() - Interrupt handler Call back function 598 * @adap: Pointer to struct i2c_algo_pch_data. 599 */ 600 static void pch_i2c_cb(struct i2c_algo_pch_data *adap) 601 { 602 u32 sts; 603 void __iomem *p = adap->pch_base_address; 604 605 sts = ioread32(p + PCH_I2CSR); 606 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT); 607 if (sts & I2CMAL_BIT) 608 adap->pch_event_flag |= I2CMAL_EVENT; 609 610 if (sts & I2CMCF_BIT) 611 adap->pch_event_flag |= I2CMCF_EVENT; 612 613 /* clear the applicable bits */ 614 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts); 615 616 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 617 618 wake_up(&pch_event); 619 } 620 621 /** 622 * pch_i2c_handler() - interrupt handler for the PCH I2C controller 623 * @irq: irq number. 624 * @pData: cookie passed back to the handler function. 625 */ 626 static irqreturn_t pch_i2c_handler(int irq, void *pData) 627 { 628 u32 reg_val; 629 int flag; 630 int i; 631 struct adapter_info *adap_info = pData; 632 void __iomem *p; 633 u32 mode; 634 635 for (i = 0, flag = 0; i < adap_info->ch_num; i++) { 636 p = adap_info->pch_data[i].pch_base_address; 637 mode = ioread32(p + PCH_I2CMOD); 638 mode &= BUFFER_MODE | EEPROM_SR_MODE; 639 if (mode != NORMAL_MODE) { 640 pch_err(adap_info->pch_data, 641 "I2C-%d mode(%d) is not supported\n", mode, i); 642 continue; 643 } 644 reg_val = ioread32(p + PCH_I2CSR); 645 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) { 646 pch_i2c_cb(&adap_info->pch_data[i]); 647 flag = 1; 648 } 649 } 650 651 return flag ? IRQ_HANDLED : IRQ_NONE; 652 } 653 654 /** 655 * pch_i2c_xfer() - Reading adnd writing data through I2C bus 656 * @i2c_adap: Pointer to the struct i2c_adapter. 657 * @msgs: Pointer to i2c_msg structure. 658 * @num: number of messages. 659 */ 660 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap, 661 struct i2c_msg *msgs, s32 num) 662 { 663 struct i2c_msg *pmsg; 664 u32 i = 0; 665 u32 status; 666 s32 ret; 667 668 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 669 670 ret = mutex_lock_interruptible(&pch_mutex); 671 if (ret) 672 return ret; 673 674 if (adap->p_adapter_info->pch_i2c_suspended) { 675 mutex_unlock(&pch_mutex); 676 return -EBUSY; 677 } 678 679 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n", 680 adap->p_adapter_info->pch_i2c_suspended); 681 /* transfer not completed */ 682 adap->pch_i2c_xfer_in_progress = true; 683 684 for (i = 0; i < num && ret >= 0; i++) { 685 pmsg = &msgs[i]; 686 pmsg->flags |= adap->pch_buff_mode_en; 687 status = pmsg->flags; 688 pch_dbg(adap, 689 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status); 690 691 if ((status & (I2C_M_RD)) != false) { 692 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num), 693 (i == 0)); 694 } else { 695 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num), 696 (i == 0)); 697 } 698 } 699 700 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */ 701 702 mutex_unlock(&pch_mutex); 703 704 return (ret < 0) ? ret : num; 705 } 706 707 /** 708 * pch_i2c_func() - return the functionality of the I2C driver 709 * @adap: Pointer to struct i2c_algo_pch_data. 710 */ 711 static u32 pch_i2c_func(struct i2c_adapter *adap) 712 { 713 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 714 } 715 716 static const struct i2c_algorithm pch_algorithm = { 717 .master_xfer = pch_i2c_xfer, 718 .functionality = pch_i2c_func 719 }; 720 721 /** 722 * pch_i2c_disbl_int() - Disable PCH I2C interrupts 723 * @adap: Pointer to struct i2c_algo_pch_data. 724 */ 725 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap) 726 { 727 void __iomem *p = adap->pch_base_address; 728 729 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL); 730 731 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK); 732 733 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK); 734 } 735 736 static int pch_i2c_probe(struct pci_dev *pdev, 737 const struct pci_device_id *id) 738 { 739 void __iomem *base_addr; 740 int ret; 741 int i, j; 742 struct adapter_info *adap_info; 743 struct i2c_adapter *pch_adap; 744 745 pch_pci_dbg(pdev, "Entered.\n"); 746 747 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL); 748 if (adap_info == NULL) 749 return -ENOMEM; 750 751 ret = pci_enable_device(pdev); 752 if (ret) { 753 pch_pci_err(pdev, "pci_enable_device FAILED\n"); 754 goto err_pci_enable; 755 } 756 757 ret = pci_request_regions(pdev, KBUILD_MODNAME); 758 if (ret) { 759 pch_pci_err(pdev, "pci_request_regions FAILED\n"); 760 goto err_pci_req; 761 } 762 763 base_addr = pci_iomap(pdev, 1, 0); 764 765 if (base_addr == NULL) { 766 pch_pci_err(pdev, "pci_iomap FAILED\n"); 767 ret = -ENOMEM; 768 goto err_pci_iomap; 769 } 770 771 /* Set the number of I2C channel instance */ 772 adap_info->ch_num = id->driver_data; 773 774 for (i = 0; i < adap_info->ch_num; i++) { 775 pch_adap = &adap_info->pch_data[i].pch_adapter; 776 adap_info->pch_i2c_suspended = false; 777 778 adap_info->pch_data[i].p_adapter_info = adap_info; 779 780 pch_adap->owner = THIS_MODULE; 781 pch_adap->class = I2C_CLASS_HWMON; 782 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name)); 783 pch_adap->algo = &pch_algorithm; 784 pch_adap->algo_data = &adap_info->pch_data[i]; 785 786 /* base_addr + offset; */ 787 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i; 788 789 pch_adap->dev.of_node = pdev->dev.of_node; 790 pch_adap->dev.parent = &pdev->dev; 791 } 792 793 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED, 794 KBUILD_MODNAME, adap_info); 795 if (ret) { 796 pch_pci_err(pdev, "request_irq FAILED\n"); 797 goto err_request_irq; 798 } 799 800 for (i = 0; i < adap_info->ch_num; i++) { 801 pch_adap = &adap_info->pch_data[i].pch_adapter; 802 803 pch_i2c_init(&adap_info->pch_data[i]); 804 805 pch_adap->nr = i; 806 ret = i2c_add_numbered_adapter(pch_adap); 807 if (ret) { 808 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i); 809 goto err_add_adapter; 810 } 811 } 812 813 pci_set_drvdata(pdev, adap_info); 814 pch_pci_dbg(pdev, "returns %d.\n", ret); 815 return 0; 816 817 err_add_adapter: 818 for (j = 0; j < i; j++) 819 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter); 820 free_irq(pdev->irq, adap_info); 821 err_request_irq: 822 pci_iounmap(pdev, base_addr); 823 err_pci_iomap: 824 pci_release_regions(pdev); 825 err_pci_req: 826 pci_disable_device(pdev); 827 err_pci_enable: 828 kfree(adap_info); 829 return ret; 830 } 831 832 static void pch_i2c_remove(struct pci_dev *pdev) 833 { 834 int i; 835 struct adapter_info *adap_info = pci_get_drvdata(pdev); 836 837 free_irq(pdev->irq, adap_info); 838 839 for (i = 0; i < adap_info->ch_num; i++) { 840 pch_i2c_disbl_int(&adap_info->pch_data[i]); 841 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter); 842 } 843 844 if (adap_info->pch_data[0].pch_base_address) 845 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address); 846 847 for (i = 0; i < adap_info->ch_num; i++) 848 adap_info->pch_data[i].pch_base_address = NULL; 849 850 pci_release_regions(pdev); 851 852 pci_disable_device(pdev); 853 kfree(adap_info); 854 } 855 856 #ifdef CONFIG_PM 857 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state) 858 { 859 int ret; 860 int i; 861 struct adapter_info *adap_info = pci_get_drvdata(pdev); 862 void __iomem *p = adap_info->pch_data[0].pch_base_address; 863 864 adap_info->pch_i2c_suspended = true; 865 866 for (i = 0; i < adap_info->ch_num; i++) { 867 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) { 868 /* Wait until all channel transfers are completed */ 869 msleep(20); 870 } 871 } 872 873 /* Disable the i2c interrupts */ 874 for (i = 0; i < adap_info->ch_num; i++) 875 pch_i2c_disbl_int(&adap_info->pch_data[i]); 876 877 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x " 878 "invoked function pch_i2c_disbl_int successfully\n", 879 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA), 880 ioread32(p + PCH_I2CESRSTA)); 881 882 ret = pci_save_state(pdev); 883 884 if (ret) { 885 pch_pci_err(pdev, "pci_save_state\n"); 886 return ret; 887 } 888 889 pci_enable_wake(pdev, PCI_D3hot, 0); 890 pci_disable_device(pdev); 891 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 892 893 return 0; 894 } 895 896 static int pch_i2c_resume(struct pci_dev *pdev) 897 { 898 int i; 899 struct adapter_info *adap_info = pci_get_drvdata(pdev); 900 901 pci_set_power_state(pdev, PCI_D0); 902 pci_restore_state(pdev); 903 904 if (pci_enable_device(pdev) < 0) { 905 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n"); 906 return -EIO; 907 } 908 909 pci_enable_wake(pdev, PCI_D3hot, 0); 910 911 for (i = 0; i < adap_info->ch_num; i++) 912 pch_i2c_init(&adap_info->pch_data[i]); 913 914 adap_info->pch_i2c_suspended = false; 915 916 return 0; 917 } 918 #else 919 #define pch_i2c_suspend NULL 920 #define pch_i2c_resume NULL 921 #endif 922 923 static struct pci_driver pch_pcidriver = { 924 .name = KBUILD_MODNAME, 925 .id_table = pch_pcidev_id, 926 .probe = pch_i2c_probe, 927 .remove = pch_i2c_remove, 928 .suspend = pch_i2c_suspend, 929 .resume = pch_i2c_resume 930 }; 931 932 module_pci_driver(pch_pcidriver); 933 934 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C"); 935 MODULE_LICENSE("GPL"); 936 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>"); 937 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR)); 938 module_param(pch_clk, int, (S_IRUSR | S_IWUSR)); 939