1 /* 2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/delay.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/i2c.h> 24 #include <linux/fs.h> 25 #include <linux/io.h> 26 #include <linux/types.h> 27 #include <linux/interrupt.h> 28 #include <linux/jiffies.h> 29 #include <linux/pci.h> 30 #include <linux/mutex.h> 31 #include <linux/ktime.h> 32 #include <linux/slab.h> 33 34 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */ 35 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */ 36 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */ 37 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */ 38 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */ 39 40 #define PCH_I2CSADR 0x00 /* I2C slave address register */ 41 #define PCH_I2CCTL 0x04 /* I2C control register */ 42 #define PCH_I2CSR 0x08 /* I2C status register */ 43 #define PCH_I2CDR 0x0C /* I2C data register */ 44 #define PCH_I2CMON 0x10 /* I2C bus monitor register */ 45 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */ 46 #define PCH_I2CMOD 0x18 /* I2C mode register */ 47 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */ 48 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */ 49 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */ 50 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */ 51 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */ 52 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */ 53 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */ 54 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */ 55 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */ 56 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */ 57 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */ 58 #define PCH_I2CTMR 0x48 /* I2C timer register */ 59 #define PCH_I2CSRST 0xFC /* I2C reset register */ 60 #define PCH_I2CNF 0xF8 /* I2C noise filter register */ 61 62 #define BUS_IDLE_TIMEOUT 20 63 #define PCH_I2CCTL_I2CMEN 0x0080 64 #define TEN_BIT_ADDR_DEFAULT 0xF000 65 #define TEN_BIT_ADDR_MASK 0xF0 66 #define PCH_START 0x0020 67 #define PCH_ESR_START 0x0001 68 #define PCH_BUFF_START 0x1 69 #define PCH_REPSTART 0x0004 70 #define PCH_ACK 0x0008 71 #define PCH_GETACK 0x0001 72 #define CLR_REG 0x0 73 #define I2C_RD 0x1 74 #define I2CMCF_BIT 0x0080 75 #define I2CMIF_BIT 0x0002 76 #define I2CMAL_BIT 0x0010 77 #define I2CBMFI_BIT 0x0001 78 #define I2CBMAL_BIT 0x0002 79 #define I2CBMNA_BIT 0x0004 80 #define I2CBMTO_BIT 0x0008 81 #define I2CBMIS_BIT 0x0010 82 #define I2CESRFI_BIT 0X0001 83 #define I2CESRTO_BIT 0x0002 84 #define I2CESRFIIE_BIT 0x1 85 #define I2CESRTOIE_BIT 0x2 86 #define I2CBMDZ_BIT 0x0040 87 #define I2CBMAG_BIT 0x0020 88 #define I2CMBB_BIT 0x0020 89 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \ 90 I2CBMTO_BIT | I2CBMIS_BIT) 91 #define I2C_ADDR_MSK 0xFF 92 #define I2C_MSB_2B_MSK 0x300 93 #define FAST_MODE_CLK 400 94 #define FAST_MODE_EN 0x0001 95 #define SUB_ADDR_LEN_MAX 4 96 #define BUF_LEN_MAX 32 97 #define PCH_BUFFER_MODE 0x1 98 #define EEPROM_SW_RST_MODE 0x0002 99 #define NORMAL_INTR_ENBL 0x0300 100 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT) 101 #define EEPROM_RST_INTR_DISBL 0x0 102 #define BUFFER_MODE_INTR_ENBL 0x001F 103 #define BUFFER_MODE_INTR_DISBL 0x0 104 #define NORMAL_MODE 0x0 105 #define BUFFER_MODE 0x1 106 #define EEPROM_SR_MODE 0x2 107 #define I2C_TX_MODE 0x0010 108 #define PCH_BUF_TX 0xFFF7 109 #define PCH_BUF_RD 0x0008 110 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \ 111 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT) 112 #define I2CMAL_EVENT 0x0001 113 #define I2CMCF_EVENT 0x0002 114 #define I2CBMFI_EVENT 0x0004 115 #define I2CBMAL_EVENT 0x0008 116 #define I2CBMNA_EVENT 0x0010 117 #define I2CBMTO_EVENT 0x0020 118 #define I2CBMIS_EVENT 0x0040 119 #define I2CESRFI_EVENT 0x0080 120 #define I2CESRTO_EVENT 0x0100 121 #define PCI_DEVICE_ID_PCH_I2C 0x8817 122 123 #define pch_dbg(adap, fmt, arg...) \ 124 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 125 126 #define pch_err(adap, fmt, arg...) \ 127 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg) 128 129 #define pch_pci_err(pdev, fmt, arg...) \ 130 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg) 131 132 #define pch_pci_dbg(pdev, fmt, arg...) \ 133 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg) 134 135 /** 136 * struct i2c_algo_pch_data - for I2C driver functionalities 137 * @pch_adapter: stores the reference to i2c_adapter structure 138 * @p_adapter_info: stores the reference to adapter_info structure 139 * @pch_base_address: specifies the remapped base address 140 * @pch_buff_mode_en: specifies if buffer mode is enabled 141 * @pch_event_flag: specifies occurrence of interrupt events 142 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed 143 */ 144 struct i2c_algo_pch_data { 145 struct i2c_adapter pch_adapter; 146 struct adapter_info *p_adapter_info; 147 void __iomem *pch_base_address; 148 int pch_buff_mode_en; 149 u32 pch_event_flag; 150 bool pch_i2c_xfer_in_progress; 151 }; 152 153 /** 154 * struct adapter_info - This structure holds the adapter information for the 155 PCH i2c controller 156 * @pch_data: stores a list of i2c_algo_pch_data 157 * @pch_i2c_suspended: specifies whether the system is suspended or not 158 * perhaps with more lines and words. 159 * 160 * pch_data has as many elements as maximum I2C channels 161 */ 162 struct adapter_info { 163 struct i2c_algo_pch_data pch_data; 164 bool pch_i2c_suspended; 165 }; 166 167 168 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */ 169 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */ 170 static wait_queue_head_t pch_event; 171 static DEFINE_MUTEX(pch_mutex); 172 173 static struct pci_device_id __devinitdata pch_pcidev_id[] = { 174 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)}, 175 {0,} 176 }; 177 178 static irqreturn_t pch_i2c_handler(int irq, void *pData); 179 180 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask) 181 { 182 u32 val; 183 val = ioread32(addr + offset); 184 val |= bitmask; 185 iowrite32(val, addr + offset); 186 } 187 188 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask) 189 { 190 u32 val; 191 val = ioread32(addr + offset); 192 val &= (~bitmask); 193 iowrite32(val, addr + offset); 194 } 195 196 /** 197 * pch_i2c_init() - hardware initialization of I2C module 198 * @adap: Pointer to struct i2c_algo_pch_data. 199 */ 200 static void pch_i2c_init(struct i2c_algo_pch_data *adap) 201 { 202 void __iomem *p = adap->pch_base_address; 203 u32 pch_i2cbc; 204 u32 pch_i2ctmr; 205 u32 reg_value; 206 207 /* reset I2C controller */ 208 iowrite32(0x01, p + PCH_I2CSRST); 209 msleep(20); 210 iowrite32(0x0, p + PCH_I2CSRST); 211 212 /* Initialize I2C registers */ 213 iowrite32(0x21, p + PCH_I2CNF); 214 215 pch_setbit(adap->pch_base_address, PCH_I2CCTL, 216 PCH_I2CCTL_I2CMEN); 217 218 if (pch_i2c_speed != 400) 219 pch_i2c_speed = 100; 220 221 reg_value = PCH_I2CCTL_I2CMEN; 222 if (pch_i2c_speed == FAST_MODE_CLK) { 223 reg_value |= FAST_MODE_EN; 224 pch_dbg(adap, "Fast mode enabled\n"); 225 } 226 227 if (pch_clk > PCH_MAX_CLK) 228 pch_clk = 62500; 229 230 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / pch_i2c_speed * 8; 231 /* Set transfer speed in I2CBC */ 232 iowrite32(pch_i2cbc, p + PCH_I2CBC); 233 234 pch_i2ctmr = (pch_clk) / 8; 235 iowrite32(pch_i2ctmr, p + PCH_I2CTMR); 236 237 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */ 238 iowrite32(reg_value, p + PCH_I2CCTL); 239 240 pch_dbg(adap, 241 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n", 242 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr); 243 244 init_waitqueue_head(&pch_event); 245 } 246 247 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2) 248 { 249 return cmp1.tv64 < cmp2.tv64; 250 } 251 252 /** 253 * pch_i2c_wait_for_bus_idle() - check the status of bus. 254 * @adap: Pointer to struct i2c_algo_pch_data. 255 * @timeout: waiting time counter (us). 256 */ 257 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, 258 s32 timeout) 259 { 260 void __iomem *p = adap->pch_base_address; 261 262 /* MAX timeout value is timeout*1000*1000nsec */ 263 ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); 264 do { 265 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) 266 break; 267 msleep(20); 268 } while (ktime_lt(ktime_get(), ns_val)); 269 270 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 271 272 if (timeout == 0) { 273 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME); 274 return -ETIME; 275 } 276 277 return 0; 278 } 279 280 /** 281 * pch_i2c_start() - Generate I2C start condition in normal mode. 282 * @adap: Pointer to struct i2c_algo_pch_data. 283 * 284 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1. 285 */ 286 static void pch_i2c_start(struct i2c_algo_pch_data *adap) 287 { 288 void __iomem *p = adap->pch_base_address; 289 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 290 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 291 } 292 293 /** 294 * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event 295 * @adap: Pointer to struct i2c_algo_pch_data. 296 */ 297 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap) 298 { 299 s32 ret; 300 ret = wait_event_timeout(pch_event, 301 (adap->pch_event_flag != 0), msecs_to_jiffies(50)); 302 if (ret < 0) { 303 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 304 return ret; 305 } 306 307 if (ret == 0) { 308 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 309 return -ETIMEDOUT; 310 } 311 312 if (adap->pch_event_flag & I2C_ERROR_MASK) { 313 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag); 314 return -EIO; 315 } 316 317 adap->pch_event_flag = 0; 318 319 return 0; 320 } 321 322 /** 323 * pch_i2c_getack() - to confirm ACK/NACK 324 * @adap: Pointer to struct i2c_algo_pch_data. 325 */ 326 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap) 327 { 328 u32 reg_val; 329 void __iomem *p = adap->pch_base_address; 330 reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK; 331 332 if (reg_val != 0) { 333 pch_err(adap, "return%d\n", -EPROTO); 334 return -EPROTO; 335 } 336 337 return 0; 338 } 339 340 /** 341 * pch_i2c_stop() - generate stop condition in normal mode. 342 * @adap: Pointer to struct i2c_algo_pch_data. 343 */ 344 static void pch_i2c_stop(struct i2c_algo_pch_data *adap) 345 { 346 void __iomem *p = adap->pch_base_address; 347 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 348 /* clear the start bit */ 349 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START); 350 } 351 352 /** 353 * pch_i2c_repstart() - generate repeated start condition in normal mode 354 * @adap: Pointer to struct i2c_algo_pch_data. 355 */ 356 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap) 357 { 358 void __iomem *p = adap->pch_base_address; 359 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 360 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART); 361 } 362 363 /** 364 * pch_i2c_writebytes() - write data to I2C bus in normal mode 365 * @i2c_adap: Pointer to the struct i2c_adapter. 366 * @last: specifies whether last message or not. 367 * In the case of compound mode it will be 1 for last message, 368 * otherwise 0. 369 * @first: specifies whether first message or not. 370 * 1 for first message otherwise 0. 371 */ 372 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, 373 struct i2c_msg *msgs, u32 last, u32 first) 374 { 375 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 376 u8 *buf; 377 u32 length; 378 u32 addr; 379 u32 addr_2_msb; 380 u32 addr_8_lsb; 381 s32 wrcount; 382 void __iomem *p = adap->pch_base_address; 383 384 length = msgs->len; 385 buf = msgs->buf; 386 addr = msgs->addr; 387 388 /* enable master tx */ 389 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 390 391 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL), 392 length); 393 394 if (first) { 395 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 396 return -ETIME; 397 } 398 399 if (msgs->flags & I2C_M_TEN) { 400 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); 401 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 402 if (first) 403 pch_i2c_start(adap); 404 if (pch_i2c_wait_for_xfer_complete(adap) == 0 && 405 pch_i2c_getack(adap) == 0) { 406 addr_8_lsb = (addr & I2C_ADDR_MSK); 407 iowrite32(addr_8_lsb, p + PCH_I2CDR); 408 } else { 409 pch_i2c_stop(adap); 410 return -ETIME; 411 } 412 } else { 413 /* set 7 bit slave address and R/W bit as 0 */ 414 iowrite32(addr << 1, p + PCH_I2CDR); 415 if (first) 416 pch_i2c_start(adap); 417 } 418 419 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 420 (pch_i2c_getack(adap) == 0)) { 421 for (wrcount = 0; wrcount < length; ++wrcount) { 422 /* write buffer value to I2C data register */ 423 iowrite32(buf[wrcount], p + PCH_I2CDR); 424 pch_dbg(adap, "writing %x to Data register\n", 425 buf[wrcount]); 426 427 if (pch_i2c_wait_for_xfer_complete(adap) != 0) 428 return -ETIME; 429 430 if (pch_i2c_getack(adap)) 431 return -EIO; 432 } 433 434 /* check if this is the last message */ 435 if (last) 436 pch_i2c_stop(adap); 437 else 438 pch_i2c_repstart(adap); 439 } else { 440 pch_i2c_stop(adap); 441 return -EIO; 442 } 443 444 pch_dbg(adap, "return=%d\n", wrcount); 445 446 return wrcount; 447 } 448 449 /** 450 * pch_i2c_sendack() - send ACK 451 * @adap: Pointer to struct i2c_algo_pch_data. 452 */ 453 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap) 454 { 455 void __iomem *p = adap->pch_base_address; 456 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 457 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 458 } 459 460 /** 461 * pch_i2c_sendnack() - send NACK 462 * @adap: Pointer to struct i2c_algo_pch_data. 463 */ 464 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap) 465 { 466 void __iomem *p = adap->pch_base_address; 467 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); 468 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); 469 } 470 471 /** 472 * pch_i2c_readbytes() - read data from I2C bus in normal mode. 473 * @i2c_adap: Pointer to the struct i2c_adapter. 474 * @msgs: Pointer to i2c_msg structure. 475 * @last: specifies whether last message or not. 476 * @first: specifies whether first message or not. 477 */ 478 s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 479 u32 last, u32 first) 480 { 481 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 482 483 u8 *buf; 484 u32 count; 485 u32 length; 486 u32 addr; 487 u32 addr_2_msb; 488 void __iomem *p = adap->pch_base_address; 489 490 length = msgs->len; 491 buf = msgs->buf; 492 addr = msgs->addr; 493 494 /* enable master reception */ 495 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE); 496 497 if (first) { 498 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME) 499 return -ETIME; 500 } 501 502 if (msgs->flags & I2C_M_TEN) { 503 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD)); 504 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 505 506 } else { 507 /* 7 address bits + R/W bit */ 508 addr = (((addr) << 1) | (I2C_RD)); 509 iowrite32(addr, p + PCH_I2CDR); 510 } 511 512 /* check if it is the first message */ 513 if (first) 514 pch_i2c_start(adap); 515 516 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 517 (pch_i2c_getack(adap) == 0)) { 518 pch_dbg(adap, "return %d\n", 0); 519 520 if (length == 0) { 521 pch_i2c_stop(adap); 522 ioread32(p + PCH_I2CDR); /* Dummy read needs */ 523 524 count = length; 525 } else { 526 int read_index; 527 int loop; 528 pch_i2c_sendack(adap); 529 530 /* Dummy read */ 531 for (loop = 1, read_index = 0; loop < length; loop++) { 532 buf[read_index] = ioread32(p + PCH_I2CDR); 533 534 if (loop != 1) 535 read_index++; 536 537 if (pch_i2c_wait_for_xfer_complete(adap) != 0) { 538 pch_i2c_stop(adap); 539 return -ETIME; 540 } 541 } /* end for */ 542 543 pch_i2c_sendnack(adap); 544 545 buf[read_index] = ioread32(p + PCH_I2CDR); 546 547 if (length != 1) 548 read_index++; 549 550 if (pch_i2c_wait_for_xfer_complete(adap) == 0) { 551 if (last) 552 pch_i2c_stop(adap); 553 else 554 pch_i2c_repstart(adap); 555 556 buf[read_index++] = ioread32(p + PCH_I2CDR); 557 count = read_index; 558 } else { 559 count = -ETIME; 560 } 561 562 } 563 } else { 564 count = -ETIME; 565 pch_i2c_stop(adap); 566 } 567 568 return count; 569 } 570 571 /** 572 * pch_i2c_cb_ch0() - Interrupt handler Call back function 573 * @adap: Pointer to struct i2c_algo_pch_data. 574 */ 575 static void pch_i2c_cb_ch0(struct i2c_algo_pch_data *adap) 576 { 577 u32 sts; 578 void __iomem *p = adap->pch_base_address; 579 580 sts = ioread32(p + PCH_I2CSR); 581 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT); 582 if (sts & I2CMAL_BIT) 583 adap->pch_event_flag |= I2CMAL_EVENT; 584 585 if (sts & I2CMCF_BIT) 586 adap->pch_event_flag |= I2CMCF_EVENT; 587 588 /* clear the applicable bits */ 589 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts); 590 591 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 592 593 wake_up(&pch_event); 594 } 595 596 /** 597 * pch_i2c_handler() - interrupt handler for the PCH I2C controller 598 * @irq: irq number. 599 * @pData: cookie passed back to the handler function. 600 */ 601 static irqreturn_t pch_i2c_handler(int irq, void *pData) 602 { 603 s32 reg_val; 604 605 struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData; 606 void __iomem *p = adap_data->pch_base_address; 607 u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE); 608 609 if (mode != NORMAL_MODE) { 610 pch_err(adap_data, "I2C mode is not supported\n"); 611 return IRQ_NONE; 612 } 613 614 reg_val = ioread32(p + PCH_I2CSR); 615 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) 616 pch_i2c_cb_ch0(adap_data); 617 else 618 return IRQ_NONE; 619 620 return IRQ_HANDLED; 621 } 622 623 /** 624 * pch_i2c_xfer() - Reading adnd writing data through I2C bus 625 * @i2c_adap: Pointer to the struct i2c_adapter. 626 * @msgs: Pointer to i2c_msg structure. 627 * @num: number of messages. 628 */ 629 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap, 630 struct i2c_msg *msgs, s32 num) 631 { 632 struct i2c_msg *pmsg; 633 u32 i = 0; 634 u32 status; 635 u32 msglen; 636 u32 subaddrlen; 637 s32 ret; 638 639 struct i2c_algo_pch_data *adap = i2c_adap->algo_data; 640 641 ret = mutex_lock_interruptible(&pch_mutex); 642 if (ret) 643 return -ERESTARTSYS; 644 645 if (adap->p_adapter_info->pch_i2c_suspended) { 646 mutex_unlock(&pch_mutex); 647 return -EBUSY; 648 } 649 650 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n", 651 adap->p_adapter_info->pch_i2c_suspended); 652 /* transfer not completed */ 653 adap->pch_i2c_xfer_in_progress = true; 654 655 pmsg = &msgs[0]; 656 pmsg->flags |= adap->pch_buff_mode_en; 657 status = pmsg->flags; 658 pch_dbg(adap, 659 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status); 660 /* calculate sub address length and message length */ 661 /* these are applicable only for buffer mode */ 662 subaddrlen = pmsg->buf[0]; 663 /* calculate actual message length excluding 664 * the sub address fields */ 665 msglen = (pmsg->len) - (subaddrlen + 1); 666 if (status & (I2C_M_RD)) { 667 pch_dbg(adap, "invoking pch_i2c_readbytes\n"); 668 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num), 669 (i == 0)); 670 } else { 671 pch_dbg(adap, "invoking pch_i2c_writebytes\n"); 672 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num), 673 (i == 0)); 674 } 675 676 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */ 677 678 mutex_unlock(&pch_mutex); 679 680 return ret; 681 } 682 683 /** 684 * pch_i2c_func() - return the functionality of the I2C driver 685 * @adap: Pointer to struct i2c_algo_pch_data. 686 */ 687 static u32 pch_i2c_func(struct i2c_adapter *adap) 688 { 689 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; 690 } 691 692 static struct i2c_algorithm pch_algorithm = { 693 .master_xfer = pch_i2c_xfer, 694 .functionality = pch_i2c_func 695 }; 696 697 /** 698 * pch_i2c_disbl_int() - Disable PCH I2C interrupts 699 * @adap: Pointer to struct i2c_algo_pch_data. 700 */ 701 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap) 702 { 703 void __iomem *p = adap->pch_base_address; 704 705 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL); 706 707 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK); 708 709 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK); 710 } 711 712 static int __devinit pch_i2c_probe(struct pci_dev *pdev, 713 const struct pci_device_id *id) 714 { 715 void __iomem *base_addr; 716 s32 ret; 717 struct adapter_info *adap_info; 718 719 pch_pci_dbg(pdev, "Entered.\n"); 720 721 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL); 722 if (adap_info == NULL) { 723 pch_pci_err(pdev, "Memory allocation FAILED\n"); 724 return -ENOMEM; 725 } 726 727 ret = pci_enable_device(pdev); 728 if (ret) { 729 pch_pci_err(pdev, "pci_enable_device FAILED\n"); 730 goto err_pci_enable; 731 } 732 733 ret = pci_request_regions(pdev, KBUILD_MODNAME); 734 if (ret) { 735 pch_pci_err(pdev, "pci_request_regions FAILED\n"); 736 goto err_pci_req; 737 } 738 739 base_addr = pci_iomap(pdev, 1, 0); 740 741 if (base_addr == NULL) { 742 pch_pci_err(pdev, "pci_iomap FAILED\n"); 743 ret = -ENOMEM; 744 goto err_pci_iomap; 745 } 746 747 adap_info->pch_i2c_suspended = false; 748 749 adap_info->pch_data.p_adapter_info = adap_info; 750 751 adap_info->pch_data.pch_adapter.owner = THIS_MODULE; 752 adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON; 753 strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME); 754 adap_info->pch_data.pch_adapter.algo = &pch_algorithm; 755 adap_info->pch_data.pch_adapter.algo_data = 756 &adap_info->pch_data; 757 758 /* (i * 0x80) + base_addr; */ 759 adap_info->pch_data.pch_base_address = base_addr; 760 761 adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev; 762 763 ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter)); 764 765 if (ret) { 766 pch_pci_err(pdev, "i2c_add_adapter FAILED\n"); 767 goto err_i2c_add_adapter; 768 } 769 770 pch_i2c_init(&adap_info->pch_data); 771 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED, 772 KBUILD_MODNAME, &adap_info->pch_data); 773 if (ret) { 774 pch_pci_err(pdev, "request_irq FAILED\n"); 775 goto err_request_irq; 776 } 777 778 pci_set_drvdata(pdev, adap_info); 779 pch_pci_dbg(pdev, "returns %d.\n", ret); 780 return 0; 781 782 err_request_irq: 783 i2c_del_adapter(&(adap_info->pch_data.pch_adapter)); 784 err_i2c_add_adapter: 785 pci_iounmap(pdev, base_addr); 786 err_pci_iomap: 787 pci_release_regions(pdev); 788 err_pci_req: 789 pci_disable_device(pdev); 790 err_pci_enable: 791 kfree(adap_info); 792 return ret; 793 } 794 795 static void __devexit pch_i2c_remove(struct pci_dev *pdev) 796 { 797 struct adapter_info *adap_info = pci_get_drvdata(pdev); 798 799 pch_i2c_disbl_int(&adap_info->pch_data); 800 free_irq(pdev->irq, &adap_info->pch_data); 801 i2c_del_adapter(&(adap_info->pch_data.pch_adapter)); 802 803 if (adap_info->pch_data.pch_base_address) { 804 pci_iounmap(pdev, adap_info->pch_data.pch_base_address); 805 adap_info->pch_data.pch_base_address = 0; 806 } 807 808 pci_set_drvdata(pdev, NULL); 809 810 pci_release_regions(pdev); 811 812 pci_disable_device(pdev); 813 kfree(adap_info); 814 } 815 816 #ifdef CONFIG_PM 817 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state) 818 { 819 int ret; 820 struct adapter_info *adap_info = pci_get_drvdata(pdev); 821 void __iomem *p = adap_info->pch_data.pch_base_address; 822 823 adap_info->pch_i2c_suspended = true; 824 825 while ((adap_info->pch_data.pch_i2c_xfer_in_progress)) { 826 /* Wait until all channel transfers are completed */ 827 msleep(20); 828 } 829 /* Disable the i2c interrupts */ 830 pch_i2c_disbl_int(&adap_info->pch_data); 831 832 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x " 833 "invoked function pch_i2c_disbl_int successfully\n", 834 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA), 835 ioread32(p + PCH_I2CESRSTA)); 836 837 ret = pci_save_state(pdev); 838 839 if (ret) { 840 pch_pci_err(pdev, "pci_save_state\n"); 841 return ret; 842 } 843 844 pci_enable_wake(pdev, PCI_D3hot, 0); 845 pci_disable_device(pdev); 846 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 847 848 return 0; 849 } 850 851 static int pch_i2c_resume(struct pci_dev *pdev) 852 { 853 struct adapter_info *adap_info = pci_get_drvdata(pdev); 854 855 pci_set_power_state(pdev, PCI_D0); 856 pci_restore_state(pdev); 857 858 if (pci_enable_device(pdev) < 0) { 859 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n"); 860 return -EIO; 861 } 862 863 pci_enable_wake(pdev, PCI_D3hot, 0); 864 865 pch_i2c_init(&adap_info->pch_data); 866 867 adap_info->pch_i2c_suspended = false; 868 869 return 0; 870 } 871 #else 872 #define pch_i2c_suspend NULL 873 #define pch_i2c_resume NULL 874 #endif 875 876 static struct pci_driver pch_pcidriver = { 877 .name = KBUILD_MODNAME, 878 .id_table = pch_pcidev_id, 879 .probe = pch_i2c_probe, 880 .remove = __devexit_p(pch_i2c_remove), 881 .suspend = pch_i2c_suspend, 882 .resume = pch_i2c_resume 883 }; 884 885 static int __init pch_pci_init(void) 886 { 887 return pci_register_driver(&pch_pcidriver); 888 } 889 module_init(pch_pci_init); 890 891 static void __exit pch_pci_exit(void) 892 { 893 pci_unregister_driver(&pch_pcidriver); 894 } 895 module_exit(pch_pci_exit); 896 897 MODULE_DESCRIPTION("PCH I2C PCI Driver"); 898 MODULE_LICENSE("GPL"); 899 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.okisemi.com>"); 900 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR)); 901 module_param(pch_clk, int, (S_IRUSR | S_IWUSR)); 902