1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/reservation.h> 5 #include <linux/mm_types.h> 6 #include <drm/drmP.h> 7 #include <drm/drm_encoder.h> 8 #include <drm/drm_gem.h> 9 #include <drm/gpu_scheduler.h> 10 11 #define GMP_GRANULARITY (128 * 1024) 12 13 /* Enum for each of the V3D queues. We maintain various queue 14 * tracking as an array because at some point we'll want to support 15 * the TFU (texture formatting unit) as another queue. 16 */ 17 enum v3d_queue { 18 V3D_BIN, 19 V3D_RENDER, 20 }; 21 22 #define V3D_MAX_QUEUES (V3D_RENDER + 1) 23 24 struct v3d_queue_state { 25 struct drm_gpu_scheduler sched; 26 27 u64 fence_context; 28 u64 emit_seqno; 29 }; 30 31 struct v3d_dev { 32 struct drm_device drm; 33 34 /* Short representation (e.g. 33, 41) of the V3D tech version 35 * and revision. 36 */ 37 int ver; 38 39 struct device *dev; 40 struct platform_device *pdev; 41 void __iomem *hub_regs; 42 void __iomem *core_regs[3]; 43 void __iomem *bridge_regs; 44 void __iomem *gca_regs; 45 struct clk *clk; 46 47 /* Virtual and DMA addresses of the single shared page table. */ 48 volatile u32 *pt; 49 dma_addr_t pt_paddr; 50 51 /* Virtual and DMA addresses of the MMU's scratch page. When 52 * a read or write is invalid in the MMU, it will be 53 * redirected here. 54 */ 55 void *mmu_scratch; 56 dma_addr_t mmu_scratch_paddr; 57 58 /* Number of V3D cores. */ 59 u32 cores; 60 61 /* Allocator managing the address space. All units are in 62 * number of pages. 63 */ 64 struct drm_mm mm; 65 spinlock_t mm_lock; 66 67 struct work_struct overflow_mem_work; 68 69 struct v3d_exec_info *bin_job; 70 struct v3d_exec_info *render_job; 71 72 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 73 74 /* Spinlock used to synchronize the overflow memory 75 * management against bin job submission. 76 */ 77 spinlock_t job_lock; 78 79 /* Protects bo_stats */ 80 struct mutex bo_lock; 81 82 /* Lock taken when resetting the GPU, to keep multiple 83 * processes from trying to park the scheduler threads and 84 * reset at once. 85 */ 86 struct mutex reset_lock; 87 88 /* Lock taken when creating and pushing the GPU scheduler 89 * jobs, to keep the sched-fence seqnos in order. 90 */ 91 struct mutex sched_lock; 92 93 struct { 94 u32 num_allocated; 95 u32 pages_allocated; 96 } bo_stats; 97 }; 98 99 static inline struct v3d_dev * 100 to_v3d_dev(struct drm_device *dev) 101 { 102 return (struct v3d_dev *)dev->dev_private; 103 } 104 105 /* The per-fd struct, which tracks the MMU mappings. */ 106 struct v3d_file_priv { 107 struct v3d_dev *v3d; 108 109 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 110 }; 111 112 /* Tracks a mapping of a BO into a per-fd address space */ 113 struct v3d_vma { 114 struct v3d_page_table *pt; 115 struct list_head list; /* entry in v3d_bo.vmas */ 116 }; 117 118 struct v3d_bo { 119 struct drm_gem_object base; 120 121 struct mutex lock; 122 123 struct drm_mm_node node; 124 125 u32 pages_refcount; 126 struct page **pages; 127 struct sg_table *sgt; 128 void *vaddr; 129 130 struct list_head vmas; /* list of v3d_vma */ 131 132 /* List entry for the BO's position in 133 * v3d_exec_info->unref_list 134 */ 135 struct list_head unref_head; 136 137 /* normally (resv == &_resv) except for imported bo's */ 138 struct reservation_object *resv; 139 struct reservation_object _resv; 140 }; 141 142 static inline struct v3d_bo * 143 to_v3d_bo(struct drm_gem_object *bo) 144 { 145 return (struct v3d_bo *)bo; 146 } 147 148 struct v3d_fence { 149 struct dma_fence base; 150 struct drm_device *dev; 151 /* v3d seqno for signaled() test */ 152 u64 seqno; 153 enum v3d_queue queue; 154 }; 155 156 static inline struct v3d_fence * 157 to_v3d_fence(struct dma_fence *fence) 158 { 159 return (struct v3d_fence *)fence; 160 } 161 162 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 163 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 164 165 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 166 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 167 168 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 169 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 170 171 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 172 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 173 174 struct v3d_job { 175 struct drm_sched_job base; 176 177 struct v3d_exec_info *exec; 178 179 /* An optional fence userspace can pass in for the job to depend on. */ 180 struct dma_fence *in_fence; 181 182 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 183 struct dma_fence *done_fence; 184 185 /* GPU virtual addresses of the start/end of the CL job. */ 186 u32 start, end; 187 188 u32 timedout_ctca, timedout_ctra; 189 }; 190 191 struct v3d_exec_info { 192 struct v3d_dev *v3d; 193 194 struct v3d_job bin, render; 195 196 /* Fence for when the scheduler considers the binner to be 197 * done, for render to depend on. 198 */ 199 struct dma_fence *bin_done_fence; 200 201 /* Fence for when the scheduler considers the render to be 202 * done, for when the BOs reservations should be complete. 203 */ 204 struct dma_fence *render_done_fence; 205 206 struct kref refcount; 207 208 /* This is the array of BOs that were looked up at the start of exec. */ 209 struct v3d_bo **bo; 210 u32 bo_count; 211 212 /* List of overflow BOs used in the job that need to be 213 * released once the job is complete. 214 */ 215 struct list_head unref_list; 216 217 /* Submitted tile memory allocation start/size, tile state. */ 218 u32 qma, qms, qts; 219 }; 220 221 /** 222 * _wait_for - magic (register) wait macro 223 * 224 * Does the right thing for modeset paths when run under kdgb or similar atomic 225 * contexts. Note that it's important that we check the condition again after 226 * having timed out, since the timeout could be due to preemption or similar and 227 * we've never had a chance to check the condition before the timeout. 228 */ 229 #define wait_for(COND, MS) ({ \ 230 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 231 int ret__ = 0; \ 232 while (!(COND)) { \ 233 if (time_after(jiffies, timeout__)) { \ 234 if (!(COND)) \ 235 ret__ = -ETIMEDOUT; \ 236 break; \ 237 } \ 238 msleep(1); \ 239 } \ 240 ret__; \ 241 }) 242 243 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 244 { 245 /* nsecs_to_jiffies64() does not guard against overflow */ 246 if (NSEC_PER_SEC % HZ && 247 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 248 return MAX_JIFFY_OFFSET; 249 250 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 251 } 252 253 /* v3d_bo.c */ 254 void v3d_free_object(struct drm_gem_object *gem_obj); 255 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 256 size_t size); 257 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 258 struct drm_file *file_priv); 259 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 260 struct drm_file *file_priv); 261 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 262 struct drm_file *file_priv); 263 vm_fault_t v3d_gem_fault(struct vm_fault *vmf); 264 int v3d_mmap(struct file *filp, struct vm_area_struct *vma); 265 struct reservation_object *v3d_prime_res_obj(struct drm_gem_object *obj); 266 int v3d_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 267 struct sg_table *v3d_prime_get_sg_table(struct drm_gem_object *obj); 268 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 269 struct dma_buf_attachment *attach, 270 struct sg_table *sgt); 271 272 /* v3d_debugfs.c */ 273 int v3d_debugfs_init(struct drm_minor *minor); 274 275 /* v3d_fence.c */ 276 extern const struct dma_fence_ops v3d_fence_ops; 277 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 278 279 /* v3d_gem.c */ 280 int v3d_gem_init(struct drm_device *dev); 281 void v3d_gem_destroy(struct drm_device *dev); 282 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 283 struct drm_file *file_priv); 284 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 285 struct drm_file *file_priv); 286 void v3d_exec_put(struct v3d_exec_info *exec); 287 void v3d_reset(struct v3d_dev *v3d); 288 void v3d_invalidate_caches(struct v3d_dev *v3d); 289 void v3d_flush_caches(struct v3d_dev *v3d); 290 291 /* v3d_irq.c */ 292 void v3d_irq_init(struct v3d_dev *v3d); 293 void v3d_irq_enable(struct v3d_dev *v3d); 294 void v3d_irq_disable(struct v3d_dev *v3d); 295 void v3d_irq_reset(struct v3d_dev *v3d); 296 297 /* v3d_mmu.c */ 298 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo, 299 u32 *offset); 300 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 301 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 302 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 303 304 /* v3d_sched.c */ 305 int v3d_sched_init(struct v3d_dev *v3d); 306 void v3d_sched_fini(struct v3d_dev *v3d); 307