1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* LCDC DRM driver, based on da8xx-fb */ 19 20 #include <linux/component.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/suspend.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 26 #include "tilcdc_drv.h" 27 #include "tilcdc_regs.h" 28 #include "tilcdc_tfp410.h" 29 #include "tilcdc_panel.h" 30 #include "tilcdc_external.h" 31 32 #include "drm_fb_helper.h" 33 34 static LIST_HEAD(module_list); 35 36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 37 38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 39 DRM_FORMAT_BGR888, 40 DRM_FORMAT_XBGR8888 }; 41 42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 43 DRM_FORMAT_RGB888, 44 DRM_FORMAT_XRGB8888 }; 45 46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 47 DRM_FORMAT_RGB888, 48 DRM_FORMAT_XRGB8888 }; 49 50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 51 const struct tilcdc_module_ops *funcs) 52 { 53 mod->name = name; 54 mod->funcs = funcs; 55 INIT_LIST_HEAD(&mod->list); 56 list_add(&mod->list, &module_list); 57 } 58 59 void tilcdc_module_cleanup(struct tilcdc_module *mod) 60 { 61 list_del(&mod->list); 62 } 63 64 static struct of_device_id tilcdc_of_match[]; 65 66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) 68 { 69 return drm_fb_cma_create(dev, file_priv, mode_cmd); 70 } 71 72 static void tilcdc_fb_output_poll_changed(struct drm_device *dev) 73 { 74 struct tilcdc_drm_private *priv = dev->dev_private; 75 drm_fbdev_cma_hotplug_event(priv->fbdev); 76 } 77 78 static int tilcdc_atomic_check(struct drm_device *dev, 79 struct drm_atomic_state *state) 80 { 81 int ret; 82 83 ret = drm_atomic_helper_check_modeset(dev, state); 84 if (ret) 85 return ret; 86 87 ret = drm_atomic_helper_check_planes(dev, state); 88 if (ret) 89 return ret; 90 91 /* 92 * tilcdc ->atomic_check can update ->mode_changed if pixel format 93 * changes, hence will we check modeset changes again. 94 */ 95 ret = drm_atomic_helper_check_modeset(dev, state); 96 if (ret) 97 return ret; 98 99 return ret; 100 } 101 102 static int tilcdc_commit(struct drm_device *dev, 103 struct drm_atomic_state *state, 104 bool async) 105 { 106 int ret; 107 108 ret = drm_atomic_helper_prepare_planes(dev, state); 109 if (ret) 110 return ret; 111 112 drm_atomic_helper_swap_state(state, true); 113 114 /* 115 * Everything below can be run asynchronously without the need to grab 116 * any modeset locks at all under one condition: It must be guaranteed 117 * that the asynchronous work has either been cancelled (if the driver 118 * supports it, which at least requires that the framebuffers get 119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 120 * before the new state gets committed on the software side with 121 * drm_atomic_helper_swap_state(). 122 * 123 * This scheme allows new atomic state updates to be prepared and 124 * checked in parallel to the asynchronous completion of the previous 125 * update. Which is important since compositors need to figure out the 126 * composition of the next frame right after having submitted the 127 * current layout. 128 */ 129 130 drm_atomic_helper_commit_modeset_disables(dev, state); 131 132 drm_atomic_helper_commit_planes(dev, state, 0); 133 134 drm_atomic_helper_commit_modeset_enables(dev, state); 135 136 drm_atomic_helper_wait_for_vblanks(dev, state); 137 138 drm_atomic_helper_cleanup_planes(dev, state); 139 140 return 0; 141 } 142 143 static const struct drm_mode_config_funcs mode_config_funcs = { 144 .fb_create = tilcdc_fb_create, 145 .output_poll_changed = tilcdc_fb_output_poll_changed, 146 .atomic_check = tilcdc_atomic_check, 147 .atomic_commit = tilcdc_commit, 148 }; 149 150 static void modeset_init(struct drm_device *dev) 151 { 152 struct tilcdc_drm_private *priv = dev->dev_private; 153 struct tilcdc_module *mod; 154 155 list_for_each_entry(mod, &module_list, list) { 156 DBG("loading module: %s", mod->name); 157 mod->funcs->modeset_init(mod, dev); 158 } 159 160 dev->mode_config.min_width = 0; 161 dev->mode_config.min_height = 0; 162 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 163 dev->mode_config.max_height = 2048; 164 dev->mode_config.funcs = &mode_config_funcs; 165 } 166 167 #ifdef CONFIG_CPU_FREQ 168 static int cpufreq_transition(struct notifier_block *nb, 169 unsigned long val, void *data) 170 { 171 struct tilcdc_drm_private *priv = container_of(nb, 172 struct tilcdc_drm_private, freq_transition); 173 174 if (val == CPUFREQ_POSTCHANGE) 175 tilcdc_crtc_update_clk(priv->crtc); 176 177 return 0; 178 } 179 #endif 180 181 /* 182 * DRM operations: 183 */ 184 185 static void tilcdc_fini(struct drm_device *dev) 186 { 187 struct tilcdc_drm_private *priv = dev->dev_private; 188 189 if (priv->crtc) 190 tilcdc_crtc_shutdown(priv->crtc); 191 192 if (priv->is_registered) 193 drm_dev_unregister(dev); 194 195 drm_kms_helper_poll_fini(dev); 196 197 if (priv->fbdev) 198 drm_fbdev_cma_fini(priv->fbdev); 199 200 drm_irq_uninstall(dev); 201 drm_mode_config_cleanup(dev); 202 tilcdc_remove_external_device(dev); 203 204 #ifdef CONFIG_CPU_FREQ 205 if (priv->freq_transition.notifier_call) 206 cpufreq_unregister_notifier(&priv->freq_transition, 207 CPUFREQ_TRANSITION_NOTIFIER); 208 #endif 209 210 if (priv->clk) 211 clk_put(priv->clk); 212 213 if (priv->mmio) 214 iounmap(priv->mmio); 215 216 if (priv->wq) { 217 flush_workqueue(priv->wq); 218 destroy_workqueue(priv->wq); 219 } 220 221 dev->dev_private = NULL; 222 223 pm_runtime_disable(dev->dev); 224 225 drm_dev_unref(dev); 226 } 227 228 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) 229 { 230 struct drm_device *ddev; 231 struct platform_device *pdev = to_platform_device(dev); 232 struct device_node *node = dev->of_node; 233 struct tilcdc_drm_private *priv; 234 struct resource *res; 235 u32 bpp = 0; 236 int ret; 237 238 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 239 if (!priv) { 240 dev_err(dev, "failed to allocate private data\n"); 241 return -ENOMEM; 242 } 243 244 ddev = drm_dev_alloc(ddrv, dev); 245 if (IS_ERR(ddev)) 246 return PTR_ERR(ddev); 247 248 ddev->dev_private = priv; 249 platform_set_drvdata(pdev, ddev); 250 drm_mode_config_init(ddev); 251 252 priv->is_componentized = 253 tilcdc_get_external_components(dev, NULL) > 0; 254 255 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 256 if (!priv->wq) { 257 ret = -ENOMEM; 258 goto init_failed; 259 } 260 261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 262 if (!res) { 263 dev_err(dev, "failed to get memory resource\n"); 264 ret = -EINVAL; 265 goto init_failed; 266 } 267 268 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 269 if (!priv->mmio) { 270 dev_err(dev, "failed to ioremap\n"); 271 ret = -ENOMEM; 272 goto init_failed; 273 } 274 275 priv->clk = clk_get(dev, "fck"); 276 if (IS_ERR(priv->clk)) { 277 dev_err(dev, "failed to get functional clock\n"); 278 ret = -ENODEV; 279 goto init_failed; 280 } 281 282 #ifdef CONFIG_CPU_FREQ 283 priv->freq_transition.notifier_call = cpufreq_transition; 284 ret = cpufreq_register_notifier(&priv->freq_transition, 285 CPUFREQ_TRANSITION_NOTIFIER); 286 if (ret) { 287 dev_err(dev, "failed to register cpufreq notifier\n"); 288 priv->freq_transition.notifier_call = NULL; 289 goto init_failed; 290 } 291 #endif 292 293 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 294 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 295 296 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 297 298 if (of_property_read_u32(node, "max-width", &priv->max_width)) 299 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 300 301 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 302 303 if (of_property_read_u32(node, "max-pixelclock", 304 &priv->max_pixelclock)) 305 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 306 307 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 308 309 pm_runtime_enable(dev); 310 311 /* Determine LCD IP Version */ 312 pm_runtime_get_sync(dev); 313 switch (tilcdc_read(ddev, LCDC_PID_REG)) { 314 case 0x4c100102: 315 priv->rev = 1; 316 break; 317 case 0x4f200800: 318 case 0x4f201000: 319 priv->rev = 2; 320 break; 321 default: 322 dev_warn(dev, "Unknown PID Reg value 0x%08x, " 323 "defaulting to LCD revision 1\n", 324 tilcdc_read(ddev, LCDC_PID_REG)); 325 priv->rev = 1; 326 break; 327 } 328 329 pm_runtime_put_sync(dev); 330 331 if (priv->rev == 1) { 332 DBG("Revision 1 LCDC supports only RGB565 format"); 333 priv->pixelformats = tilcdc_rev1_formats; 334 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 335 bpp = 16; 336 } else { 337 const char *str = "\0"; 338 339 of_property_read_string(node, "blue-and-red-wiring", &str); 340 if (0 == strcmp(str, "crossed")) { 341 DBG("Configured for crossed blue and red wires"); 342 priv->pixelformats = tilcdc_crossed_formats; 343 priv->num_pixelformats = 344 ARRAY_SIZE(tilcdc_crossed_formats); 345 bpp = 32; /* Choose bpp with RGB support for fbdef */ 346 } else if (0 == strcmp(str, "straight")) { 347 DBG("Configured for straight blue and red wires"); 348 priv->pixelformats = tilcdc_straight_formats; 349 priv->num_pixelformats = 350 ARRAY_SIZE(tilcdc_straight_formats); 351 bpp = 16; /* Choose bpp with RGB support for fbdef */ 352 } else { 353 DBG("Blue and red wiring '%s' unknown, use legacy mode", 354 str); 355 priv->pixelformats = tilcdc_legacy_formats; 356 priv->num_pixelformats = 357 ARRAY_SIZE(tilcdc_legacy_formats); 358 bpp = 16; /* This is just a guess */ 359 } 360 } 361 362 ret = tilcdc_crtc_create(ddev); 363 if (ret < 0) { 364 dev_err(dev, "failed to create crtc\n"); 365 goto init_failed; 366 } 367 modeset_init(ddev); 368 369 if (priv->is_componentized) { 370 ret = component_bind_all(dev, ddev); 371 if (ret < 0) 372 goto init_failed; 373 374 ret = tilcdc_add_component_encoder(ddev); 375 if (ret < 0) 376 goto init_failed; 377 } else { 378 ret = tilcdc_attach_external_device(ddev); 379 if (ret) 380 goto init_failed; 381 } 382 383 if (!priv->external_connector && 384 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { 385 dev_err(dev, "no encoders/connectors found\n"); 386 ret = -ENXIO; 387 goto init_failed; 388 } 389 390 ret = drm_vblank_init(ddev, 1); 391 if (ret < 0) { 392 dev_err(dev, "failed to initialize vblank\n"); 393 goto init_failed; 394 } 395 396 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); 397 if (ret < 0) { 398 dev_err(dev, "failed to install IRQ handler\n"); 399 goto init_failed; 400 } 401 402 drm_mode_config_reset(ddev); 403 404 priv->fbdev = drm_fbdev_cma_init(ddev, bpp, 405 ddev->mode_config.num_connector); 406 if (IS_ERR(priv->fbdev)) { 407 ret = PTR_ERR(priv->fbdev); 408 goto init_failed; 409 } 410 411 drm_kms_helper_poll_init(ddev); 412 413 ret = drm_dev_register(ddev, 0); 414 if (ret) 415 goto init_failed; 416 417 priv->is_registered = true; 418 return 0; 419 420 init_failed: 421 tilcdc_fini(ddev); 422 423 return ret; 424 } 425 426 static void tilcdc_lastclose(struct drm_device *dev) 427 { 428 struct tilcdc_drm_private *priv = dev->dev_private; 429 drm_fbdev_cma_restore_mode(priv->fbdev); 430 } 431 432 static irqreturn_t tilcdc_irq(int irq, void *arg) 433 { 434 struct drm_device *dev = arg; 435 struct tilcdc_drm_private *priv = dev->dev_private; 436 return tilcdc_crtc_irq(priv->crtc); 437 } 438 439 #if defined(CONFIG_DEBUG_FS) 440 static const struct { 441 const char *name; 442 uint8_t rev; 443 uint8_t save; 444 uint32_t reg; 445 } registers[] = { 446 #define REG(rev, save, reg) { #reg, rev, save, reg } 447 /* exists in revision 1: */ 448 REG(1, false, LCDC_PID_REG), 449 REG(1, true, LCDC_CTRL_REG), 450 REG(1, false, LCDC_STAT_REG), 451 REG(1, true, LCDC_RASTER_CTRL_REG), 452 REG(1, true, LCDC_RASTER_TIMING_0_REG), 453 REG(1, true, LCDC_RASTER_TIMING_1_REG), 454 REG(1, true, LCDC_RASTER_TIMING_2_REG), 455 REG(1, true, LCDC_DMA_CTRL_REG), 456 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 457 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 458 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 459 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 460 /* new in revision 2: */ 461 REG(2, false, LCDC_RAW_STAT_REG), 462 REG(2, false, LCDC_MASKED_STAT_REG), 463 REG(2, true, LCDC_INT_ENABLE_SET_REG), 464 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 465 REG(2, false, LCDC_END_OF_INT_IND_REG), 466 REG(2, true, LCDC_CLK_ENABLE_REG), 467 #undef REG 468 }; 469 470 #endif 471 472 #ifdef CONFIG_DEBUG_FS 473 static int tilcdc_regs_show(struct seq_file *m, void *arg) 474 { 475 struct drm_info_node *node = (struct drm_info_node *) m->private; 476 struct drm_device *dev = node->minor->dev; 477 struct tilcdc_drm_private *priv = dev->dev_private; 478 unsigned i; 479 480 pm_runtime_get_sync(dev->dev); 481 482 seq_printf(m, "revision: %d\n", priv->rev); 483 484 for (i = 0; i < ARRAY_SIZE(registers); i++) 485 if (priv->rev >= registers[i].rev) 486 seq_printf(m, "%s:\t %08x\n", registers[i].name, 487 tilcdc_read(dev, registers[i].reg)); 488 489 pm_runtime_put_sync(dev->dev); 490 491 return 0; 492 } 493 494 static int tilcdc_mm_show(struct seq_file *m, void *arg) 495 { 496 struct drm_info_node *node = (struct drm_info_node *) m->private; 497 struct drm_device *dev = node->minor->dev; 498 struct drm_printer p = drm_seq_file_printer(m); 499 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 500 return 0; 501 } 502 503 static struct drm_info_list tilcdc_debugfs_list[] = { 504 { "regs", tilcdc_regs_show, 0 }, 505 { "mm", tilcdc_mm_show, 0 }, 506 { "fb", drm_fb_cma_debugfs_show, 0 }, 507 }; 508 509 static int tilcdc_debugfs_init(struct drm_minor *minor) 510 { 511 struct drm_device *dev = minor->dev; 512 struct tilcdc_module *mod; 513 int ret; 514 515 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 516 ARRAY_SIZE(tilcdc_debugfs_list), 517 minor->debugfs_root, minor); 518 519 list_for_each_entry(mod, &module_list, list) 520 if (mod->funcs->debugfs_init) 521 mod->funcs->debugfs_init(mod, minor); 522 523 if (ret) { 524 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 525 return ret; 526 } 527 528 return ret; 529 } 530 #endif 531 532 DEFINE_DRM_GEM_CMA_FOPS(fops); 533 534 static struct drm_driver tilcdc_driver = { 535 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET | 536 DRIVER_PRIME | DRIVER_ATOMIC), 537 .lastclose = tilcdc_lastclose, 538 .irq_handler = tilcdc_irq, 539 .gem_free_object_unlocked = drm_gem_cma_free_object, 540 .gem_vm_ops = &drm_gem_cma_vm_ops, 541 .dumb_create = drm_gem_cma_dumb_create, 542 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 543 .dumb_destroy = drm_gem_dumb_destroy, 544 545 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 546 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 547 .gem_prime_import = drm_gem_prime_import, 548 .gem_prime_export = drm_gem_prime_export, 549 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 550 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 551 .gem_prime_vmap = drm_gem_cma_prime_vmap, 552 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 553 .gem_prime_mmap = drm_gem_cma_prime_mmap, 554 #ifdef CONFIG_DEBUG_FS 555 .debugfs_init = tilcdc_debugfs_init, 556 #endif 557 .fops = &fops, 558 .name = "tilcdc", 559 .desc = "TI LCD Controller DRM", 560 .date = "20121205", 561 .major = 1, 562 .minor = 0, 563 }; 564 565 /* 566 * Power management: 567 */ 568 569 #ifdef CONFIG_PM_SLEEP 570 static int tilcdc_pm_suspend(struct device *dev) 571 { 572 struct drm_device *ddev = dev_get_drvdata(dev); 573 struct tilcdc_drm_private *priv = ddev->dev_private; 574 575 priv->saved_state = drm_atomic_helper_suspend(ddev); 576 577 /* Select sleep pin state */ 578 pinctrl_pm_select_sleep_state(dev); 579 580 return 0; 581 } 582 583 static int tilcdc_pm_resume(struct device *dev) 584 { 585 struct drm_device *ddev = dev_get_drvdata(dev); 586 struct tilcdc_drm_private *priv = ddev->dev_private; 587 int ret = 0; 588 589 /* Select default pin state */ 590 pinctrl_pm_select_default_state(dev); 591 592 if (priv->saved_state) 593 ret = drm_atomic_helper_resume(ddev, priv->saved_state); 594 595 return ret; 596 } 597 #endif 598 599 static const struct dev_pm_ops tilcdc_pm_ops = { 600 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 601 }; 602 603 /* 604 * Platform driver: 605 */ 606 static int tilcdc_bind(struct device *dev) 607 { 608 return tilcdc_init(&tilcdc_driver, dev); 609 } 610 611 static void tilcdc_unbind(struct device *dev) 612 { 613 struct drm_device *ddev = dev_get_drvdata(dev); 614 615 /* Check if a subcomponent has already triggered the unloading. */ 616 if (!ddev->dev_private) 617 return; 618 619 tilcdc_fini(dev_get_drvdata(dev)); 620 } 621 622 static const struct component_master_ops tilcdc_comp_ops = { 623 .bind = tilcdc_bind, 624 .unbind = tilcdc_unbind, 625 }; 626 627 static int tilcdc_pdev_probe(struct platform_device *pdev) 628 { 629 struct component_match *match = NULL; 630 int ret; 631 632 /* bail out early if no DT data: */ 633 if (!pdev->dev.of_node) { 634 dev_err(&pdev->dev, "device-tree data is missing\n"); 635 return -ENXIO; 636 } 637 638 ret = tilcdc_get_external_components(&pdev->dev, &match); 639 if (ret < 0) 640 return ret; 641 else if (ret == 0) 642 return tilcdc_init(&tilcdc_driver, &pdev->dev); 643 else 644 return component_master_add_with_match(&pdev->dev, 645 &tilcdc_comp_ops, 646 match); 647 } 648 649 static int tilcdc_pdev_remove(struct platform_device *pdev) 650 { 651 int ret; 652 653 ret = tilcdc_get_external_components(&pdev->dev, NULL); 654 if (ret < 0) 655 return ret; 656 else if (ret == 0) 657 tilcdc_fini(platform_get_drvdata(pdev)); 658 else 659 component_master_del(&pdev->dev, &tilcdc_comp_ops); 660 661 return 0; 662 } 663 664 static struct of_device_id tilcdc_of_match[] = { 665 { .compatible = "ti,am33xx-tilcdc", }, 666 { .compatible = "ti,da850-tilcdc", }, 667 { }, 668 }; 669 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 670 671 static struct platform_driver tilcdc_platform_driver = { 672 .probe = tilcdc_pdev_probe, 673 .remove = tilcdc_pdev_remove, 674 .driver = { 675 .name = "tilcdc", 676 .pm = &tilcdc_pm_ops, 677 .of_match_table = tilcdc_of_match, 678 }, 679 }; 680 681 static int __init tilcdc_drm_init(void) 682 { 683 DBG("init"); 684 tilcdc_tfp410_init(); 685 tilcdc_panel_init(); 686 return platform_driver_register(&tilcdc_platform_driver); 687 } 688 689 static void __exit tilcdc_drm_fini(void) 690 { 691 DBG("fini"); 692 platform_driver_unregister(&tilcdc_platform_driver); 693 tilcdc_panel_fini(); 694 tilcdc_tfp410_fini(); 695 } 696 697 module_init(tilcdc_drm_init); 698 module_exit(tilcdc_drm_fini); 699 700 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 701 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 702 MODULE_LICENSE("GPL"); 703