1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* LCDC DRM driver, based on da8xx-fb */ 19 20 #include <linux/component.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/suspend.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 26 #include "tilcdc_drv.h" 27 #include "tilcdc_regs.h" 28 #include "tilcdc_tfp410.h" 29 #include "tilcdc_panel.h" 30 #include "tilcdc_external.h" 31 32 #include "drm_fb_helper.h" 33 34 static LIST_HEAD(module_list); 35 36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 37 38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 39 DRM_FORMAT_BGR888, 40 DRM_FORMAT_XBGR8888 }; 41 42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 43 DRM_FORMAT_RGB888, 44 DRM_FORMAT_XRGB8888 }; 45 46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 47 DRM_FORMAT_RGB888, 48 DRM_FORMAT_XRGB8888 }; 49 50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 51 const struct tilcdc_module_ops *funcs) 52 { 53 mod->name = name; 54 mod->funcs = funcs; 55 INIT_LIST_HEAD(&mod->list); 56 list_add(&mod->list, &module_list); 57 } 58 59 void tilcdc_module_cleanup(struct tilcdc_module *mod) 60 { 61 list_del(&mod->list); 62 } 63 64 static struct of_device_id tilcdc_of_match[]; 65 66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) 68 { 69 return drm_fb_cma_create(dev, file_priv, mode_cmd); 70 } 71 72 static void tilcdc_fb_output_poll_changed(struct drm_device *dev) 73 { 74 struct tilcdc_drm_private *priv = dev->dev_private; 75 drm_fbdev_cma_hotplug_event(priv->fbdev); 76 } 77 78 static int tilcdc_atomic_check(struct drm_device *dev, 79 struct drm_atomic_state *state) 80 { 81 int ret; 82 83 ret = drm_atomic_helper_check_modeset(dev, state); 84 if (ret) 85 return ret; 86 87 ret = drm_atomic_helper_check_planes(dev, state); 88 if (ret) 89 return ret; 90 91 /* 92 * tilcdc ->atomic_check can update ->mode_changed if pixel format 93 * changes, hence will we check modeset changes again. 94 */ 95 ret = drm_atomic_helper_check_modeset(dev, state); 96 if (ret) 97 return ret; 98 99 return ret; 100 } 101 102 static int tilcdc_commit(struct drm_device *dev, 103 struct drm_atomic_state *state, 104 bool async) 105 { 106 int ret; 107 108 ret = drm_atomic_helper_prepare_planes(dev, state); 109 if (ret) 110 return ret; 111 112 drm_atomic_helper_swap_state(state, true); 113 114 /* 115 * Everything below can be run asynchronously without the need to grab 116 * any modeset locks at all under one condition: It must be guaranteed 117 * that the asynchronous work has either been cancelled (if the driver 118 * supports it, which at least requires that the framebuffers get 119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 120 * before the new state gets committed on the software side with 121 * drm_atomic_helper_swap_state(). 122 * 123 * This scheme allows new atomic state updates to be prepared and 124 * checked in parallel to the asynchronous completion of the previous 125 * update. Which is important since compositors need to figure out the 126 * composition of the next frame right after having submitted the 127 * current layout. 128 */ 129 130 /* Keep HW on while we commit the state. */ 131 pm_runtime_get_sync(dev->dev); 132 133 drm_atomic_helper_commit_modeset_disables(dev, state); 134 135 drm_atomic_helper_commit_planes(dev, state, 0); 136 137 drm_atomic_helper_commit_modeset_enables(dev, state); 138 139 /* Now HW should remain on if need becase the crtc is enabled */ 140 pm_runtime_put_sync(dev->dev); 141 142 drm_atomic_helper_wait_for_vblanks(dev, state); 143 144 drm_atomic_helper_cleanup_planes(dev, state); 145 146 return 0; 147 } 148 149 static const struct drm_mode_config_funcs mode_config_funcs = { 150 .fb_create = tilcdc_fb_create, 151 .output_poll_changed = tilcdc_fb_output_poll_changed, 152 .atomic_check = tilcdc_atomic_check, 153 .atomic_commit = tilcdc_commit, 154 }; 155 156 static int modeset_init(struct drm_device *dev) 157 { 158 struct tilcdc_drm_private *priv = dev->dev_private; 159 struct tilcdc_module *mod; 160 161 drm_mode_config_init(dev); 162 163 priv->crtc = tilcdc_crtc_create(dev); 164 165 list_for_each_entry(mod, &module_list, list) { 166 DBG("loading module: %s", mod->name); 167 mod->funcs->modeset_init(mod, dev); 168 } 169 170 dev->mode_config.min_width = 0; 171 dev->mode_config.min_height = 0; 172 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 173 dev->mode_config.max_height = 2048; 174 dev->mode_config.funcs = &mode_config_funcs; 175 176 return 0; 177 } 178 179 #ifdef CONFIG_CPU_FREQ 180 static int cpufreq_transition(struct notifier_block *nb, 181 unsigned long val, void *data) 182 { 183 struct tilcdc_drm_private *priv = container_of(nb, 184 struct tilcdc_drm_private, freq_transition); 185 186 if (val == CPUFREQ_POSTCHANGE) 187 tilcdc_crtc_update_clk(priv->crtc); 188 189 return 0; 190 } 191 #endif 192 193 /* 194 * DRM operations: 195 */ 196 197 static int tilcdc_unload(struct drm_device *dev) 198 { 199 struct tilcdc_drm_private *priv = dev->dev_private; 200 201 tilcdc_remove_external_encoders(dev); 202 203 drm_fbdev_cma_fini(priv->fbdev); 204 drm_kms_helper_poll_fini(dev); 205 drm_mode_config_cleanup(dev); 206 drm_vblank_cleanup(dev); 207 208 drm_irq_uninstall(dev); 209 210 #ifdef CONFIG_CPU_FREQ 211 cpufreq_unregister_notifier(&priv->freq_transition, 212 CPUFREQ_TRANSITION_NOTIFIER); 213 #endif 214 215 if (priv->clk) 216 clk_put(priv->clk); 217 218 if (priv->mmio) 219 iounmap(priv->mmio); 220 221 flush_workqueue(priv->wq); 222 destroy_workqueue(priv->wq); 223 224 dev->dev_private = NULL; 225 226 pm_runtime_disable(dev->dev); 227 228 return 0; 229 } 230 231 static int tilcdc_load(struct drm_device *dev, unsigned long flags) 232 { 233 struct platform_device *pdev = dev->platformdev; 234 struct device_node *node = pdev->dev.of_node; 235 struct tilcdc_drm_private *priv; 236 struct resource *res; 237 u32 bpp = 0; 238 int ret; 239 240 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); 241 if (!priv) { 242 dev_err(dev->dev, "failed to allocate private data\n"); 243 return -ENOMEM; 244 } 245 246 dev->dev_private = priv; 247 248 priv->is_componentized = 249 tilcdc_get_external_components(dev->dev, NULL) > 0; 250 251 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 252 if (!priv->wq) { 253 ret = -ENOMEM; 254 goto fail_unset_priv; 255 } 256 257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 258 if (!res) { 259 dev_err(dev->dev, "failed to get memory resource\n"); 260 ret = -EINVAL; 261 goto fail_free_wq; 262 } 263 264 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 265 if (!priv->mmio) { 266 dev_err(dev->dev, "failed to ioremap\n"); 267 ret = -ENOMEM; 268 goto fail_free_wq; 269 } 270 271 priv->clk = clk_get(dev->dev, "fck"); 272 if (IS_ERR(priv->clk)) { 273 dev_err(dev->dev, "failed to get functional clock\n"); 274 ret = -ENODEV; 275 goto fail_iounmap; 276 } 277 278 #ifdef CONFIG_CPU_FREQ 279 priv->freq_transition.notifier_call = cpufreq_transition; 280 ret = cpufreq_register_notifier(&priv->freq_transition, 281 CPUFREQ_TRANSITION_NOTIFIER); 282 if (ret) { 283 dev_err(dev->dev, "failed to register cpufreq notifier\n"); 284 goto fail_put_clk; 285 } 286 #endif 287 288 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 289 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 290 291 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 292 293 if (of_property_read_u32(node, "ti,max-width", &priv->max_width)) 294 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 295 296 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 297 298 if (of_property_read_u32(node, "ti,max-pixelclock", 299 &priv->max_pixelclock)) 300 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 301 302 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 303 304 pm_runtime_enable(dev->dev); 305 306 /* Determine LCD IP Version */ 307 pm_runtime_get_sync(dev->dev); 308 switch (tilcdc_read(dev, LCDC_PID_REG)) { 309 case 0x4c100102: 310 priv->rev = 1; 311 break; 312 case 0x4f200800: 313 case 0x4f201000: 314 priv->rev = 2; 315 break; 316 default: 317 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, " 318 "defaulting to LCD revision 1\n", 319 tilcdc_read(dev, LCDC_PID_REG)); 320 priv->rev = 1; 321 break; 322 } 323 324 pm_runtime_put_sync(dev->dev); 325 326 if (priv->rev == 1) { 327 DBG("Revision 1 LCDC supports only RGB565 format"); 328 priv->pixelformats = tilcdc_rev1_formats; 329 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 330 bpp = 16; 331 } else { 332 const char *str = "\0"; 333 334 of_property_read_string(node, "blue-and-red-wiring", &str); 335 if (0 == strcmp(str, "crossed")) { 336 DBG("Configured for crossed blue and red wires"); 337 priv->pixelformats = tilcdc_crossed_formats; 338 priv->num_pixelformats = 339 ARRAY_SIZE(tilcdc_crossed_formats); 340 bpp = 32; /* Choose bpp with RGB support for fbdef */ 341 } else if (0 == strcmp(str, "straight")) { 342 DBG("Configured for straight blue and red wires"); 343 priv->pixelformats = tilcdc_straight_formats; 344 priv->num_pixelformats = 345 ARRAY_SIZE(tilcdc_straight_formats); 346 bpp = 16; /* Choose bpp with RGB support for fbdef */ 347 } else { 348 DBG("Blue and red wiring '%s' unknown, use legacy mode", 349 str); 350 priv->pixelformats = tilcdc_legacy_formats; 351 priv->num_pixelformats = 352 ARRAY_SIZE(tilcdc_legacy_formats); 353 bpp = 16; /* This is just a guess */ 354 } 355 } 356 357 ret = modeset_init(dev); 358 if (ret < 0) { 359 dev_err(dev->dev, "failed to initialize mode setting\n"); 360 goto fail_cpufreq_unregister; 361 } 362 363 platform_set_drvdata(pdev, dev); 364 365 if (priv->is_componentized) { 366 ret = component_bind_all(dev->dev, dev); 367 if (ret < 0) 368 goto fail_mode_config_cleanup; 369 370 ret = tilcdc_add_external_encoders(dev); 371 if (ret < 0) 372 goto fail_component_cleanup; 373 } 374 375 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { 376 dev_err(dev->dev, "no encoders/connectors found\n"); 377 ret = -ENXIO; 378 goto fail_external_cleanup; 379 } 380 381 ret = drm_vblank_init(dev, 1); 382 if (ret < 0) { 383 dev_err(dev->dev, "failed to initialize vblank\n"); 384 goto fail_external_cleanup; 385 } 386 387 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); 388 if (ret < 0) { 389 dev_err(dev->dev, "failed to install IRQ handler\n"); 390 goto fail_vblank_cleanup; 391 } 392 393 drm_mode_config_reset(dev); 394 395 priv->fbdev = drm_fbdev_cma_init(dev, bpp, 396 dev->mode_config.num_crtc, 397 dev->mode_config.num_connector); 398 if (IS_ERR(priv->fbdev)) { 399 ret = PTR_ERR(priv->fbdev); 400 goto fail_irq_uninstall; 401 } 402 403 drm_kms_helper_poll_init(dev); 404 405 return 0; 406 407 fail_irq_uninstall: 408 drm_irq_uninstall(dev); 409 410 fail_vblank_cleanup: 411 drm_vblank_cleanup(dev); 412 413 fail_component_cleanup: 414 if (priv->is_componentized) 415 component_unbind_all(dev->dev, dev); 416 417 fail_mode_config_cleanup: 418 drm_mode_config_cleanup(dev); 419 420 fail_external_cleanup: 421 tilcdc_remove_external_encoders(dev); 422 423 fail_cpufreq_unregister: 424 pm_runtime_disable(dev->dev); 425 #ifdef CONFIG_CPU_FREQ 426 cpufreq_unregister_notifier(&priv->freq_transition, 427 CPUFREQ_TRANSITION_NOTIFIER); 428 429 fail_put_clk: 430 #endif 431 clk_put(priv->clk); 432 433 fail_iounmap: 434 iounmap(priv->mmio); 435 436 fail_free_wq: 437 flush_workqueue(priv->wq); 438 destroy_workqueue(priv->wq); 439 440 fail_unset_priv: 441 dev->dev_private = NULL; 442 443 return ret; 444 } 445 446 static void tilcdc_lastclose(struct drm_device *dev) 447 { 448 struct tilcdc_drm_private *priv = dev->dev_private; 449 drm_fbdev_cma_restore_mode(priv->fbdev); 450 } 451 452 static irqreturn_t tilcdc_irq(int irq, void *arg) 453 { 454 struct drm_device *dev = arg; 455 struct tilcdc_drm_private *priv = dev->dev_private; 456 return tilcdc_crtc_irq(priv->crtc); 457 } 458 459 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe) 460 { 461 return 0; 462 } 463 464 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe) 465 { 466 return; 467 } 468 469 #if defined(CONFIG_DEBUG_FS) 470 static const struct { 471 const char *name; 472 uint8_t rev; 473 uint8_t save; 474 uint32_t reg; 475 } registers[] = { 476 #define REG(rev, save, reg) { #reg, rev, save, reg } 477 /* exists in revision 1: */ 478 REG(1, false, LCDC_PID_REG), 479 REG(1, true, LCDC_CTRL_REG), 480 REG(1, false, LCDC_STAT_REG), 481 REG(1, true, LCDC_RASTER_CTRL_REG), 482 REG(1, true, LCDC_RASTER_TIMING_0_REG), 483 REG(1, true, LCDC_RASTER_TIMING_1_REG), 484 REG(1, true, LCDC_RASTER_TIMING_2_REG), 485 REG(1, true, LCDC_DMA_CTRL_REG), 486 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 487 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 488 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 489 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 490 /* new in revision 2: */ 491 REG(2, false, LCDC_RAW_STAT_REG), 492 REG(2, false, LCDC_MASKED_STAT_REG), 493 REG(2, true, LCDC_INT_ENABLE_SET_REG), 494 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 495 REG(2, false, LCDC_END_OF_INT_IND_REG), 496 REG(2, true, LCDC_CLK_ENABLE_REG), 497 #undef REG 498 }; 499 500 #endif 501 502 #ifdef CONFIG_DEBUG_FS 503 static int tilcdc_regs_show(struct seq_file *m, void *arg) 504 { 505 struct drm_info_node *node = (struct drm_info_node *) m->private; 506 struct drm_device *dev = node->minor->dev; 507 struct tilcdc_drm_private *priv = dev->dev_private; 508 unsigned i; 509 510 pm_runtime_get_sync(dev->dev); 511 512 seq_printf(m, "revision: %d\n", priv->rev); 513 514 for (i = 0; i < ARRAY_SIZE(registers); i++) 515 if (priv->rev >= registers[i].rev) 516 seq_printf(m, "%s:\t %08x\n", registers[i].name, 517 tilcdc_read(dev, registers[i].reg)); 518 519 pm_runtime_put_sync(dev->dev); 520 521 return 0; 522 } 523 524 static int tilcdc_mm_show(struct seq_file *m, void *arg) 525 { 526 struct drm_info_node *node = (struct drm_info_node *) m->private; 527 struct drm_device *dev = node->minor->dev; 528 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); 529 } 530 531 static struct drm_info_list tilcdc_debugfs_list[] = { 532 { "regs", tilcdc_regs_show, 0 }, 533 { "mm", tilcdc_mm_show, 0 }, 534 { "fb", drm_fb_cma_debugfs_show, 0 }, 535 }; 536 537 static int tilcdc_debugfs_init(struct drm_minor *minor) 538 { 539 struct drm_device *dev = minor->dev; 540 struct tilcdc_module *mod; 541 int ret; 542 543 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 544 ARRAY_SIZE(tilcdc_debugfs_list), 545 minor->debugfs_root, minor); 546 547 list_for_each_entry(mod, &module_list, list) 548 if (mod->funcs->debugfs_init) 549 mod->funcs->debugfs_init(mod, minor); 550 551 if (ret) { 552 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 553 return ret; 554 } 555 556 return ret; 557 } 558 559 static void tilcdc_debugfs_cleanup(struct drm_minor *minor) 560 { 561 struct tilcdc_module *mod; 562 drm_debugfs_remove_files(tilcdc_debugfs_list, 563 ARRAY_SIZE(tilcdc_debugfs_list), minor); 564 565 list_for_each_entry(mod, &module_list, list) 566 if (mod->funcs->debugfs_cleanup) 567 mod->funcs->debugfs_cleanup(mod, minor); 568 } 569 #endif 570 571 static const struct file_operations fops = { 572 .owner = THIS_MODULE, 573 .open = drm_open, 574 .release = drm_release, 575 .unlocked_ioctl = drm_ioctl, 576 .compat_ioctl = drm_compat_ioctl, 577 .poll = drm_poll, 578 .read = drm_read, 579 .llseek = no_llseek, 580 .mmap = drm_gem_cma_mmap, 581 }; 582 583 static struct drm_driver tilcdc_driver = { 584 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET | 585 DRIVER_PRIME | DRIVER_ATOMIC), 586 .load = tilcdc_load, 587 .unload = tilcdc_unload, 588 .lastclose = tilcdc_lastclose, 589 .irq_handler = tilcdc_irq, 590 .get_vblank_counter = drm_vblank_no_hw_counter, 591 .enable_vblank = tilcdc_enable_vblank, 592 .disable_vblank = tilcdc_disable_vblank, 593 .gem_free_object_unlocked = drm_gem_cma_free_object, 594 .gem_vm_ops = &drm_gem_cma_vm_ops, 595 .dumb_create = drm_gem_cma_dumb_create, 596 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 597 .dumb_destroy = drm_gem_dumb_destroy, 598 599 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 600 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 601 .gem_prime_import = drm_gem_prime_import, 602 .gem_prime_export = drm_gem_prime_export, 603 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 604 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 605 .gem_prime_vmap = drm_gem_cma_prime_vmap, 606 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 607 .gem_prime_mmap = drm_gem_cma_prime_mmap, 608 #ifdef CONFIG_DEBUG_FS 609 .debugfs_init = tilcdc_debugfs_init, 610 .debugfs_cleanup = tilcdc_debugfs_cleanup, 611 #endif 612 .fops = &fops, 613 .name = "tilcdc", 614 .desc = "TI LCD Controller DRM", 615 .date = "20121205", 616 .major = 1, 617 .minor = 0, 618 }; 619 620 /* 621 * Power management: 622 */ 623 624 #ifdef CONFIG_PM_SLEEP 625 static int tilcdc_pm_suspend(struct device *dev) 626 { 627 struct drm_device *ddev = dev_get_drvdata(dev); 628 struct tilcdc_drm_private *priv = ddev->dev_private; 629 630 priv->saved_state = drm_atomic_helper_suspend(ddev); 631 632 /* Select sleep pin state */ 633 pinctrl_pm_select_sleep_state(dev); 634 635 return 0; 636 } 637 638 static int tilcdc_pm_resume(struct device *dev) 639 { 640 struct drm_device *ddev = dev_get_drvdata(dev); 641 struct tilcdc_drm_private *priv = ddev->dev_private; 642 int ret = 0; 643 644 /* Select default pin state */ 645 pinctrl_pm_select_default_state(dev); 646 647 if (priv->saved_state) 648 ret = drm_atomic_helper_resume(ddev, priv->saved_state); 649 650 return ret; 651 } 652 #endif 653 654 static const struct dev_pm_ops tilcdc_pm_ops = { 655 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 656 }; 657 658 /* 659 * Platform driver: 660 */ 661 662 static int tilcdc_bind(struct device *dev) 663 { 664 return drm_platform_init(&tilcdc_driver, to_platform_device(dev)); 665 } 666 667 static void tilcdc_unbind(struct device *dev) 668 { 669 struct drm_device *ddev = dev_get_drvdata(dev); 670 671 /* Check if a subcomponent has already triggered the unloading. */ 672 if (!ddev->dev_private) 673 return; 674 675 drm_put_dev(dev_get_drvdata(dev)); 676 } 677 678 static const struct component_master_ops tilcdc_comp_ops = { 679 .bind = tilcdc_bind, 680 .unbind = tilcdc_unbind, 681 }; 682 683 static int tilcdc_pdev_probe(struct platform_device *pdev) 684 { 685 struct component_match *match = NULL; 686 int ret; 687 688 /* bail out early if no DT data: */ 689 if (!pdev->dev.of_node) { 690 dev_err(&pdev->dev, "device-tree data is missing\n"); 691 return -ENXIO; 692 } 693 694 ret = tilcdc_get_external_components(&pdev->dev, &match); 695 if (ret < 0) 696 return ret; 697 else if (ret == 0) 698 return drm_platform_init(&tilcdc_driver, pdev); 699 else 700 return component_master_add_with_match(&pdev->dev, 701 &tilcdc_comp_ops, 702 match); 703 } 704 705 static int tilcdc_pdev_remove(struct platform_device *pdev) 706 { 707 int ret; 708 709 ret = tilcdc_get_external_components(&pdev->dev, NULL); 710 if (ret < 0) 711 return ret; 712 else if (ret == 0) 713 drm_put_dev(platform_get_drvdata(pdev)); 714 else 715 component_master_del(&pdev->dev, &tilcdc_comp_ops); 716 717 return 0; 718 } 719 720 static struct of_device_id tilcdc_of_match[] = { 721 { .compatible = "ti,am33xx-tilcdc", }, 722 { }, 723 }; 724 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 725 726 static struct platform_driver tilcdc_platform_driver = { 727 .probe = tilcdc_pdev_probe, 728 .remove = tilcdc_pdev_remove, 729 .driver = { 730 .name = "tilcdc", 731 .pm = &tilcdc_pm_ops, 732 .of_match_table = tilcdc_of_match, 733 }, 734 }; 735 736 static int __init tilcdc_drm_init(void) 737 { 738 DBG("init"); 739 tilcdc_tfp410_init(); 740 tilcdc_panel_init(); 741 return platform_driver_register(&tilcdc_platform_driver); 742 } 743 744 static void __exit tilcdc_drm_fini(void) 745 { 746 DBG("fini"); 747 platform_driver_unregister(&tilcdc_platform_driver); 748 tilcdc_panel_fini(); 749 tilcdc_tfp410_fini(); 750 } 751 752 module_init(tilcdc_drm_init); 753 module_exit(tilcdc_drm_fini); 754 755 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 756 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 757 MODULE_LICENSE("GPL"); 758