1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* LCDC DRM driver, based on da8xx-fb */ 19 20 #include <linux/component.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/suspend.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 26 #include "tilcdc_drv.h" 27 #include "tilcdc_regs.h" 28 #include "tilcdc_tfp410.h" 29 #include "tilcdc_panel.h" 30 #include "tilcdc_external.h" 31 32 #include "drm_fb_helper.h" 33 34 static LIST_HEAD(module_list); 35 36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 37 38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 39 DRM_FORMAT_BGR888, 40 DRM_FORMAT_XBGR8888 }; 41 42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 43 DRM_FORMAT_RGB888, 44 DRM_FORMAT_XRGB8888 }; 45 46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 47 DRM_FORMAT_RGB888, 48 DRM_FORMAT_XRGB8888 }; 49 50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 51 const struct tilcdc_module_ops *funcs) 52 { 53 mod->name = name; 54 mod->funcs = funcs; 55 INIT_LIST_HEAD(&mod->list); 56 list_add(&mod->list, &module_list); 57 } 58 59 void tilcdc_module_cleanup(struct tilcdc_module *mod) 60 { 61 list_del(&mod->list); 62 } 63 64 static struct of_device_id tilcdc_of_match[]; 65 66 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 67 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) 68 { 69 return drm_fb_cma_create(dev, file_priv, mode_cmd); 70 } 71 72 static void tilcdc_fb_output_poll_changed(struct drm_device *dev) 73 { 74 struct tilcdc_drm_private *priv = dev->dev_private; 75 drm_fbdev_cma_hotplug_event(priv->fbdev); 76 } 77 78 static int tilcdc_atomic_check(struct drm_device *dev, 79 struct drm_atomic_state *state) 80 { 81 int ret; 82 83 ret = drm_atomic_helper_check_modeset(dev, state); 84 if (ret) 85 return ret; 86 87 ret = drm_atomic_helper_check_planes(dev, state); 88 if (ret) 89 return ret; 90 91 /* 92 * tilcdc ->atomic_check can update ->mode_changed if pixel format 93 * changes, hence will we check modeset changes again. 94 */ 95 ret = drm_atomic_helper_check_modeset(dev, state); 96 if (ret) 97 return ret; 98 99 return ret; 100 } 101 102 static int tilcdc_commit(struct drm_device *dev, 103 struct drm_atomic_state *state, 104 bool async) 105 { 106 int ret; 107 108 ret = drm_atomic_helper_prepare_planes(dev, state); 109 if (ret) 110 return ret; 111 112 drm_atomic_helper_swap_state(state, true); 113 114 /* 115 * Everything below can be run asynchronously without the need to grab 116 * any modeset locks at all under one condition: It must be guaranteed 117 * that the asynchronous work has either been cancelled (if the driver 118 * supports it, which at least requires that the framebuffers get 119 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 120 * before the new state gets committed on the software side with 121 * drm_atomic_helper_swap_state(). 122 * 123 * This scheme allows new atomic state updates to be prepared and 124 * checked in parallel to the asynchronous completion of the previous 125 * update. Which is important since compositors need to figure out the 126 * composition of the next frame right after having submitted the 127 * current layout. 128 */ 129 130 drm_atomic_helper_commit_modeset_disables(dev, state); 131 132 drm_atomic_helper_commit_planes(dev, state, 0); 133 134 drm_atomic_helper_commit_modeset_enables(dev, state); 135 136 drm_atomic_helper_wait_for_vblanks(dev, state); 137 138 drm_atomic_helper_cleanup_planes(dev, state); 139 140 return 0; 141 } 142 143 static const struct drm_mode_config_funcs mode_config_funcs = { 144 .fb_create = tilcdc_fb_create, 145 .output_poll_changed = tilcdc_fb_output_poll_changed, 146 .atomic_check = tilcdc_atomic_check, 147 .atomic_commit = tilcdc_commit, 148 }; 149 150 static void modeset_init(struct drm_device *dev) 151 { 152 struct tilcdc_drm_private *priv = dev->dev_private; 153 struct tilcdc_module *mod; 154 155 list_for_each_entry(mod, &module_list, list) { 156 DBG("loading module: %s", mod->name); 157 mod->funcs->modeset_init(mod, dev); 158 } 159 160 dev->mode_config.min_width = 0; 161 dev->mode_config.min_height = 0; 162 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 163 dev->mode_config.max_height = 2048; 164 dev->mode_config.funcs = &mode_config_funcs; 165 } 166 167 #ifdef CONFIG_CPU_FREQ 168 static int cpufreq_transition(struct notifier_block *nb, 169 unsigned long val, void *data) 170 { 171 struct tilcdc_drm_private *priv = container_of(nb, 172 struct tilcdc_drm_private, freq_transition); 173 174 if (val == CPUFREQ_POSTCHANGE) 175 tilcdc_crtc_update_clk(priv->crtc); 176 177 return 0; 178 } 179 #endif 180 181 /* 182 * DRM operations: 183 */ 184 185 static void tilcdc_fini(struct drm_device *dev) 186 { 187 struct tilcdc_drm_private *priv = dev->dev_private; 188 189 if (priv->crtc) 190 tilcdc_crtc_shutdown(priv->crtc); 191 192 if (priv->is_registered) 193 drm_dev_unregister(dev); 194 195 drm_kms_helper_poll_fini(dev); 196 197 if (priv->fbdev) 198 drm_fbdev_cma_fini(priv->fbdev); 199 200 drm_irq_uninstall(dev); 201 drm_mode_config_cleanup(dev); 202 tilcdc_remove_external_device(dev); 203 204 #ifdef CONFIG_CPU_FREQ 205 if (priv->freq_transition.notifier_call) 206 cpufreq_unregister_notifier(&priv->freq_transition, 207 CPUFREQ_TRANSITION_NOTIFIER); 208 #endif 209 210 if (priv->clk) 211 clk_put(priv->clk); 212 213 if (priv->mmio) 214 iounmap(priv->mmio); 215 216 if (priv->wq) { 217 flush_workqueue(priv->wq); 218 destroy_workqueue(priv->wq); 219 } 220 221 dev->dev_private = NULL; 222 223 pm_runtime_disable(dev->dev); 224 225 drm_dev_unref(dev); 226 } 227 228 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) 229 { 230 struct drm_device *ddev; 231 struct platform_device *pdev = to_platform_device(dev); 232 struct device_node *node = dev->of_node; 233 struct tilcdc_drm_private *priv; 234 struct resource *res; 235 u32 bpp = 0; 236 int ret; 237 238 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 239 if (!priv) { 240 dev_err(dev, "failed to allocate private data\n"); 241 return -ENOMEM; 242 } 243 244 ddev = drm_dev_alloc(ddrv, dev); 245 if (IS_ERR(ddev)) 246 return PTR_ERR(ddev); 247 248 ddev->platformdev = pdev; 249 ddev->dev_private = priv; 250 platform_set_drvdata(pdev, ddev); 251 drm_mode_config_init(ddev); 252 253 priv->is_componentized = 254 tilcdc_get_external_components(dev, NULL) > 0; 255 256 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 257 if (!priv->wq) { 258 ret = -ENOMEM; 259 goto init_failed; 260 } 261 262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 263 if (!res) { 264 dev_err(dev, "failed to get memory resource\n"); 265 ret = -EINVAL; 266 goto init_failed; 267 } 268 269 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 270 if (!priv->mmio) { 271 dev_err(dev, "failed to ioremap\n"); 272 ret = -ENOMEM; 273 goto init_failed; 274 } 275 276 priv->clk = clk_get(dev, "fck"); 277 if (IS_ERR(priv->clk)) { 278 dev_err(dev, "failed to get functional clock\n"); 279 ret = -ENODEV; 280 goto init_failed; 281 } 282 283 #ifdef CONFIG_CPU_FREQ 284 priv->freq_transition.notifier_call = cpufreq_transition; 285 ret = cpufreq_register_notifier(&priv->freq_transition, 286 CPUFREQ_TRANSITION_NOTIFIER); 287 if (ret) { 288 dev_err(dev, "failed to register cpufreq notifier\n"); 289 priv->freq_transition.notifier_call = NULL; 290 goto init_failed; 291 } 292 #endif 293 294 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 295 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 296 297 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 298 299 if (of_property_read_u32(node, "max-width", &priv->max_width)) 300 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 301 302 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 303 304 if (of_property_read_u32(node, "max-pixelclock", 305 &priv->max_pixelclock)) 306 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 307 308 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 309 310 pm_runtime_enable(dev); 311 312 /* Determine LCD IP Version */ 313 pm_runtime_get_sync(dev); 314 switch (tilcdc_read(ddev, LCDC_PID_REG)) { 315 case 0x4c100102: 316 priv->rev = 1; 317 break; 318 case 0x4f200800: 319 case 0x4f201000: 320 priv->rev = 2; 321 break; 322 default: 323 dev_warn(dev, "Unknown PID Reg value 0x%08x, " 324 "defaulting to LCD revision 1\n", 325 tilcdc_read(ddev, LCDC_PID_REG)); 326 priv->rev = 1; 327 break; 328 } 329 330 pm_runtime_put_sync(dev); 331 332 if (priv->rev == 1) { 333 DBG("Revision 1 LCDC supports only RGB565 format"); 334 priv->pixelformats = tilcdc_rev1_formats; 335 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 336 bpp = 16; 337 } else { 338 const char *str = "\0"; 339 340 of_property_read_string(node, "blue-and-red-wiring", &str); 341 if (0 == strcmp(str, "crossed")) { 342 DBG("Configured for crossed blue and red wires"); 343 priv->pixelformats = tilcdc_crossed_formats; 344 priv->num_pixelformats = 345 ARRAY_SIZE(tilcdc_crossed_formats); 346 bpp = 32; /* Choose bpp with RGB support for fbdef */ 347 } else if (0 == strcmp(str, "straight")) { 348 DBG("Configured for straight blue and red wires"); 349 priv->pixelformats = tilcdc_straight_formats; 350 priv->num_pixelformats = 351 ARRAY_SIZE(tilcdc_straight_formats); 352 bpp = 16; /* Choose bpp with RGB support for fbdef */ 353 } else { 354 DBG("Blue and red wiring '%s' unknown, use legacy mode", 355 str); 356 priv->pixelformats = tilcdc_legacy_formats; 357 priv->num_pixelformats = 358 ARRAY_SIZE(tilcdc_legacy_formats); 359 bpp = 16; /* This is just a guess */ 360 } 361 } 362 363 ret = tilcdc_crtc_create(ddev); 364 if (ret < 0) { 365 dev_err(dev, "failed to create crtc\n"); 366 goto init_failed; 367 } 368 modeset_init(ddev); 369 370 if (priv->is_componentized) { 371 ret = component_bind_all(dev, ddev); 372 if (ret < 0) 373 goto init_failed; 374 375 ret = tilcdc_add_component_encoder(ddev); 376 if (ret < 0) 377 goto init_failed; 378 } else { 379 ret = tilcdc_attach_external_device(ddev); 380 if (ret) 381 goto init_failed; 382 } 383 384 if (!priv->external_connector && 385 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { 386 dev_err(dev, "no encoders/connectors found\n"); 387 ret = -ENXIO; 388 goto init_failed; 389 } 390 391 ret = drm_vblank_init(ddev, 1); 392 if (ret < 0) { 393 dev_err(dev, "failed to initialize vblank\n"); 394 goto init_failed; 395 } 396 397 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); 398 if (ret < 0) { 399 dev_err(dev, "failed to install IRQ handler\n"); 400 goto init_failed; 401 } 402 403 drm_mode_config_reset(ddev); 404 405 priv->fbdev = drm_fbdev_cma_init(ddev, bpp, 406 ddev->mode_config.num_connector); 407 if (IS_ERR(priv->fbdev)) { 408 ret = PTR_ERR(priv->fbdev); 409 goto init_failed; 410 } 411 412 drm_kms_helper_poll_init(ddev); 413 414 ret = drm_dev_register(ddev, 0); 415 if (ret) 416 goto init_failed; 417 418 priv->is_registered = true; 419 return 0; 420 421 init_failed: 422 tilcdc_fini(ddev); 423 424 return ret; 425 } 426 427 static void tilcdc_lastclose(struct drm_device *dev) 428 { 429 struct tilcdc_drm_private *priv = dev->dev_private; 430 drm_fbdev_cma_restore_mode(priv->fbdev); 431 } 432 433 static irqreturn_t tilcdc_irq(int irq, void *arg) 434 { 435 struct drm_device *dev = arg; 436 struct tilcdc_drm_private *priv = dev->dev_private; 437 return tilcdc_crtc_irq(priv->crtc); 438 } 439 440 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe) 441 { 442 return 0; 443 } 444 445 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe) 446 { 447 return; 448 } 449 450 #if defined(CONFIG_DEBUG_FS) 451 static const struct { 452 const char *name; 453 uint8_t rev; 454 uint8_t save; 455 uint32_t reg; 456 } registers[] = { 457 #define REG(rev, save, reg) { #reg, rev, save, reg } 458 /* exists in revision 1: */ 459 REG(1, false, LCDC_PID_REG), 460 REG(1, true, LCDC_CTRL_REG), 461 REG(1, false, LCDC_STAT_REG), 462 REG(1, true, LCDC_RASTER_CTRL_REG), 463 REG(1, true, LCDC_RASTER_TIMING_0_REG), 464 REG(1, true, LCDC_RASTER_TIMING_1_REG), 465 REG(1, true, LCDC_RASTER_TIMING_2_REG), 466 REG(1, true, LCDC_DMA_CTRL_REG), 467 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 468 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 469 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 470 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 471 /* new in revision 2: */ 472 REG(2, false, LCDC_RAW_STAT_REG), 473 REG(2, false, LCDC_MASKED_STAT_REG), 474 REG(2, true, LCDC_INT_ENABLE_SET_REG), 475 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 476 REG(2, false, LCDC_END_OF_INT_IND_REG), 477 REG(2, true, LCDC_CLK_ENABLE_REG), 478 #undef REG 479 }; 480 481 #endif 482 483 #ifdef CONFIG_DEBUG_FS 484 static int tilcdc_regs_show(struct seq_file *m, void *arg) 485 { 486 struct drm_info_node *node = (struct drm_info_node *) m->private; 487 struct drm_device *dev = node->minor->dev; 488 struct tilcdc_drm_private *priv = dev->dev_private; 489 unsigned i; 490 491 pm_runtime_get_sync(dev->dev); 492 493 seq_printf(m, "revision: %d\n", priv->rev); 494 495 for (i = 0; i < ARRAY_SIZE(registers); i++) 496 if (priv->rev >= registers[i].rev) 497 seq_printf(m, "%s:\t %08x\n", registers[i].name, 498 tilcdc_read(dev, registers[i].reg)); 499 500 pm_runtime_put_sync(dev->dev); 501 502 return 0; 503 } 504 505 static int tilcdc_mm_show(struct seq_file *m, void *arg) 506 { 507 struct drm_info_node *node = (struct drm_info_node *) m->private; 508 struct drm_device *dev = node->minor->dev; 509 struct drm_printer p = drm_seq_file_printer(m); 510 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 511 return 0; 512 } 513 514 static struct drm_info_list tilcdc_debugfs_list[] = { 515 { "regs", tilcdc_regs_show, 0 }, 516 { "mm", tilcdc_mm_show, 0 }, 517 { "fb", drm_fb_cma_debugfs_show, 0 }, 518 }; 519 520 static int tilcdc_debugfs_init(struct drm_minor *minor) 521 { 522 struct drm_device *dev = minor->dev; 523 struct tilcdc_module *mod; 524 int ret; 525 526 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 527 ARRAY_SIZE(tilcdc_debugfs_list), 528 minor->debugfs_root, minor); 529 530 list_for_each_entry(mod, &module_list, list) 531 if (mod->funcs->debugfs_init) 532 mod->funcs->debugfs_init(mod, minor); 533 534 if (ret) { 535 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 536 return ret; 537 } 538 539 return ret; 540 } 541 #endif 542 543 static const struct file_operations fops = { 544 .owner = THIS_MODULE, 545 .open = drm_open, 546 .release = drm_release, 547 .unlocked_ioctl = drm_ioctl, 548 .compat_ioctl = drm_compat_ioctl, 549 .poll = drm_poll, 550 .read = drm_read, 551 .llseek = no_llseek, 552 .mmap = drm_gem_cma_mmap, 553 }; 554 555 static struct drm_driver tilcdc_driver = { 556 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET | 557 DRIVER_PRIME | DRIVER_ATOMIC), 558 .lastclose = tilcdc_lastclose, 559 .irq_handler = tilcdc_irq, 560 .get_vblank_counter = drm_vblank_no_hw_counter, 561 .enable_vblank = tilcdc_enable_vblank, 562 .disable_vblank = tilcdc_disable_vblank, 563 .gem_free_object_unlocked = drm_gem_cma_free_object, 564 .gem_vm_ops = &drm_gem_cma_vm_ops, 565 .dumb_create = drm_gem_cma_dumb_create, 566 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 567 .dumb_destroy = drm_gem_dumb_destroy, 568 569 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 570 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 571 .gem_prime_import = drm_gem_prime_import, 572 .gem_prime_export = drm_gem_prime_export, 573 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 574 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 575 .gem_prime_vmap = drm_gem_cma_prime_vmap, 576 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 577 .gem_prime_mmap = drm_gem_cma_prime_mmap, 578 #ifdef CONFIG_DEBUG_FS 579 .debugfs_init = tilcdc_debugfs_init, 580 #endif 581 .fops = &fops, 582 .name = "tilcdc", 583 .desc = "TI LCD Controller DRM", 584 .date = "20121205", 585 .major = 1, 586 .minor = 0, 587 }; 588 589 /* 590 * Power management: 591 */ 592 593 #ifdef CONFIG_PM_SLEEP 594 static int tilcdc_pm_suspend(struct device *dev) 595 { 596 struct drm_device *ddev = dev_get_drvdata(dev); 597 struct tilcdc_drm_private *priv = ddev->dev_private; 598 599 priv->saved_state = drm_atomic_helper_suspend(ddev); 600 601 /* Select sleep pin state */ 602 pinctrl_pm_select_sleep_state(dev); 603 604 return 0; 605 } 606 607 static int tilcdc_pm_resume(struct device *dev) 608 { 609 struct drm_device *ddev = dev_get_drvdata(dev); 610 struct tilcdc_drm_private *priv = ddev->dev_private; 611 int ret = 0; 612 613 /* Select default pin state */ 614 pinctrl_pm_select_default_state(dev); 615 616 if (priv->saved_state) 617 ret = drm_atomic_helper_resume(ddev, priv->saved_state); 618 619 return ret; 620 } 621 #endif 622 623 static const struct dev_pm_ops tilcdc_pm_ops = { 624 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 625 }; 626 627 /* 628 * Platform driver: 629 */ 630 static int tilcdc_bind(struct device *dev) 631 { 632 return tilcdc_init(&tilcdc_driver, dev); 633 } 634 635 static void tilcdc_unbind(struct device *dev) 636 { 637 struct drm_device *ddev = dev_get_drvdata(dev); 638 639 /* Check if a subcomponent has already triggered the unloading. */ 640 if (!ddev->dev_private) 641 return; 642 643 tilcdc_fini(dev_get_drvdata(dev)); 644 } 645 646 static const struct component_master_ops tilcdc_comp_ops = { 647 .bind = tilcdc_bind, 648 .unbind = tilcdc_unbind, 649 }; 650 651 static int tilcdc_pdev_probe(struct platform_device *pdev) 652 { 653 struct component_match *match = NULL; 654 int ret; 655 656 /* bail out early if no DT data: */ 657 if (!pdev->dev.of_node) { 658 dev_err(&pdev->dev, "device-tree data is missing\n"); 659 return -ENXIO; 660 } 661 662 ret = tilcdc_get_external_components(&pdev->dev, &match); 663 if (ret < 0) 664 return ret; 665 else if (ret == 0) 666 return tilcdc_init(&tilcdc_driver, &pdev->dev); 667 else 668 return component_master_add_with_match(&pdev->dev, 669 &tilcdc_comp_ops, 670 match); 671 } 672 673 static int tilcdc_pdev_remove(struct platform_device *pdev) 674 { 675 int ret; 676 677 ret = tilcdc_get_external_components(&pdev->dev, NULL); 678 if (ret < 0) 679 return ret; 680 else if (ret == 0) 681 tilcdc_fini(platform_get_drvdata(pdev)); 682 else 683 component_master_del(&pdev->dev, &tilcdc_comp_ops); 684 685 return 0; 686 } 687 688 static struct of_device_id tilcdc_of_match[] = { 689 { .compatible = "ti,am33xx-tilcdc", }, 690 { .compatible = "ti,da850-tilcdc", }, 691 { }, 692 }; 693 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 694 695 static struct platform_driver tilcdc_platform_driver = { 696 .probe = tilcdc_pdev_probe, 697 .remove = tilcdc_pdev_remove, 698 .driver = { 699 .name = "tilcdc", 700 .pm = &tilcdc_pm_ops, 701 .of_match_table = tilcdc_of_match, 702 }, 703 }; 704 705 static int __init tilcdc_drm_init(void) 706 { 707 DBG("init"); 708 tilcdc_tfp410_init(); 709 tilcdc_panel_init(); 710 return platform_driver_register(&tilcdc_platform_driver); 711 } 712 713 static void __exit tilcdc_drm_fini(void) 714 { 715 DBG("fini"); 716 platform_driver_unregister(&tilcdc_platform_driver); 717 tilcdc_panel_fini(); 718 tilcdc_tfp410_fini(); 719 } 720 721 module_init(tilcdc_drm_init); 722 module_exit(tilcdc_drm_fini); 723 724 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 725 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 726 MODULE_LICENSE("GPL"); 727