1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 /* LCDC DRM driver, based on da8xx-fb */ 8 9 #include <linux/component.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_debugfs.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fb_helper.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_irq.h> 24 #include <drm/drm_mm.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 29 #include "tilcdc_drv.h" 30 #include "tilcdc_external.h" 31 #include "tilcdc_panel.h" 32 #include "tilcdc_regs.h" 33 #include "tilcdc_tfp410.h" 34 35 static LIST_HEAD(module_list); 36 37 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 38 39 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 40 DRM_FORMAT_BGR888, 41 DRM_FORMAT_XBGR8888 }; 42 43 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 44 DRM_FORMAT_RGB888, 45 DRM_FORMAT_XRGB8888 }; 46 47 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 48 DRM_FORMAT_RGB888, 49 DRM_FORMAT_XRGB8888 }; 50 51 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 52 const struct tilcdc_module_ops *funcs) 53 { 54 mod->name = name; 55 mod->funcs = funcs; 56 INIT_LIST_HEAD(&mod->list); 57 list_add(&mod->list, &module_list); 58 } 59 60 void tilcdc_module_cleanup(struct tilcdc_module *mod) 61 { 62 list_del(&mod->list); 63 } 64 65 static struct of_device_id tilcdc_of_match[]; 66 67 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 68 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) 69 { 70 return drm_gem_fb_create(dev, file_priv, mode_cmd); 71 } 72 73 static int tilcdc_atomic_check(struct drm_device *dev, 74 struct drm_atomic_state *state) 75 { 76 int ret; 77 78 ret = drm_atomic_helper_check_modeset(dev, state); 79 if (ret) 80 return ret; 81 82 ret = drm_atomic_helper_check_planes(dev, state); 83 if (ret) 84 return ret; 85 86 /* 87 * tilcdc ->atomic_check can update ->mode_changed if pixel format 88 * changes, hence will we check modeset changes again. 89 */ 90 ret = drm_atomic_helper_check_modeset(dev, state); 91 if (ret) 92 return ret; 93 94 return ret; 95 } 96 97 static int tilcdc_commit(struct drm_device *dev, 98 struct drm_atomic_state *state, 99 bool async) 100 { 101 int ret; 102 103 ret = drm_atomic_helper_prepare_planes(dev, state); 104 if (ret) 105 return ret; 106 107 ret = drm_atomic_helper_swap_state(state, true); 108 if (ret) { 109 drm_atomic_helper_cleanup_planes(dev, state); 110 return ret; 111 } 112 113 /* 114 * Everything below can be run asynchronously without the need to grab 115 * any modeset locks at all under one condition: It must be guaranteed 116 * that the asynchronous work has either been cancelled (if the driver 117 * supports it, which at least requires that the framebuffers get 118 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 119 * before the new state gets committed on the software side with 120 * drm_atomic_helper_swap_state(). 121 * 122 * This scheme allows new atomic state updates to be prepared and 123 * checked in parallel to the asynchronous completion of the previous 124 * update. Which is important since compositors need to figure out the 125 * composition of the next frame right after having submitted the 126 * current layout. 127 */ 128 129 drm_atomic_helper_commit_modeset_disables(dev, state); 130 131 drm_atomic_helper_commit_planes(dev, state, 0); 132 133 drm_atomic_helper_commit_modeset_enables(dev, state); 134 135 drm_atomic_helper_wait_for_vblanks(dev, state); 136 137 drm_atomic_helper_cleanup_planes(dev, state); 138 139 return 0; 140 } 141 142 static const struct drm_mode_config_funcs mode_config_funcs = { 143 .fb_create = tilcdc_fb_create, 144 .atomic_check = tilcdc_atomic_check, 145 .atomic_commit = tilcdc_commit, 146 }; 147 148 static void modeset_init(struct drm_device *dev) 149 { 150 struct tilcdc_drm_private *priv = dev->dev_private; 151 struct tilcdc_module *mod; 152 153 list_for_each_entry(mod, &module_list, list) { 154 DBG("loading module: %s", mod->name); 155 mod->funcs->modeset_init(mod, dev); 156 } 157 158 dev->mode_config.min_width = 0; 159 dev->mode_config.min_height = 0; 160 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 161 dev->mode_config.max_height = 2048; 162 dev->mode_config.funcs = &mode_config_funcs; 163 } 164 165 #ifdef CONFIG_CPU_FREQ 166 static int cpufreq_transition(struct notifier_block *nb, 167 unsigned long val, void *data) 168 { 169 struct tilcdc_drm_private *priv = container_of(nb, 170 struct tilcdc_drm_private, freq_transition); 171 172 if (val == CPUFREQ_POSTCHANGE) 173 tilcdc_crtc_update_clk(priv->crtc); 174 175 return 0; 176 } 177 #endif 178 179 /* 180 * DRM operations: 181 */ 182 183 static void tilcdc_fini(struct drm_device *dev) 184 { 185 struct tilcdc_drm_private *priv = dev->dev_private; 186 187 #ifdef CONFIG_CPU_FREQ 188 if (priv->freq_transition.notifier_call) 189 cpufreq_unregister_notifier(&priv->freq_transition, 190 CPUFREQ_TRANSITION_NOTIFIER); 191 #endif 192 193 if (priv->crtc) 194 tilcdc_crtc_shutdown(priv->crtc); 195 196 if (priv->is_registered) 197 drm_dev_unregister(dev); 198 199 drm_kms_helper_poll_fini(dev); 200 drm_irq_uninstall(dev); 201 drm_mode_config_cleanup(dev); 202 203 if (priv->clk) 204 clk_put(priv->clk); 205 206 if (priv->mmio) 207 iounmap(priv->mmio); 208 209 if (priv->wq) { 210 flush_workqueue(priv->wq); 211 destroy_workqueue(priv->wq); 212 } 213 214 dev->dev_private = NULL; 215 216 pm_runtime_disable(dev->dev); 217 218 drm_dev_put(dev); 219 } 220 221 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) 222 { 223 struct drm_device *ddev; 224 struct platform_device *pdev = to_platform_device(dev); 225 struct device_node *node = dev->of_node; 226 struct tilcdc_drm_private *priv; 227 struct resource *res; 228 u32 bpp = 0; 229 int ret; 230 231 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 232 if (!priv) 233 return -ENOMEM; 234 235 ddev = drm_dev_alloc(ddrv, dev); 236 if (IS_ERR(ddev)) 237 return PTR_ERR(ddev); 238 239 ddev->dev_private = priv; 240 platform_set_drvdata(pdev, ddev); 241 drm_mode_config_init(ddev); 242 243 priv->is_componentized = 244 tilcdc_get_external_components(dev, NULL) > 0; 245 246 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 247 if (!priv->wq) { 248 ret = -ENOMEM; 249 goto init_failed; 250 } 251 252 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 253 if (!res) { 254 dev_err(dev, "failed to get memory resource\n"); 255 ret = -EINVAL; 256 goto init_failed; 257 } 258 259 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 260 if (!priv->mmio) { 261 dev_err(dev, "failed to ioremap\n"); 262 ret = -ENOMEM; 263 goto init_failed; 264 } 265 266 priv->clk = clk_get(dev, "fck"); 267 if (IS_ERR(priv->clk)) { 268 dev_err(dev, "failed to get functional clock\n"); 269 ret = -ENODEV; 270 goto init_failed; 271 } 272 273 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 274 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 275 276 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 277 278 if (of_property_read_u32(node, "max-width", &priv->max_width)) 279 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 280 281 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 282 283 if (of_property_read_u32(node, "max-pixelclock", 284 &priv->max_pixelclock)) 285 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 286 287 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 288 289 pm_runtime_enable(dev); 290 291 /* Determine LCD IP Version */ 292 pm_runtime_get_sync(dev); 293 switch (tilcdc_read(ddev, LCDC_PID_REG)) { 294 case 0x4c100102: 295 priv->rev = 1; 296 break; 297 case 0x4f200800: 298 case 0x4f201000: 299 priv->rev = 2; 300 break; 301 default: 302 dev_warn(dev, "Unknown PID Reg value 0x%08x, " 303 "defaulting to LCD revision 1\n", 304 tilcdc_read(ddev, LCDC_PID_REG)); 305 priv->rev = 1; 306 break; 307 } 308 309 pm_runtime_put_sync(dev); 310 311 if (priv->rev == 1) { 312 DBG("Revision 1 LCDC supports only RGB565 format"); 313 priv->pixelformats = tilcdc_rev1_formats; 314 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 315 bpp = 16; 316 } else { 317 const char *str = "\0"; 318 319 of_property_read_string(node, "blue-and-red-wiring", &str); 320 if (0 == strcmp(str, "crossed")) { 321 DBG("Configured for crossed blue and red wires"); 322 priv->pixelformats = tilcdc_crossed_formats; 323 priv->num_pixelformats = 324 ARRAY_SIZE(tilcdc_crossed_formats); 325 bpp = 32; /* Choose bpp with RGB support for fbdef */ 326 } else if (0 == strcmp(str, "straight")) { 327 DBG("Configured for straight blue and red wires"); 328 priv->pixelformats = tilcdc_straight_formats; 329 priv->num_pixelformats = 330 ARRAY_SIZE(tilcdc_straight_formats); 331 bpp = 16; /* Choose bpp with RGB support for fbdef */ 332 } else { 333 DBG("Blue and red wiring '%s' unknown, use legacy mode", 334 str); 335 priv->pixelformats = tilcdc_legacy_formats; 336 priv->num_pixelformats = 337 ARRAY_SIZE(tilcdc_legacy_formats); 338 bpp = 16; /* This is just a guess */ 339 } 340 } 341 342 ret = tilcdc_crtc_create(ddev); 343 if (ret < 0) { 344 dev_err(dev, "failed to create crtc\n"); 345 goto init_failed; 346 } 347 modeset_init(ddev); 348 349 #ifdef CONFIG_CPU_FREQ 350 priv->freq_transition.notifier_call = cpufreq_transition; 351 ret = cpufreq_register_notifier(&priv->freq_transition, 352 CPUFREQ_TRANSITION_NOTIFIER); 353 if (ret) { 354 dev_err(dev, "failed to register cpufreq notifier\n"); 355 priv->freq_transition.notifier_call = NULL; 356 goto init_failed; 357 } 358 #endif 359 360 if (priv->is_componentized) { 361 ret = component_bind_all(dev, ddev); 362 if (ret < 0) 363 goto init_failed; 364 365 ret = tilcdc_add_component_encoder(ddev); 366 if (ret < 0) 367 goto init_failed; 368 } else { 369 ret = tilcdc_attach_external_device(ddev); 370 if (ret) 371 goto init_failed; 372 } 373 374 if (!priv->external_connector && 375 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { 376 dev_err(dev, "no encoders/connectors found\n"); 377 ret = -EPROBE_DEFER; 378 goto init_failed; 379 } 380 381 ret = drm_vblank_init(ddev, 1); 382 if (ret < 0) { 383 dev_err(dev, "failed to initialize vblank\n"); 384 goto init_failed; 385 } 386 387 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); 388 if (ret < 0) { 389 dev_err(dev, "failed to install IRQ handler\n"); 390 goto init_failed; 391 } 392 393 drm_mode_config_reset(ddev); 394 395 drm_kms_helper_poll_init(ddev); 396 397 ret = drm_dev_register(ddev, 0); 398 if (ret) 399 goto init_failed; 400 401 drm_fbdev_generic_setup(ddev, bpp); 402 403 priv->is_registered = true; 404 return 0; 405 406 init_failed: 407 tilcdc_fini(ddev); 408 409 return ret; 410 } 411 412 static irqreturn_t tilcdc_irq(int irq, void *arg) 413 { 414 struct drm_device *dev = arg; 415 struct tilcdc_drm_private *priv = dev->dev_private; 416 return tilcdc_crtc_irq(priv->crtc); 417 } 418 419 #if defined(CONFIG_DEBUG_FS) 420 static const struct { 421 const char *name; 422 uint8_t rev; 423 uint8_t save; 424 uint32_t reg; 425 } registers[] = { 426 #define REG(rev, save, reg) { #reg, rev, save, reg } 427 /* exists in revision 1: */ 428 REG(1, false, LCDC_PID_REG), 429 REG(1, true, LCDC_CTRL_REG), 430 REG(1, false, LCDC_STAT_REG), 431 REG(1, true, LCDC_RASTER_CTRL_REG), 432 REG(1, true, LCDC_RASTER_TIMING_0_REG), 433 REG(1, true, LCDC_RASTER_TIMING_1_REG), 434 REG(1, true, LCDC_RASTER_TIMING_2_REG), 435 REG(1, true, LCDC_DMA_CTRL_REG), 436 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 437 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 438 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 439 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 440 /* new in revision 2: */ 441 REG(2, false, LCDC_RAW_STAT_REG), 442 REG(2, false, LCDC_MASKED_STAT_REG), 443 REG(2, true, LCDC_INT_ENABLE_SET_REG), 444 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 445 REG(2, false, LCDC_END_OF_INT_IND_REG), 446 REG(2, true, LCDC_CLK_ENABLE_REG), 447 #undef REG 448 }; 449 450 #endif 451 452 #ifdef CONFIG_DEBUG_FS 453 static int tilcdc_regs_show(struct seq_file *m, void *arg) 454 { 455 struct drm_info_node *node = (struct drm_info_node *) m->private; 456 struct drm_device *dev = node->minor->dev; 457 struct tilcdc_drm_private *priv = dev->dev_private; 458 unsigned i; 459 460 pm_runtime_get_sync(dev->dev); 461 462 seq_printf(m, "revision: %d\n", priv->rev); 463 464 for (i = 0; i < ARRAY_SIZE(registers); i++) 465 if (priv->rev >= registers[i].rev) 466 seq_printf(m, "%s:\t %08x\n", registers[i].name, 467 tilcdc_read(dev, registers[i].reg)); 468 469 pm_runtime_put_sync(dev->dev); 470 471 return 0; 472 } 473 474 static int tilcdc_mm_show(struct seq_file *m, void *arg) 475 { 476 struct drm_info_node *node = (struct drm_info_node *) m->private; 477 struct drm_device *dev = node->minor->dev; 478 struct drm_printer p = drm_seq_file_printer(m); 479 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 480 return 0; 481 } 482 483 static struct drm_info_list tilcdc_debugfs_list[] = { 484 { "regs", tilcdc_regs_show, 0 }, 485 { "mm", tilcdc_mm_show, 0 }, 486 }; 487 488 static int tilcdc_debugfs_init(struct drm_minor *minor) 489 { 490 struct drm_device *dev = minor->dev; 491 struct tilcdc_module *mod; 492 int ret; 493 494 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 495 ARRAY_SIZE(tilcdc_debugfs_list), 496 minor->debugfs_root, minor); 497 498 list_for_each_entry(mod, &module_list, list) 499 if (mod->funcs->debugfs_init) 500 mod->funcs->debugfs_init(mod, minor); 501 502 if (ret) { 503 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 504 return ret; 505 } 506 507 return ret; 508 } 509 #endif 510 511 DEFINE_DRM_GEM_CMA_FOPS(fops); 512 513 static struct drm_driver tilcdc_driver = { 514 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 515 .irq_handler = tilcdc_irq, 516 .gem_free_object_unlocked = drm_gem_cma_free_object, 517 .gem_print_info = drm_gem_cma_print_info, 518 .gem_vm_ops = &drm_gem_cma_vm_ops, 519 .dumb_create = drm_gem_cma_dumb_create, 520 521 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 522 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 523 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 524 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 525 .gem_prime_vmap = drm_gem_cma_prime_vmap, 526 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 527 .gem_prime_mmap = drm_gem_cma_prime_mmap, 528 #ifdef CONFIG_DEBUG_FS 529 .debugfs_init = tilcdc_debugfs_init, 530 #endif 531 .fops = &fops, 532 .name = "tilcdc", 533 .desc = "TI LCD Controller DRM", 534 .date = "20121205", 535 .major = 1, 536 .minor = 0, 537 }; 538 539 /* 540 * Power management: 541 */ 542 543 #ifdef CONFIG_PM_SLEEP 544 static int tilcdc_pm_suspend(struct device *dev) 545 { 546 struct drm_device *ddev = dev_get_drvdata(dev); 547 int ret = 0; 548 549 ret = drm_mode_config_helper_suspend(ddev); 550 551 /* Select sleep pin state */ 552 pinctrl_pm_select_sleep_state(dev); 553 554 return ret; 555 } 556 557 static int tilcdc_pm_resume(struct device *dev) 558 { 559 struct drm_device *ddev = dev_get_drvdata(dev); 560 561 /* Select default pin state */ 562 pinctrl_pm_select_default_state(dev); 563 return drm_mode_config_helper_resume(ddev); 564 } 565 #endif 566 567 static const struct dev_pm_ops tilcdc_pm_ops = { 568 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 569 }; 570 571 /* 572 * Platform driver: 573 */ 574 static int tilcdc_bind(struct device *dev) 575 { 576 return tilcdc_init(&tilcdc_driver, dev); 577 } 578 579 static void tilcdc_unbind(struct device *dev) 580 { 581 struct drm_device *ddev = dev_get_drvdata(dev); 582 583 /* Check if a subcomponent has already triggered the unloading. */ 584 if (!ddev->dev_private) 585 return; 586 587 tilcdc_fini(dev_get_drvdata(dev)); 588 } 589 590 static const struct component_master_ops tilcdc_comp_ops = { 591 .bind = tilcdc_bind, 592 .unbind = tilcdc_unbind, 593 }; 594 595 static int tilcdc_pdev_probe(struct platform_device *pdev) 596 { 597 struct component_match *match = NULL; 598 int ret; 599 600 /* bail out early if no DT data: */ 601 if (!pdev->dev.of_node) { 602 dev_err(&pdev->dev, "device-tree data is missing\n"); 603 return -ENXIO; 604 } 605 606 ret = tilcdc_get_external_components(&pdev->dev, &match); 607 if (ret < 0) 608 return ret; 609 else if (ret == 0) 610 return tilcdc_init(&tilcdc_driver, &pdev->dev); 611 else 612 return component_master_add_with_match(&pdev->dev, 613 &tilcdc_comp_ops, 614 match); 615 } 616 617 static int tilcdc_pdev_remove(struct platform_device *pdev) 618 { 619 int ret; 620 621 ret = tilcdc_get_external_components(&pdev->dev, NULL); 622 if (ret < 0) 623 return ret; 624 else if (ret == 0) 625 tilcdc_fini(platform_get_drvdata(pdev)); 626 else 627 component_master_del(&pdev->dev, &tilcdc_comp_ops); 628 629 return 0; 630 } 631 632 static struct of_device_id tilcdc_of_match[] = { 633 { .compatible = "ti,am33xx-tilcdc", }, 634 { .compatible = "ti,da850-tilcdc", }, 635 { }, 636 }; 637 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 638 639 static struct platform_driver tilcdc_platform_driver = { 640 .probe = tilcdc_pdev_probe, 641 .remove = tilcdc_pdev_remove, 642 .driver = { 643 .name = "tilcdc", 644 .pm = &tilcdc_pm_ops, 645 .of_match_table = tilcdc_of_match, 646 }, 647 }; 648 649 static int __init tilcdc_drm_init(void) 650 { 651 DBG("init"); 652 tilcdc_tfp410_init(); 653 tilcdc_panel_init(); 654 return platform_driver_register(&tilcdc_platform_driver); 655 } 656 657 static void __exit tilcdc_drm_fini(void) 658 { 659 DBG("fini"); 660 platform_driver_unregister(&tilcdc_platform_driver); 661 tilcdc_panel_fini(); 662 tilcdc_tfp410_fini(); 663 } 664 665 module_init(tilcdc_drm_init); 666 module_exit(tilcdc_drm_fini); 667 668 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 669 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 670 MODULE_LICENSE("GPL"); 671