1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 /* LCDC DRM driver, based on da8xx-fb */ 8 9 #include <linux/component.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_debugfs.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fbdev_dma.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem_dma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_mm.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 28 #include "tilcdc_drv.h" 29 #include "tilcdc_external.h" 30 #include "tilcdc_panel.h" 31 #include "tilcdc_regs.h" 32 33 static LIST_HEAD(module_list); 34 35 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 36 37 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 38 DRM_FORMAT_BGR888, 39 DRM_FORMAT_XBGR8888 }; 40 41 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 42 DRM_FORMAT_RGB888, 43 DRM_FORMAT_XRGB8888 }; 44 45 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 46 DRM_FORMAT_RGB888, 47 DRM_FORMAT_XRGB8888 }; 48 49 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 50 const struct tilcdc_module_ops *funcs) 51 { 52 mod->name = name; 53 mod->funcs = funcs; 54 INIT_LIST_HEAD(&mod->list); 55 list_add(&mod->list, &module_list); 56 } 57 58 void tilcdc_module_cleanup(struct tilcdc_module *mod) 59 { 60 list_del(&mod->list); 61 } 62 63 static int tilcdc_atomic_check(struct drm_device *dev, 64 struct drm_atomic_state *state) 65 { 66 int ret; 67 68 ret = drm_atomic_helper_check_modeset(dev, state); 69 if (ret) 70 return ret; 71 72 ret = drm_atomic_helper_check_planes(dev, state); 73 if (ret) 74 return ret; 75 76 /* 77 * tilcdc ->atomic_check can update ->mode_changed if pixel format 78 * changes, hence will we check modeset changes again. 79 */ 80 ret = drm_atomic_helper_check_modeset(dev, state); 81 if (ret) 82 return ret; 83 84 return ret; 85 } 86 87 static const struct drm_mode_config_funcs mode_config_funcs = { 88 .fb_create = drm_gem_fb_create, 89 .atomic_check = tilcdc_atomic_check, 90 .atomic_commit = drm_atomic_helper_commit, 91 }; 92 93 static void modeset_init(struct drm_device *dev) 94 { 95 struct tilcdc_drm_private *priv = dev->dev_private; 96 struct tilcdc_module *mod; 97 98 list_for_each_entry(mod, &module_list, list) { 99 DBG("loading module: %s", mod->name); 100 mod->funcs->modeset_init(mod, dev); 101 } 102 103 dev->mode_config.min_width = 0; 104 dev->mode_config.min_height = 0; 105 dev->mode_config.max_width = priv->max_width; 106 dev->mode_config.max_height = 2048; 107 dev->mode_config.funcs = &mode_config_funcs; 108 } 109 110 #ifdef CONFIG_CPU_FREQ 111 static int cpufreq_transition(struct notifier_block *nb, 112 unsigned long val, void *data) 113 { 114 struct tilcdc_drm_private *priv = container_of(nb, 115 struct tilcdc_drm_private, freq_transition); 116 117 if (val == CPUFREQ_POSTCHANGE) 118 tilcdc_crtc_update_clk(priv->crtc); 119 120 return 0; 121 } 122 #endif 123 124 static irqreturn_t tilcdc_irq(int irq, void *arg) 125 { 126 struct drm_device *dev = arg; 127 struct tilcdc_drm_private *priv = dev->dev_private; 128 129 return tilcdc_crtc_irq(priv->crtc); 130 } 131 132 static int tilcdc_irq_install(struct drm_device *dev, unsigned int irq) 133 { 134 struct tilcdc_drm_private *priv = dev->dev_private; 135 int ret; 136 137 ret = request_irq(irq, tilcdc_irq, 0, dev->driver->name, dev); 138 if (ret) 139 return ret; 140 141 priv->irq_enabled = true; 142 143 return 0; 144 } 145 146 static void tilcdc_irq_uninstall(struct drm_device *dev) 147 { 148 struct tilcdc_drm_private *priv = dev->dev_private; 149 150 if (!priv->irq_enabled) 151 return; 152 153 free_irq(priv->irq, dev); 154 priv->irq_enabled = false; 155 } 156 157 /* 158 * DRM operations: 159 */ 160 161 static void tilcdc_fini(struct drm_device *dev) 162 { 163 struct tilcdc_drm_private *priv = dev->dev_private; 164 165 #ifdef CONFIG_CPU_FREQ 166 if (priv->freq_transition.notifier_call) 167 cpufreq_unregister_notifier(&priv->freq_transition, 168 CPUFREQ_TRANSITION_NOTIFIER); 169 #endif 170 171 if (priv->crtc) 172 tilcdc_crtc_shutdown(priv->crtc); 173 174 if (priv->is_registered) 175 drm_dev_unregister(dev); 176 177 drm_kms_helper_poll_fini(dev); 178 drm_atomic_helper_shutdown(dev); 179 tilcdc_irq_uninstall(dev); 180 drm_mode_config_cleanup(dev); 181 182 if (priv->clk) 183 clk_put(priv->clk); 184 185 if (priv->mmio) 186 iounmap(priv->mmio); 187 188 if (priv->wq) 189 destroy_workqueue(priv->wq); 190 191 dev->dev_private = NULL; 192 193 pm_runtime_disable(dev->dev); 194 195 drm_dev_put(dev); 196 } 197 198 static int tilcdc_init(const struct drm_driver *ddrv, struct device *dev) 199 { 200 struct drm_device *ddev; 201 struct platform_device *pdev = to_platform_device(dev); 202 struct device_node *node = dev->of_node; 203 struct tilcdc_drm_private *priv; 204 struct resource *res; 205 u32 bpp = 0; 206 int ret; 207 208 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 209 if (!priv) 210 return -ENOMEM; 211 212 ddev = drm_dev_alloc(ddrv, dev); 213 if (IS_ERR(ddev)) 214 return PTR_ERR(ddev); 215 216 ddev->dev_private = priv; 217 platform_set_drvdata(pdev, ddev); 218 drm_mode_config_init(ddev); 219 220 priv->is_componentized = 221 tilcdc_get_external_components(dev, NULL) > 0; 222 223 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 224 if (!priv->wq) { 225 ret = -ENOMEM; 226 goto init_failed; 227 } 228 229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 230 if (!res) { 231 dev_err(dev, "failed to get memory resource\n"); 232 ret = -EINVAL; 233 goto init_failed; 234 } 235 236 priv->mmio = ioremap(res->start, resource_size(res)); 237 if (!priv->mmio) { 238 dev_err(dev, "failed to ioremap\n"); 239 ret = -ENOMEM; 240 goto init_failed; 241 } 242 243 priv->clk = clk_get(dev, "fck"); 244 if (IS_ERR(priv->clk)) { 245 dev_err(dev, "failed to get functional clock\n"); 246 ret = -ENODEV; 247 goto init_failed; 248 } 249 250 pm_runtime_enable(dev); 251 252 /* Determine LCD IP Version */ 253 pm_runtime_get_sync(dev); 254 switch (tilcdc_read(ddev, LCDC_PID_REG)) { 255 case 0x4c100102: 256 priv->rev = 1; 257 break; 258 case 0x4f200800: 259 case 0x4f201000: 260 priv->rev = 2; 261 break; 262 default: 263 dev_warn(dev, "Unknown PID Reg value 0x%08x, " 264 "defaulting to LCD revision 1\n", 265 tilcdc_read(ddev, LCDC_PID_REG)); 266 priv->rev = 1; 267 break; 268 } 269 270 pm_runtime_put_sync(dev); 271 272 if (priv->rev == 1) { 273 DBG("Revision 1 LCDC supports only RGB565 format"); 274 priv->pixelformats = tilcdc_rev1_formats; 275 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 276 bpp = 16; 277 } else { 278 const char *str = "\0"; 279 280 of_property_read_string(node, "blue-and-red-wiring", &str); 281 if (0 == strcmp(str, "crossed")) { 282 DBG("Configured for crossed blue and red wires"); 283 priv->pixelformats = tilcdc_crossed_formats; 284 priv->num_pixelformats = 285 ARRAY_SIZE(tilcdc_crossed_formats); 286 bpp = 32; /* Choose bpp with RGB support for fbdef */ 287 } else if (0 == strcmp(str, "straight")) { 288 DBG("Configured for straight blue and red wires"); 289 priv->pixelformats = tilcdc_straight_formats; 290 priv->num_pixelformats = 291 ARRAY_SIZE(tilcdc_straight_formats); 292 bpp = 16; /* Choose bpp with RGB support for fbdef */ 293 } else { 294 DBG("Blue and red wiring '%s' unknown, use legacy mode", 295 str); 296 priv->pixelformats = tilcdc_legacy_formats; 297 priv->num_pixelformats = 298 ARRAY_SIZE(tilcdc_legacy_formats); 299 bpp = 16; /* This is just a guess */ 300 } 301 } 302 303 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 304 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 305 306 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 307 308 if (of_property_read_u32(node, "max-width", &priv->max_width)) { 309 if (priv->rev == 1) 310 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V1; 311 else 312 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V2; 313 } 314 315 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 316 317 if (of_property_read_u32(node, "max-pixelclock", 318 &priv->max_pixelclock)) 319 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 320 321 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 322 323 ret = tilcdc_crtc_create(ddev); 324 if (ret < 0) { 325 dev_err(dev, "failed to create crtc\n"); 326 goto init_failed; 327 } 328 modeset_init(ddev); 329 330 #ifdef CONFIG_CPU_FREQ 331 priv->freq_transition.notifier_call = cpufreq_transition; 332 ret = cpufreq_register_notifier(&priv->freq_transition, 333 CPUFREQ_TRANSITION_NOTIFIER); 334 if (ret) { 335 dev_err(dev, "failed to register cpufreq notifier\n"); 336 priv->freq_transition.notifier_call = NULL; 337 goto init_failed; 338 } 339 #endif 340 341 if (priv->is_componentized) { 342 ret = component_bind_all(dev, ddev); 343 if (ret < 0) 344 goto init_failed; 345 346 ret = tilcdc_add_component_encoder(ddev); 347 if (ret < 0) 348 goto init_failed; 349 } else { 350 ret = tilcdc_attach_external_device(ddev); 351 if (ret) 352 goto init_failed; 353 } 354 355 if (!priv->external_connector && 356 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { 357 dev_err(dev, "no encoders/connectors found\n"); 358 ret = -EPROBE_DEFER; 359 goto init_failed; 360 } 361 362 ret = drm_vblank_init(ddev, 1); 363 if (ret < 0) { 364 dev_err(dev, "failed to initialize vblank\n"); 365 goto init_failed; 366 } 367 368 ret = platform_get_irq(pdev, 0); 369 if (ret < 0) 370 goto init_failed; 371 priv->irq = ret; 372 373 ret = tilcdc_irq_install(ddev, priv->irq); 374 if (ret < 0) { 375 dev_err(dev, "failed to install IRQ handler\n"); 376 goto init_failed; 377 } 378 379 drm_mode_config_reset(ddev); 380 381 drm_kms_helper_poll_init(ddev); 382 383 ret = drm_dev_register(ddev, 0); 384 if (ret) 385 goto init_failed; 386 priv->is_registered = true; 387 388 drm_fbdev_dma_setup(ddev, bpp); 389 return 0; 390 391 init_failed: 392 tilcdc_fini(ddev); 393 platform_set_drvdata(pdev, NULL); 394 395 return ret; 396 } 397 398 #if defined(CONFIG_DEBUG_FS) 399 static const struct { 400 const char *name; 401 uint8_t rev; 402 uint8_t save; 403 uint32_t reg; 404 } registers[] = { 405 #define REG(rev, save, reg) { #reg, rev, save, reg } 406 /* exists in revision 1: */ 407 REG(1, false, LCDC_PID_REG), 408 REG(1, true, LCDC_CTRL_REG), 409 REG(1, false, LCDC_STAT_REG), 410 REG(1, true, LCDC_RASTER_CTRL_REG), 411 REG(1, true, LCDC_RASTER_TIMING_0_REG), 412 REG(1, true, LCDC_RASTER_TIMING_1_REG), 413 REG(1, true, LCDC_RASTER_TIMING_2_REG), 414 REG(1, true, LCDC_DMA_CTRL_REG), 415 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 416 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 417 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 418 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 419 /* new in revision 2: */ 420 REG(2, false, LCDC_RAW_STAT_REG), 421 REG(2, false, LCDC_MASKED_STAT_REG), 422 REG(2, true, LCDC_INT_ENABLE_SET_REG), 423 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 424 REG(2, false, LCDC_END_OF_INT_IND_REG), 425 REG(2, true, LCDC_CLK_ENABLE_REG), 426 #undef REG 427 }; 428 429 #endif 430 431 #ifdef CONFIG_DEBUG_FS 432 static int tilcdc_regs_show(struct seq_file *m, void *arg) 433 { 434 struct drm_info_node *node = (struct drm_info_node *) m->private; 435 struct drm_device *dev = node->minor->dev; 436 struct tilcdc_drm_private *priv = dev->dev_private; 437 unsigned i; 438 439 pm_runtime_get_sync(dev->dev); 440 441 seq_printf(m, "revision: %d\n", priv->rev); 442 443 for (i = 0; i < ARRAY_SIZE(registers); i++) 444 if (priv->rev >= registers[i].rev) 445 seq_printf(m, "%s:\t %08x\n", registers[i].name, 446 tilcdc_read(dev, registers[i].reg)); 447 448 pm_runtime_put_sync(dev->dev); 449 450 return 0; 451 } 452 453 static int tilcdc_mm_show(struct seq_file *m, void *arg) 454 { 455 struct drm_info_node *node = (struct drm_info_node *) m->private; 456 struct drm_device *dev = node->minor->dev; 457 struct drm_printer p = drm_seq_file_printer(m); 458 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 459 return 0; 460 } 461 462 static struct drm_info_list tilcdc_debugfs_list[] = { 463 { "regs", tilcdc_regs_show, 0, NULL }, 464 { "mm", tilcdc_mm_show, 0, NULL }, 465 }; 466 467 static void tilcdc_debugfs_init(struct drm_minor *minor) 468 { 469 struct tilcdc_module *mod; 470 471 drm_debugfs_create_files(tilcdc_debugfs_list, 472 ARRAY_SIZE(tilcdc_debugfs_list), 473 minor->debugfs_root, minor); 474 475 list_for_each_entry(mod, &module_list, list) 476 if (mod->funcs->debugfs_init) 477 mod->funcs->debugfs_init(mod, minor); 478 } 479 #endif 480 481 DEFINE_DRM_GEM_DMA_FOPS(fops); 482 483 static const struct drm_driver tilcdc_driver = { 484 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 485 DRM_GEM_DMA_DRIVER_OPS, 486 #ifdef CONFIG_DEBUG_FS 487 .debugfs_init = tilcdc_debugfs_init, 488 #endif 489 .fops = &fops, 490 .name = "tilcdc", 491 .desc = "TI LCD Controller DRM", 492 .date = "20121205", 493 .major = 1, 494 .minor = 0, 495 }; 496 497 /* 498 * Power management: 499 */ 500 501 static int tilcdc_pm_suspend(struct device *dev) 502 { 503 struct drm_device *ddev = dev_get_drvdata(dev); 504 int ret = 0; 505 506 ret = drm_mode_config_helper_suspend(ddev); 507 508 /* Select sleep pin state */ 509 pinctrl_pm_select_sleep_state(dev); 510 511 return ret; 512 } 513 514 static int tilcdc_pm_resume(struct device *dev) 515 { 516 struct drm_device *ddev = dev_get_drvdata(dev); 517 518 /* Select default pin state */ 519 pinctrl_pm_select_default_state(dev); 520 return drm_mode_config_helper_resume(ddev); 521 } 522 523 static DEFINE_SIMPLE_DEV_PM_OPS(tilcdc_pm_ops, 524 tilcdc_pm_suspend, tilcdc_pm_resume); 525 526 /* 527 * Platform driver: 528 */ 529 static int tilcdc_bind(struct device *dev) 530 { 531 return tilcdc_init(&tilcdc_driver, dev); 532 } 533 534 static void tilcdc_unbind(struct device *dev) 535 { 536 struct drm_device *ddev = dev_get_drvdata(dev); 537 538 /* Check if a subcomponent has already triggered the unloading. */ 539 if (!ddev->dev_private) 540 return; 541 542 tilcdc_fini(ddev); 543 dev_set_drvdata(dev, NULL); 544 } 545 546 static const struct component_master_ops tilcdc_comp_ops = { 547 .bind = tilcdc_bind, 548 .unbind = tilcdc_unbind, 549 }; 550 551 static int tilcdc_pdev_probe(struct platform_device *pdev) 552 { 553 struct component_match *match = NULL; 554 int ret; 555 556 /* bail out early if no DT data: */ 557 if (!pdev->dev.of_node) { 558 dev_err(&pdev->dev, "device-tree data is missing\n"); 559 return -ENXIO; 560 } 561 562 ret = tilcdc_get_external_components(&pdev->dev, &match); 563 if (ret < 0) 564 return ret; 565 else if (ret == 0) 566 return tilcdc_init(&tilcdc_driver, &pdev->dev); 567 else 568 return component_master_add_with_match(&pdev->dev, 569 &tilcdc_comp_ops, 570 match); 571 } 572 573 static int tilcdc_pdev_remove(struct platform_device *pdev) 574 { 575 int ret; 576 577 ret = tilcdc_get_external_components(&pdev->dev, NULL); 578 if (ret < 0) 579 return ret; 580 else if (ret == 0) 581 tilcdc_fini(platform_get_drvdata(pdev)); 582 else 583 component_master_del(&pdev->dev, &tilcdc_comp_ops); 584 585 return 0; 586 } 587 588 static void tilcdc_pdev_shutdown(struct platform_device *pdev) 589 { 590 drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); 591 } 592 593 static const struct of_device_id tilcdc_of_match[] = { 594 { .compatible = "ti,am33xx-tilcdc", }, 595 { .compatible = "ti,da850-tilcdc", }, 596 { }, 597 }; 598 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 599 600 static struct platform_driver tilcdc_platform_driver = { 601 .probe = tilcdc_pdev_probe, 602 .remove = tilcdc_pdev_remove, 603 .shutdown = tilcdc_pdev_shutdown, 604 .driver = { 605 .name = "tilcdc", 606 .pm = pm_sleep_ptr(&tilcdc_pm_ops), 607 .of_match_table = tilcdc_of_match, 608 }, 609 }; 610 611 static int __init tilcdc_drm_init(void) 612 { 613 if (drm_firmware_drivers_only()) 614 return -ENODEV; 615 616 DBG("init"); 617 tilcdc_panel_init(); 618 return platform_driver_register(&tilcdc_platform_driver); 619 } 620 621 static void __exit tilcdc_drm_fini(void) 622 { 623 DBG("fini"); 624 platform_driver_unregister(&tilcdc_platform_driver); 625 tilcdc_panel_fini(); 626 } 627 628 module_init(tilcdc_drm_init); 629 module_exit(tilcdc_drm_fini); 630 631 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 632 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 633 MODULE_LICENSE("GPL"); 634