1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2013, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/reset.h> 14 15 #include <soc/tegra/common.h> 16 17 #include "drm.h" 18 #include "gem.h" 19 #include "gr2d.h" 20 21 enum { 22 RST_MC, 23 RST_GR2D, 24 RST_GR2D_MAX, 25 }; 26 27 struct gr2d_soc { 28 unsigned int version; 29 }; 30 31 struct gr2d { 32 struct tegra_drm_client client; 33 struct host1x_channel *channel; 34 struct clk *clk; 35 36 struct reset_control_bulk_data resets[RST_GR2D_MAX]; 37 unsigned int nresets; 38 39 const struct gr2d_soc *soc; 40 41 DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS); 42 }; 43 44 static inline struct gr2d *to_gr2d(struct tegra_drm_client *client) 45 { 46 return container_of(client, struct gr2d, client); 47 } 48 49 static int gr2d_init(struct host1x_client *client) 50 { 51 struct tegra_drm_client *drm = host1x_to_drm_client(client); 52 struct drm_device *dev = dev_get_drvdata(client->host); 53 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 54 struct gr2d *gr2d = to_gr2d(drm); 55 int err; 56 57 gr2d->channel = host1x_channel_request(client); 58 if (!gr2d->channel) 59 return -ENOMEM; 60 61 client->syncpts[0] = host1x_syncpt_request(client, flags); 62 if (!client->syncpts[0]) { 63 err = -ENOMEM; 64 dev_err(client->dev, "failed to request syncpoint: %d\n", err); 65 goto put; 66 } 67 68 err = host1x_client_iommu_attach(client); 69 if (err < 0) { 70 dev_err(client->dev, "failed to attach to domain: %d\n", err); 71 goto free; 72 } 73 74 pm_runtime_enable(client->dev); 75 pm_runtime_use_autosuspend(client->dev); 76 pm_runtime_set_autosuspend_delay(client->dev, 200); 77 78 err = tegra_drm_register_client(dev->dev_private, drm); 79 if (err < 0) { 80 dev_err(client->dev, "failed to register client: %d\n", err); 81 goto disable_rpm; 82 } 83 84 return 0; 85 86 disable_rpm: 87 pm_runtime_dont_use_autosuspend(client->dev); 88 pm_runtime_force_suspend(client->dev); 89 90 host1x_client_iommu_detach(client); 91 free: 92 host1x_syncpt_put(client->syncpts[0]); 93 put: 94 host1x_channel_put(gr2d->channel); 95 return err; 96 } 97 98 static int gr2d_exit(struct host1x_client *client) 99 { 100 struct tegra_drm_client *drm = host1x_to_drm_client(client); 101 struct drm_device *dev = dev_get_drvdata(client->host); 102 struct tegra_drm *tegra = dev->dev_private; 103 struct gr2d *gr2d = to_gr2d(drm); 104 int err; 105 106 err = tegra_drm_unregister_client(tegra, drm); 107 if (err < 0) 108 return err; 109 110 pm_runtime_dont_use_autosuspend(client->dev); 111 pm_runtime_force_suspend(client->dev); 112 113 host1x_client_iommu_detach(client); 114 host1x_syncpt_put(client->syncpts[0]); 115 host1x_channel_put(gr2d->channel); 116 117 gr2d->channel = NULL; 118 119 return 0; 120 } 121 122 static const struct host1x_client_ops gr2d_client_ops = { 123 .init = gr2d_init, 124 .exit = gr2d_exit, 125 }; 126 127 static int gr2d_open_channel(struct tegra_drm_client *client, 128 struct tegra_drm_context *context) 129 { 130 struct gr2d *gr2d = to_gr2d(client); 131 132 context->channel = host1x_channel_get(gr2d->channel); 133 if (!context->channel) 134 return -ENOMEM; 135 136 return 0; 137 } 138 139 static void gr2d_close_channel(struct tegra_drm_context *context) 140 { 141 host1x_channel_put(context->channel); 142 } 143 144 static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset) 145 { 146 struct gr2d *gr2d = dev_get_drvdata(dev); 147 148 switch (class) { 149 case HOST1X_CLASS_HOST1X: 150 if (offset == 0x2b) 151 return 1; 152 153 break; 154 155 case HOST1X_CLASS_GR2D: 156 case HOST1X_CLASS_GR2D_SB: 157 if (offset >= GR2D_NUM_REGS) 158 break; 159 160 if (test_bit(offset, gr2d->addr_regs)) 161 return 1; 162 163 break; 164 } 165 166 return 0; 167 } 168 169 static int gr2d_is_valid_class(u32 class) 170 { 171 return (class == HOST1X_CLASS_GR2D || 172 class == HOST1X_CLASS_GR2D_SB); 173 } 174 175 static const struct tegra_drm_client_ops gr2d_ops = { 176 .open_channel = gr2d_open_channel, 177 .close_channel = gr2d_close_channel, 178 .is_addr_reg = gr2d_is_addr_reg, 179 .is_valid_class = gr2d_is_valid_class, 180 .submit = tegra_drm_submit, 181 }; 182 183 static const struct gr2d_soc tegra20_gr2d_soc = { 184 .version = 0x20, 185 }; 186 187 static const struct gr2d_soc tegra30_gr2d_soc = { 188 .version = 0x30, 189 }; 190 191 static const struct gr2d_soc tegra114_gr2d_soc = { 192 .version = 0x35, 193 }; 194 195 static const struct of_device_id gr2d_match[] = { 196 { .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc }, 197 { .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc }, 198 { .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc }, 199 { }, 200 }; 201 MODULE_DEVICE_TABLE(of, gr2d_match); 202 203 static const u32 gr2d_addr_regs[] = { 204 GR2D_UA_BASE_ADDR, 205 GR2D_VA_BASE_ADDR, 206 GR2D_PAT_BASE_ADDR, 207 GR2D_DSTA_BASE_ADDR, 208 GR2D_DSTB_BASE_ADDR, 209 GR2D_DSTC_BASE_ADDR, 210 GR2D_SRCA_BASE_ADDR, 211 GR2D_SRCB_BASE_ADDR, 212 GR2D_PATBASE_ADDR, 213 GR2D_SRC_BASE_ADDR_SB, 214 GR2D_DSTA_BASE_ADDR_SB, 215 GR2D_DSTB_BASE_ADDR_SB, 216 GR2D_UA_BASE_ADDR_SB, 217 GR2D_VA_BASE_ADDR_SB, 218 }; 219 220 static int gr2d_get_resets(struct device *dev, struct gr2d *gr2d) 221 { 222 int err; 223 224 gr2d->resets[RST_MC].id = "mc"; 225 gr2d->resets[RST_GR2D].id = "2d"; 226 gr2d->nresets = RST_GR2D_MAX; 227 228 err = devm_reset_control_bulk_get_optional_exclusive_released( 229 dev, gr2d->nresets, gr2d->resets); 230 if (err) { 231 dev_err(dev, "failed to get reset: %d\n", err); 232 return err; 233 } 234 235 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc)) 236 return -ENOENT; 237 238 return 0; 239 } 240 241 static int gr2d_probe(struct platform_device *pdev) 242 { 243 struct device *dev = &pdev->dev; 244 struct host1x_syncpt **syncpts; 245 struct gr2d *gr2d; 246 unsigned int i; 247 int err; 248 249 gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL); 250 if (!gr2d) 251 return -ENOMEM; 252 253 platform_set_drvdata(pdev, gr2d); 254 255 gr2d->soc = of_device_get_match_data(dev); 256 257 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 258 if (!syncpts) 259 return -ENOMEM; 260 261 gr2d->clk = devm_clk_get(dev, NULL); 262 if (IS_ERR(gr2d->clk)) { 263 dev_err(dev, "cannot get clock\n"); 264 return PTR_ERR(gr2d->clk); 265 } 266 267 err = gr2d_get_resets(dev, gr2d); 268 if (err) 269 return err; 270 271 INIT_LIST_HEAD(&gr2d->client.base.list); 272 gr2d->client.base.ops = &gr2d_client_ops; 273 gr2d->client.base.dev = dev; 274 gr2d->client.base.class = HOST1X_CLASS_GR2D; 275 gr2d->client.base.syncpts = syncpts; 276 gr2d->client.base.num_syncpts = 1; 277 278 INIT_LIST_HEAD(&gr2d->client.list); 279 gr2d->client.version = gr2d->soc->version; 280 gr2d->client.ops = &gr2d_ops; 281 282 err = devm_tegra_core_dev_init_opp_table_common(dev); 283 if (err) 284 return err; 285 286 err = host1x_client_register(&gr2d->client.base); 287 if (err < 0) { 288 dev_err(dev, "failed to register host1x client: %d\n", err); 289 return err; 290 } 291 292 /* initialize address register map */ 293 for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++) 294 set_bit(gr2d_addr_regs[i], gr2d->addr_regs); 295 296 return 0; 297 } 298 299 static void gr2d_remove(struct platform_device *pdev) 300 { 301 struct gr2d *gr2d = platform_get_drvdata(pdev); 302 303 host1x_client_unregister(&gr2d->client.base); 304 } 305 306 static int __maybe_unused gr2d_runtime_suspend(struct device *dev) 307 { 308 struct gr2d *gr2d = dev_get_drvdata(dev); 309 int err; 310 311 host1x_channel_stop(gr2d->channel); 312 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 313 314 /* 315 * GR2D module shouldn't be reset while hardware is idling, otherwise 316 * host1x's cmdproc will stuck on trying to access any G2 register 317 * after reset. GR2D module could be either hot-reset or reset after 318 * power-gating of the HEG partition. Hence we will put in reset only 319 * the memory client part of the module, the HEG GENPD will take care 320 * of resetting GR2D module across power-gating. 321 * 322 * On Tegra20 there is no HEG partition, but it's okay to have 323 * undetermined h/w state since userspace is expected to reprogram 324 * the state on each job submission anyways. 325 */ 326 err = reset_control_acquire(gr2d->resets[RST_MC].rstc); 327 if (err) { 328 dev_err(dev, "failed to acquire MC reset: %d\n", err); 329 goto acquire_reset; 330 } 331 332 err = reset_control_assert(gr2d->resets[RST_MC].rstc); 333 reset_control_release(gr2d->resets[RST_MC].rstc); 334 if (err) { 335 dev_err(dev, "failed to assert MC reset: %d\n", err); 336 goto acquire_reset; 337 } 338 339 clk_disable_unprepare(gr2d->clk); 340 341 return 0; 342 343 acquire_reset: 344 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 345 reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 346 347 return err; 348 } 349 350 static int __maybe_unused gr2d_runtime_resume(struct device *dev) 351 { 352 struct gr2d *gr2d = dev_get_drvdata(dev); 353 int err; 354 355 err = reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 356 if (err) { 357 dev_err(dev, "failed to acquire reset: %d\n", err); 358 return err; 359 } 360 361 err = clk_prepare_enable(gr2d->clk); 362 if (err) { 363 dev_err(dev, "failed to enable clock: %d\n", err); 364 goto release_reset; 365 } 366 367 usleep_range(2000, 4000); 368 369 /* this is a reset array which deasserts both 2D MC and 2D itself */ 370 err = reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 371 if (err) { 372 dev_err(dev, "failed to deassert reset: %d\n", err); 373 goto disable_clk; 374 } 375 376 return 0; 377 378 disable_clk: 379 clk_disable_unprepare(gr2d->clk); 380 release_reset: 381 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 382 383 return err; 384 } 385 386 static const struct dev_pm_ops tegra_gr2d_pm = { 387 SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL) 388 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 389 pm_runtime_force_resume) 390 }; 391 392 struct platform_driver tegra_gr2d_driver = { 393 .driver = { 394 .name = "tegra-gr2d", 395 .of_match_table = gr2d_match, 396 .pm = &tegra_gr2d_pm, 397 }, 398 .probe = gr2d_probe, 399 .remove_new = gr2d_remove, 400 }; 401