1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/seq_file.h> 26 27 #include <drm/drm_pci.h> 28 29 #include "atom.h" 30 #include "r600_dpm.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "rs780_dpm.h" 34 #include "rs780d.h" 35 36 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps) 37 { 38 struct igp_ps *ps = rps->ps_priv; 39 40 return ps; 41 } 42 43 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev) 44 { 45 struct igp_power_info *pi = rdev->pm.dpm.priv; 46 47 return pi; 48 } 49 50 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev) 51 { 52 struct igp_power_info *pi = rs780_get_pi(rdev); 53 struct radeon_mode_info *minfo = &rdev->mode_info; 54 struct drm_crtc *crtc; 55 struct radeon_crtc *radeon_crtc; 56 int i; 57 58 /* defaults */ 59 pi->crtc_id = 0; 60 pi->refresh_rate = 60; 61 62 for (i = 0; i < rdev->num_crtc; i++) { 63 crtc = (struct drm_crtc *)minfo->crtcs[i]; 64 if (crtc && crtc->enabled) { 65 radeon_crtc = to_radeon_crtc(crtc); 66 pi->crtc_id = radeon_crtc->crtc_id; 67 if (crtc->mode.htotal && crtc->mode.vtotal) 68 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode); 69 break; 70 } 71 } 72 } 73 74 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable); 75 76 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev, 77 struct radeon_ps *boot_ps) 78 { 79 struct atom_clock_dividers dividers; 80 struct igp_ps *default_state = rs780_get_ps(boot_ps); 81 int i, ret; 82 83 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 84 default_state->sclk_low, false, ÷rs); 85 if (ret) 86 return ret; 87 88 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); 89 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); 90 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); 91 92 if (dividers.enable_post_div) 93 r600_engine_clock_entry_enable_post_divider(rdev, 0, true); 94 else 95 r600_engine_clock_entry_enable_post_divider(rdev, 0, false); 96 97 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT); 98 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false); 99 100 r600_engine_clock_entry_enable(rdev, 0, true); 101 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++) 102 r600_engine_clock_entry_enable(rdev, i, false); 103 104 r600_enable_mclk_control(rdev, false); 105 r600_voltage_control_enable_pins(rdev, 0); 106 107 return 0; 108 } 109 110 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev, 111 struct radeon_ps *boot_ps) 112 { 113 int ret = 0; 114 int i; 115 116 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT); 117 118 r600_set_at(rdev, 0, 0, 0, 0); 119 120 r600_set_git(rdev, R600_GICST_DFLT); 121 122 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 123 r600_set_tc(rdev, i, 0, 0); 124 125 r600_select_td(rdev, R600_TD_DFLT); 126 r600_set_vrc(rdev, 0); 127 128 r600_set_tpu(rdev, R600_TPU_DFLT); 129 r600_set_tpc(rdev, R600_TPC_DFLT); 130 131 r600_set_sstu(rdev, R600_SSTU_DFLT); 132 r600_set_sst(rdev, R600_SST_DFLT); 133 134 r600_set_fctu(rdev, R600_FCTU_DFLT); 135 r600_set_fct(rdev, R600_FCT_DFLT); 136 137 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); 138 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); 139 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); 140 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); 141 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); 142 143 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); 144 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT); 145 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); 146 147 ret = rs780_initialize_dpm_power_state(rdev, boot_ps); 148 149 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); 150 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 151 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0); 152 153 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 154 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 155 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 156 157 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); 158 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0); 159 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0); 160 161 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH); 162 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH); 163 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH); 164 165 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false); 166 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); 167 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); 168 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); 169 170 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW); 171 172 r600_set_vrc(rdev, RS780_CGFTV_DFLT); 173 174 return ret; 175 } 176 177 static void rs780_start_dpm(struct radeon_device *rdev) 178 { 179 r600_enable_sclk_control(rdev, false); 180 r600_enable_mclk_control(rdev, false); 181 182 r600_dynamicpm_enable(rdev, true); 183 184 radeon_wait_for_vblank(rdev, 0); 185 radeon_wait_for_vblank(rdev, 1); 186 187 r600_enable_spll_bypass(rdev, true); 188 r600_wait_for_spll_change(rdev); 189 r600_enable_spll_bypass(rdev, false); 190 r600_wait_for_spll_change(rdev); 191 192 r600_enable_spll_bypass(rdev, true); 193 r600_wait_for_spll_change(rdev); 194 r600_enable_spll_bypass(rdev, false); 195 r600_wait_for_spll_change(rdev); 196 197 r600_enable_sclk_control(rdev, true); 198 } 199 200 201 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev) 202 { 203 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, 204 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN); 205 206 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, 207 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT), 208 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK); 209 } 210 211 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev) 212 { 213 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 214 215 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), 216 ~STARTING_FEEDBACK_DIV_MASK); 217 218 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), 219 ~FORCED_FEEDBACK_DIV_MASK); 220 221 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 222 } 223 224 static void rs780_voltage_scaling_init(struct radeon_device *rdev) 225 { 226 struct igp_power_info *pi = rs780_get_pi(rdev); 227 struct drm_device *dev = rdev->ddev; 228 u32 fv_throt_pwm_fb_div_range[3]; 229 u32 fv_throt_pwm_range[4]; 230 231 if (dev->pdev->device == 0x9614) { 232 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 233 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 234 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 235 } else if ((dev->pdev->device == 0x9714) || 236 (dev->pdev->device == 0x9715)) { 237 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT; 238 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT; 239 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT; 240 } else { 241 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT; 242 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT; 243 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT; 244 } 245 246 if (pi->pwm_voltage_control) { 247 fv_throt_pwm_range[0] = pi->min_voltage; 248 fv_throt_pwm_range[1] = pi->min_voltage; 249 fv_throt_pwm_range[2] = pi->max_voltage; 250 fv_throt_pwm_range[3] = pi->max_voltage; 251 } else { 252 fv_throt_pwm_range[0] = pi->invert_pwm_required ? 253 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT; 254 fv_throt_pwm_range[1] = pi->invert_pwm_required ? 255 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT; 256 fv_throt_pwm_range[2] = pi->invert_pwm_required ? 257 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT; 258 fv_throt_pwm_range[3] = pi->invert_pwm_required ? 259 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT; 260 } 261 262 WREG32_P(FVTHROT_PWM_CTRL_REG0, 263 STARTING_PWM_HIGHTIME(pi->max_voltage), 264 ~STARTING_PWM_HIGHTIME_MASK); 265 266 WREG32_P(FVTHROT_PWM_CTRL_REG0, 267 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period), 268 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK); 269 270 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, 271 ~FORCE_STARTING_PWM_HIGHTIME); 272 273 if (pi->invert_pwm_required) 274 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); 275 else 276 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); 277 278 rs780_voltage_scaling_enable(rdev, true); 279 280 WREG32(FVTHROT_PWM_CTRL_REG1, 281 (MIN_PWM_HIGHTIME(pi->min_voltage) | 282 MAX_PWM_HIGHTIME(pi->max_voltage))); 283 284 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT); 285 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT); 286 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT); 287 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT); 288 289 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 290 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]), 291 ~RANGE0_PWM_FEEDBACK_DIV_MASK); 292 293 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2, 294 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) | 295 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2]))); 296 297 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3, 298 (RANGE0_PWM(fv_throt_pwm_range[1]) | 299 RANGE1_PWM(fv_throt_pwm_range[2]))); 300 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4, 301 (RANGE2_PWM(fv_throt_pwm_range[1]) | 302 RANGE3_PWM(fv_throt_pwm_range[2]))); 303 } 304 305 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable) 306 { 307 if (enable) 308 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE, 309 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 310 else 311 WREG32_P(FVTHROT_CNTRL_REG, 0, 312 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE)); 313 } 314 315 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable) 316 { 317 if (enable) 318 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO); 319 else 320 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO); 321 } 322 323 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev) 324 { 325 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT); 326 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT); 327 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT); 328 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT); 329 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT); 330 331 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT); 332 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT); 333 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT); 334 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT); 335 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT); 336 } 337 338 static void rs780_set_engine_clock_sc(struct radeon_device *rdev) 339 { 340 WREG32_P(FVTHROT_FBDIV_REG2, 341 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT), 342 ~FB_DIV_TIMER_VAL_MASK); 343 344 WREG32_P(FVTHROT_CNTRL_REG, 345 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf), 346 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK)); 347 } 348 349 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev) 350 { 351 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE)); 352 } 353 354 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev) 355 { 356 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT); 357 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT); 358 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT); 359 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT); 360 361 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK); 362 } 363 364 static void rs780_program_at(struct radeon_device *rdev) 365 { 366 struct igp_power_info *pi = rs780_get_pi(rdev); 367 368 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate); 369 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate); 370 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate); 371 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate); 372 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate); 373 } 374 375 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev) 376 { 377 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000); 378 } 379 380 static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage) 381 { 382 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); 383 384 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 385 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 386 return; 387 388 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 389 390 udelay(1); 391 392 WREG32_P(FVTHROT_PWM_CTRL_REG0, 393 STARTING_PWM_HIGHTIME(voltage), 394 ~STARTING_PWM_HIGHTIME_MASK); 395 396 WREG32_P(FVTHROT_PWM_CTRL_REG0, 397 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME); 398 399 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0, 400 ~RANGE_PWM_FEEDBACK_DIV_EN); 401 402 udelay(1); 403 404 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 405 } 406 407 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) 408 { 409 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); 410 411 if (current_state->sclk_low == current_state->sclk_high) 412 return; 413 414 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 415 416 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), 417 ~FORCED_FEEDBACK_DIV_MASK); 418 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), 419 ~STARTING_FEEDBACK_DIV_MASK); 420 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); 421 422 udelay(100); 423 424 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 425 } 426 427 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev, 428 struct radeon_ps *new_ps, 429 struct radeon_ps *old_ps) 430 { 431 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers; 432 struct igp_ps *new_state = rs780_get_ps(new_ps); 433 struct igp_ps *old_state = rs780_get_ps(old_ps); 434 int ret; 435 436 if ((new_state->sclk_high == old_state->sclk_high) && 437 (new_state->sclk_low == old_state->sclk_low)) 438 return 0; 439 440 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 441 new_state->sclk_low, false, &min_dividers); 442 if (ret) 443 return ret; 444 445 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 446 new_state->sclk_high, false, &max_dividers); 447 if (ret) 448 return ret; 449 450 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 451 old_state->sclk_high, false, ¤t_max_dividers); 452 if (ret) 453 return ret; 454 455 if ((min_dividers.ref_div != max_dividers.ref_div) || 456 (min_dividers.post_div != max_dividers.post_div) || 457 (max_dividers.ref_div != current_max_dividers.ref_div) || 458 (max_dividers.post_div != current_max_dividers.post_div)) 459 return -EINVAL; 460 461 rs780_force_fbdiv(rdev, max_dividers.fb_div); 462 463 if (max_dividers.fb_div > min_dividers.fb_div) { 464 WREG32_P(FVTHROT_FBDIV_REG0, 465 MIN_FEEDBACK_DIV(min_dividers.fb_div) | 466 MAX_FEEDBACK_DIV(max_dividers.fb_div), 467 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK)); 468 469 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); 470 } 471 472 return 0; 473 } 474 475 static void rs780_set_engine_clock_spc(struct radeon_device *rdev, 476 struct radeon_ps *new_ps, 477 struct radeon_ps *old_ps) 478 { 479 struct igp_ps *new_state = rs780_get_ps(new_ps); 480 struct igp_ps *old_state = rs780_get_ps(old_ps); 481 struct igp_power_info *pi = rs780_get_pi(rdev); 482 483 if ((new_state->sclk_high == old_state->sclk_high) && 484 (new_state->sclk_low == old_state->sclk_low)) 485 return; 486 487 if (pi->crtc_id == 0) 488 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL); 489 else 490 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL); 491 492 } 493 494 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev, 495 struct radeon_ps *new_ps, 496 struct radeon_ps *old_ps) 497 { 498 struct igp_ps *new_state = rs780_get_ps(new_ps); 499 struct igp_ps *old_state = rs780_get_ps(old_ps); 500 501 if ((new_state->sclk_high == old_state->sclk_high) && 502 (new_state->sclk_low == old_state->sclk_low)) 503 return; 504 505 if (new_state->sclk_high == new_state->sclk_low) 506 return; 507 508 rs780_clk_scaling_enable(rdev, true); 509 } 510 511 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev, 512 enum rs780_vddc_level vddc) 513 { 514 struct igp_power_info *pi = rs780_get_pi(rdev); 515 516 if (vddc == RS780_VDDC_LEVEL_HIGH) 517 return pi->max_voltage; 518 else if (vddc == RS780_VDDC_LEVEL_LOW) 519 return pi->min_voltage; 520 else 521 return pi->max_voltage; 522 } 523 524 static void rs780_enable_voltage_scaling(struct radeon_device *rdev, 525 struct radeon_ps *new_ps) 526 { 527 struct igp_ps *new_state = rs780_get_ps(new_ps); 528 struct igp_power_info *pi = rs780_get_pi(rdev); 529 enum rs780_vddc_level vddc_high, vddc_low; 530 531 udelay(100); 532 533 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) && 534 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH)) 535 return; 536 537 vddc_high = rs780_get_voltage_for_vddc_level(rdev, 538 new_state->max_voltage); 539 vddc_low = rs780_get_voltage_for_vddc_level(rdev, 540 new_state->min_voltage); 541 542 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL); 543 544 udelay(1); 545 if (vddc_high > vddc_low) { 546 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 547 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN); 548 549 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME); 550 } else if (vddc_high == vddc_low) { 551 if (pi->max_voltage != vddc_high) { 552 WREG32_P(FVTHROT_PWM_CTRL_REG0, 553 STARTING_PWM_HIGHTIME(vddc_high), 554 ~STARTING_PWM_HIGHTIME_MASK); 555 556 WREG32_P(FVTHROT_PWM_CTRL_REG0, 557 FORCE_STARTING_PWM_HIGHTIME, 558 ~FORCE_STARTING_PWM_HIGHTIME); 559 } 560 } 561 562 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL); 563 } 564 565 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, 566 struct radeon_ps *new_ps, 567 struct radeon_ps *old_ps) 568 { 569 struct igp_ps *new_state = rs780_get_ps(new_ps); 570 struct igp_ps *current_state = rs780_get_ps(old_ps); 571 572 if ((new_ps->vclk == old_ps->vclk) && 573 (new_ps->dclk == old_ps->dclk)) 574 return; 575 576 if (new_state->sclk_high >= current_state->sclk_high) 577 return; 578 579 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 580 } 581 582 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, 583 struct radeon_ps *new_ps, 584 struct radeon_ps *old_ps) 585 { 586 struct igp_ps *new_state = rs780_get_ps(new_ps); 587 struct igp_ps *current_state = rs780_get_ps(old_ps); 588 589 if ((new_ps->vclk == old_ps->vclk) && 590 (new_ps->dclk == old_ps->dclk)) 591 return; 592 593 if (new_state->sclk_high < current_state->sclk_high) 594 return; 595 596 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); 597 } 598 599 int rs780_dpm_enable(struct radeon_device *rdev) 600 { 601 struct igp_power_info *pi = rs780_get_pi(rdev); 602 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 603 int ret; 604 605 rs780_get_pm_mode_parameters(rdev); 606 rs780_disable_vbios_powersaving(rdev); 607 608 if (r600_dynamicpm_enabled(rdev)) 609 return -EINVAL; 610 ret = rs780_initialize_dpm_parameters(rdev, boot_ps); 611 if (ret) 612 return ret; 613 rs780_start_dpm(rdev); 614 615 rs780_preset_ranges_slow_clk_fbdiv_en(rdev); 616 rs780_preset_starting_fbdiv(rdev); 617 if (pi->voltage_control) 618 rs780_voltage_scaling_init(rdev); 619 rs780_clk_scaling_enable(rdev, true); 620 rs780_set_engine_clock_sc(rdev); 621 rs780_set_engine_clock_wfc(rdev); 622 rs780_program_at(rdev); 623 rs780_set_engine_clock_tdc(rdev); 624 rs780_set_engine_clock_ssc(rdev); 625 626 if (pi->gfx_clock_gating) 627 r600_gfx_clockgating_enable(rdev, true); 628 629 return 0; 630 } 631 632 void rs780_dpm_disable(struct radeon_device *rdev) 633 { 634 struct igp_power_info *pi = rs780_get_pi(rdev); 635 636 r600_dynamicpm_enable(rdev, false); 637 638 rs780_clk_scaling_enable(rdev, false); 639 rs780_voltage_scaling_enable(rdev, false); 640 641 if (pi->gfx_clock_gating) 642 r600_gfx_clockgating_enable(rdev, false); 643 644 if (rdev->irq.installed && 645 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) { 646 rdev->irq.dpm_thermal = false; 647 radeon_irq_set(rdev); 648 } 649 } 650 651 int rs780_dpm_set_power_state(struct radeon_device *rdev) 652 { 653 struct igp_power_info *pi = rs780_get_pi(rdev); 654 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 655 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; 656 int ret; 657 658 rs780_get_pm_mode_parameters(rdev); 659 660 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 661 662 if (pi->voltage_control) { 663 rs780_force_voltage(rdev, pi->max_voltage); 664 mdelay(5); 665 } 666 667 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps); 668 if (ret) 669 return ret; 670 rs780_set_engine_clock_spc(rdev, new_ps, old_ps); 671 672 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps); 673 674 if (pi->voltage_control) 675 rs780_enable_voltage_scaling(rdev, new_ps); 676 677 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 678 679 return 0; 680 } 681 682 void rs780_dpm_setup_asic(struct radeon_device *rdev) 683 { 684 685 } 686 687 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev) 688 { 689 rs780_get_pm_mode_parameters(rdev); 690 rs780_program_at(rdev); 691 } 692 693 union igp_info { 694 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 695 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 696 }; 697 698 union power_info { 699 struct _ATOM_POWERPLAY_INFO info; 700 struct _ATOM_POWERPLAY_INFO_V2 info_2; 701 struct _ATOM_POWERPLAY_INFO_V3 info_3; 702 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 703 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 704 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 705 }; 706 707 union pplib_clock_info { 708 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 709 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 710 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 711 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 712 }; 713 714 union pplib_power_state { 715 struct _ATOM_PPLIB_STATE v1; 716 struct _ATOM_PPLIB_STATE_V2 v2; 717 }; 718 719 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev, 720 struct radeon_ps *rps, 721 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 722 u8 table_rev) 723 { 724 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 725 rps->class = le16_to_cpu(non_clock_info->usClassification); 726 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 727 728 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 729 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 730 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 731 } else { 732 rps->vclk = 0; 733 rps->dclk = 0; 734 } 735 736 if (r600_is_uvd_state(rps->class, rps->class2)) { 737 if ((rps->vclk == 0) || (rps->dclk == 0)) { 738 rps->vclk = RS780_DEFAULT_VCLK_FREQ; 739 rps->dclk = RS780_DEFAULT_DCLK_FREQ; 740 } 741 } 742 743 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 744 rdev->pm.dpm.boot_ps = rps; 745 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 746 rdev->pm.dpm.uvd_ps = rps; 747 } 748 749 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev, 750 struct radeon_ps *rps, 751 union pplib_clock_info *clock_info) 752 { 753 struct igp_ps *ps = rs780_get_ps(rps); 754 u32 sclk; 755 756 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 757 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 758 ps->sclk_low = sclk; 759 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); 760 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; 761 ps->sclk_high = sclk; 762 switch (le16_to_cpu(clock_info->rs780.usVDDC)) { 763 case ATOM_PPLIB_RS780_VOLTAGE_NONE: 764 default: 765 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN; 766 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN; 767 break; 768 case ATOM_PPLIB_RS780_VOLTAGE_LOW: 769 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 770 ps->max_voltage = RS780_VDDC_LEVEL_LOW; 771 break; 772 case ATOM_PPLIB_RS780_VOLTAGE_HIGH: 773 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 774 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 775 break; 776 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE: 777 ps->min_voltage = RS780_VDDC_LEVEL_LOW; 778 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 779 break; 780 } 781 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags); 782 783 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 784 ps->sclk_low = rdev->clock.default_sclk; 785 ps->sclk_high = rdev->clock.default_sclk; 786 ps->min_voltage = RS780_VDDC_LEVEL_HIGH; 787 ps->max_voltage = RS780_VDDC_LEVEL_HIGH; 788 } 789 } 790 791 static int rs780_parse_power_table(struct radeon_device *rdev) 792 { 793 struct radeon_mode_info *mode_info = &rdev->mode_info; 794 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 795 union pplib_power_state *power_state; 796 int i; 797 union pplib_clock_info *clock_info; 798 union power_info *power_info; 799 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 800 u16 data_offset; 801 u8 frev, crev; 802 struct igp_ps *ps; 803 804 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 805 &frev, &crev, &data_offset)) 806 return -EINVAL; 807 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 808 809 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, 810 sizeof(struct radeon_ps), 811 GFP_KERNEL); 812 if (!rdev->pm.dpm.ps) 813 return -ENOMEM; 814 815 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 816 power_state = (union pplib_power_state *) 817 (mode_info->atom_context->bios + data_offset + 818 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 819 i * power_info->pplib.ucStateEntrySize); 820 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 821 (mode_info->atom_context->bios + data_offset + 822 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 823 (power_state->v1.ucNonClockStateIndex * 824 power_info->pplib.ucNonClockSize)); 825 if (power_info->pplib.ucStateEntrySize - 1) { 826 clock_info = (union pplib_clock_info *) 827 (mode_info->atom_context->bios + data_offset + 828 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 829 (power_state->v1.ucClockStateIndices[0] * 830 power_info->pplib.ucClockInfoSize)); 831 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL); 832 if (ps == NULL) { 833 kfree(rdev->pm.dpm.ps); 834 return -ENOMEM; 835 } 836 rdev->pm.dpm.ps[i].ps_priv = ps; 837 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 838 non_clock_info, 839 power_info->pplib.ucNonClockSize); 840 rs780_parse_pplib_clock_info(rdev, 841 &rdev->pm.dpm.ps[i], 842 clock_info); 843 } 844 } 845 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; 846 return 0; 847 } 848 849 int rs780_dpm_init(struct radeon_device *rdev) 850 { 851 struct igp_power_info *pi; 852 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 853 union igp_info *info; 854 u16 data_offset; 855 u8 frev, crev; 856 int ret; 857 858 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL); 859 if (pi == NULL) 860 return -ENOMEM; 861 rdev->pm.dpm.priv = pi; 862 863 ret = r600_get_platform_caps(rdev); 864 if (ret) 865 return ret; 866 867 ret = rs780_parse_power_table(rdev); 868 if (ret) 869 return ret; 870 871 pi->voltage_control = false; 872 pi->gfx_clock_gating = true; 873 874 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 875 &frev, &crev, &data_offset)) { 876 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 877 878 /* Get various system informations from bios */ 879 switch (crev) { 880 case 1: 881 pi->num_of_cycles_in_period = 882 info->info.ucNumberOfCyclesInPeriod; 883 pi->num_of_cycles_in_period |= 884 info->info.ucNumberOfCyclesInPeriodHi << 8; 885 pi->invert_pwm_required = 886 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 887 pi->boot_voltage = info->info.ucStartingPWM_HighTime; 888 pi->max_voltage = info->info.ucMaxNBVoltage; 889 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8; 890 pi->min_voltage = info->info.ucMinNBVoltage; 891 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8; 892 pi->inter_voltage_low = 893 le16_to_cpu(info->info.usInterNBVoltageLow); 894 pi->inter_voltage_high = 895 le16_to_cpu(info->info.usInterNBVoltageHigh); 896 pi->voltage_control = true; 897 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100; 898 break; 899 case 2: 900 pi->num_of_cycles_in_period = 901 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod); 902 pi->invert_pwm_required = 903 (pi->num_of_cycles_in_period & 0x8000) ? true : false; 904 pi->boot_voltage = 905 le16_to_cpu(info->info_2.usBootUpNBVoltage); 906 pi->max_voltage = 907 le16_to_cpu(info->info_2.usMaxNBVoltage); 908 pi->min_voltage = 909 le16_to_cpu(info->info_2.usMinNBVoltage); 910 pi->system_config = 911 le32_to_cpu(info->info_2.ulSystemConfig); 912 pi->pwm_voltage_control = 913 (pi->system_config & 0x4) ? true : false; 914 pi->voltage_control = true; 915 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock); 916 break; 917 default: 918 DRM_ERROR("No integrated system info for your GPU\n"); 919 return -EINVAL; 920 } 921 if (pi->min_voltage > pi->max_voltage) 922 pi->voltage_control = false; 923 if (pi->pwm_voltage_control) { 924 if ((pi->num_of_cycles_in_period == 0) || 925 (pi->max_voltage == 0) || 926 (pi->min_voltage == 0)) 927 pi->voltage_control = false; 928 } else { 929 if ((pi->num_of_cycles_in_period == 0) || 930 (pi->max_voltage == 0)) 931 pi->voltage_control = false; 932 } 933 934 return 0; 935 } 936 radeon_dpm_fini(rdev); 937 return -EINVAL; 938 } 939 940 void rs780_dpm_print_power_state(struct radeon_device *rdev, 941 struct radeon_ps *rps) 942 { 943 struct igp_ps *ps = rs780_get_ps(rps); 944 945 r600_dpm_print_class_info(rps->class, rps->class2); 946 r600_dpm_print_cap_info(rps->caps); 947 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 948 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n", 949 ps->sclk_low, ps->min_voltage); 950 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n", 951 ps->sclk_high, ps->max_voltage); 952 r600_dpm_print_ps_status(rdev, rps); 953 } 954 955 void rs780_dpm_fini(struct radeon_device *rdev) 956 { 957 int i; 958 959 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 960 kfree(rdev->pm.dpm.ps[i].ps_priv); 961 } 962 kfree(rdev->pm.dpm.ps); 963 kfree(rdev->pm.dpm.priv); 964 } 965 966 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low) 967 { 968 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps); 969 970 if (low) 971 return requested_state->sclk_low; 972 else 973 return requested_state->sclk_high; 974 } 975 976 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low) 977 { 978 struct igp_power_info *pi = rs780_get_pi(rdev); 979 980 return pi->bootup_uma_clk; 981 } 982 983 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 984 struct seq_file *m) 985 { 986 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 987 struct igp_ps *ps = rs780_get_ps(rps); 988 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; 989 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 990 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; 991 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + 992 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; 993 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / 994 (post_div * ref_div); 995 996 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 997 998 /* guess based on the current sclk */ 999 if (sclk < (ps->sclk_low + 500)) 1000 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n", 1001 ps->sclk_low, ps->min_voltage); 1002 else 1003 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n", 1004 ps->sclk_high, ps->max_voltage); 1005 } 1006 1007 /* get the current sclk in 10 khz units */ 1008 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev) 1009 { 1010 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; 1011 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 1012 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; 1013 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + 1014 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; 1015 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / 1016 (post_div * ref_div); 1017 1018 return sclk; 1019 } 1020 1021 /* get the current mclk in 10 khz units */ 1022 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev) 1023 { 1024 struct igp_power_info *pi = rs780_get_pi(rdev); 1025 1026 return pi->bootup_uma_clk; 1027 } 1028 1029 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 1030 enum radeon_dpm_forced_level level) 1031 { 1032 struct igp_power_info *pi = rs780_get_pi(rdev); 1033 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 1034 struct igp_ps *ps = rs780_get_ps(rps); 1035 struct atom_clock_dividers dividers; 1036 int ret; 1037 1038 rs780_clk_scaling_enable(rdev, false); 1039 rs780_voltage_scaling_enable(rdev, false); 1040 1041 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 1042 if (pi->voltage_control) 1043 rs780_force_voltage(rdev, pi->max_voltage); 1044 1045 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1046 ps->sclk_high, false, ÷rs); 1047 if (ret) 1048 return ret; 1049 1050 rs780_force_fbdiv(rdev, dividers.fb_div); 1051 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 1052 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 1053 ps->sclk_low, false, ÷rs); 1054 if (ret) 1055 return ret; 1056 1057 rs780_force_fbdiv(rdev, dividers.fb_div); 1058 1059 if (pi->voltage_control) 1060 rs780_force_voltage(rdev, pi->min_voltage); 1061 } else { 1062 if (pi->voltage_control) 1063 rs780_force_voltage(rdev, pi->max_voltage); 1064 1065 if (ps->sclk_high != ps->sclk_low) { 1066 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV); 1067 rs780_clk_scaling_enable(rdev, true); 1068 } 1069 1070 if (pi->voltage_control) { 1071 rs780_voltage_scaling_enable(rdev, true); 1072 rs780_enable_voltage_scaling(rdev, rps); 1073 } 1074 } 1075 1076 rdev->pm.dpm.forced_level = level; 1077 1078 return 0; 1079 } 1080