1 /* 2 * Copyright 2019 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 #include <subdev/acr.h> 24 25 #include <nvfw/sec2.h> 26 27 static const struct nvkm_falcon_func 28 tu102_sec2_flcn = { 29 .disable = gm200_flcn_disable, 30 .enable = gm200_flcn_enable, 31 .reset_pmc = true, 32 .reset_eng = gp102_flcn_reset_eng, 33 .reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing, 34 .debug = 0x408, 35 .fbif = 0x600, 36 .load_imem = nvkm_falcon_v1_load_imem, 37 .load_dmem = nvkm_falcon_v1_load_dmem, 38 .read_dmem = nvkm_falcon_v1_read_dmem, 39 .emem_addr = 0x01000000, 40 .bind_context = gp102_sec2_flcn_bind_context, 41 .wait_for_halt = nvkm_falcon_v1_wait_for_halt, 42 .clear_interrupt = nvkm_falcon_v1_clear_interrupt, 43 .set_start_addr = nvkm_falcon_v1_set_start_addr, 44 .start = nvkm_falcon_v1_start, 45 .cmdq = { 0xc00, 0xc04, 8 }, 46 .msgq = { 0xc80, 0xc84, 8 }, 47 }; 48 49 static const struct nvkm_sec2_func 50 tu102_sec2 = { 51 .flcn = &tu102_sec2_flcn, 52 .unit_unload = NV_SEC2_UNIT_V2_UNLOAD, 53 .unit_acr = NV_SEC2_UNIT_V2_ACR, 54 .intr = gp102_sec2_intr, 55 .initmsg = gp102_sec2_initmsg, 56 }; 57 58 MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin"); 59 MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin"); 60 MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin"); 61 MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin"); 62 MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin"); 63 MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin"); 64 MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin"); 65 MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin"); 66 MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin"); 67 MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin"); 68 MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin"); 69 MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin"); 70 MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin"); 71 MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin"); 72 MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin"); 73 74 static const struct nvkm_sec2_fwif 75 tu102_sec2_fwif[] = { 76 { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 }, 77 { -1, gp102_sec2_nofw, &tu102_sec2 } 78 }; 79 80 int 81 tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 82 struct nvkm_sec2 **psec2) 83 { 84 /* TOP info wasn't updated on Turing to reflect the PRI 85 * address change for some reason. We override it here. 86 */ 87 return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2); 88 } 89