1 /*
2 * Copyright 2019 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "priv.h"
23 #include <subdev/acr.h>
24
25 #include <nvfw/sec2.h>
26
27 static const struct nvkm_falcon_func
28 tu102_sec2_flcn = {
29 .disable = gm200_flcn_disable,
30 .enable = gm200_flcn_enable,
31 .reset_pmc = true,
32 .reset_eng = gp102_flcn_reset_eng,
33 .reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,
34 .debug = 0x408,
35 .bind_inst = gm200_flcn_bind_inst,
36 .bind_stat = gm200_flcn_bind_stat,
37 .bind_intr = true,
38 .imem_pio = &gm200_flcn_imem_pio,
39 .dmem_pio = &gm200_flcn_dmem_pio,
40 .emem_addr = 0x01000000,
41 .emem_pio = &gp102_flcn_emem_pio,
42 .start = nvkm_falcon_v1_start,
43 .cmdq = { 0xc00, 0xc04, 8 },
44 .msgq = { 0xc80, 0xc84, 8 },
45 };
46
47 static const struct nvkm_sec2_func
48 tu102_sec2 = {
49 .flcn = &tu102_sec2_flcn,
50 .unit_unload = NV_SEC2_UNIT_V2_UNLOAD,
51 .unit_acr = NV_SEC2_UNIT_V2_ACR,
52 .intr = gp102_sec2_intr,
53 .initmsg = gp102_sec2_initmsg,
54 };
55
56 MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin");
57 MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin");
58 MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin");
59 MODULE_FIRMWARE("nvidia/tu104/sec2/desc.bin");
60 MODULE_FIRMWARE("nvidia/tu104/sec2/image.bin");
61 MODULE_FIRMWARE("nvidia/tu104/sec2/sig.bin");
62 MODULE_FIRMWARE("nvidia/tu106/sec2/desc.bin");
63 MODULE_FIRMWARE("nvidia/tu106/sec2/image.bin");
64 MODULE_FIRMWARE("nvidia/tu106/sec2/sig.bin");
65 MODULE_FIRMWARE("nvidia/tu116/sec2/desc.bin");
66 MODULE_FIRMWARE("nvidia/tu116/sec2/image.bin");
67 MODULE_FIRMWARE("nvidia/tu116/sec2/sig.bin");
68 MODULE_FIRMWARE("nvidia/tu117/sec2/desc.bin");
69 MODULE_FIRMWARE("nvidia/tu117/sec2/image.bin");
70 MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin");
71
72 static const struct nvkm_sec2_fwif
73 tu102_sec2_fwif[] = {
74 { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
75 { -1, gp102_sec2_nofw, &tu102_sec2 }
76 };
77
78 int
tu102_sec2_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_sec2 ** psec2)79 tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
80 struct nvkm_sec2 **psec2)
81 {
82 /* TOP info wasn't updated on Turing to reflect the PRI
83 * address change for some reason. We override it here.
84 */
85 return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2);
86 }
87