1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 4 * 5 * This code is based on drivers/video/fbdev/mxsfb.c : 6 * Copyright (C) 2010 Juergen Beisert, Pengutronix 7 * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spinlock.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_encoder.h> 22 #include <drm/drm_fb_cma_helper.h> 23 #include <drm/drm_fourcc.h> 24 #include <drm/drm_gem_cma_helper.h> 25 #include <drm/drm_gem_framebuffer_helper.h> 26 #include <drm/drm_plane.h> 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "mxsfb_drv.h" 31 #include "mxsfb_regs.h" 32 33 /* 1 second delay should be plenty of time for block reset */ 34 #define RESET_TIMEOUT 1000000 35 36 /* ----------------------------------------------------------------------------- 37 * CRTC 38 */ 39 40 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) 41 { 42 return (val & mxsfb->devdata->hs_wdth_mask) << 43 mxsfb->devdata->hs_wdth_shift; 44 } 45 46 /* 47 * Setup the MXSFB registers for decoding the pixels out of the framebuffer and 48 * outputting them on the bus. 49 */ 50 static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb) 51 { 52 struct drm_device *drm = mxsfb->drm; 53 const u32 format = mxsfb->crtc.primary->state->fb->format->format; 54 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 55 u32 ctrl, ctrl1; 56 57 if (mxsfb->connector->display_info.num_bus_formats) 58 bus_format = mxsfb->connector->display_info.bus_formats[0]; 59 60 DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n", 61 bus_format); 62 63 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER; 64 65 /* CTRL1 contains IRQ config and status bits, preserve those. */ 66 ctrl1 = readl(mxsfb->base + LCDC_CTRL1); 67 ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ; 68 69 switch (format) { 70 case DRM_FORMAT_RGB565: 71 dev_dbg(drm->dev, "Setting up RGB565 mode\n"); 72 ctrl |= CTRL_WORD_LENGTH_16; 73 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf); 74 break; 75 case DRM_FORMAT_XRGB8888: 76 dev_dbg(drm->dev, "Setting up XRGB8888 mode\n"); 77 ctrl |= CTRL_WORD_LENGTH_24; 78 /* Do not use packed pixels = one pixel per word instead. */ 79 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7); 80 break; 81 } 82 83 switch (bus_format) { 84 case MEDIA_BUS_FMT_RGB565_1X16: 85 ctrl |= CTRL_BUS_WIDTH_16; 86 break; 87 case MEDIA_BUS_FMT_RGB666_1X18: 88 ctrl |= CTRL_BUS_WIDTH_18; 89 break; 90 case MEDIA_BUS_FMT_RGB888_1X24: 91 ctrl |= CTRL_BUS_WIDTH_24; 92 break; 93 default: 94 dev_err(drm->dev, "Unknown media bus format %d\n", bus_format); 95 break; 96 } 97 98 writel(ctrl1, mxsfb->base + LCDC_CTRL1); 99 writel(ctrl, mxsfb->base + LCDC_CTRL); 100 } 101 102 static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) 103 { 104 u32 reg; 105 106 if (mxsfb->clk_disp_axi) 107 clk_prepare_enable(mxsfb->clk_disp_axi); 108 clk_prepare_enable(mxsfb->clk); 109 110 /* If it was disabled, re-enable the mode again */ 111 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); 112 113 /* Enable the SYNC signals first, then the DMA engine */ 114 reg = readl(mxsfb->base + LCDC_VDCTRL4); 115 reg |= VDCTRL4_SYNC_SIGNALS_ON; 116 writel(reg, mxsfb->base + LCDC_VDCTRL4); 117 118 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); 119 } 120 121 static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) 122 { 123 u32 reg; 124 125 /* 126 * Even if we disable the controller here, it will still continue 127 * until its FIFOs are running out of data 128 */ 129 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); 130 131 readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN), 132 0, 1000); 133 134 reg = readl(mxsfb->base + LCDC_VDCTRL4); 135 reg &= ~VDCTRL4_SYNC_SIGNALS_ON; 136 writel(reg, mxsfb->base + LCDC_VDCTRL4); 137 138 clk_disable_unprepare(mxsfb->clk); 139 if (mxsfb->clk_disp_axi) 140 clk_disable_unprepare(mxsfb->clk_disp_axi); 141 } 142 143 /* 144 * Clear the bit and poll it cleared. This is usually called with 145 * a reset address and mask being either SFTRST(bit 31) or CLKGATE 146 * (bit 30). 147 */ 148 static int clear_poll_bit(void __iomem *addr, u32 mask) 149 { 150 u32 reg; 151 152 writel(mask, addr + REG_CLR); 153 return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT); 154 } 155 156 static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) 157 { 158 int ret; 159 160 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); 161 if (ret) 162 return ret; 163 164 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); 165 166 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); 167 if (ret) 168 return ret; 169 170 return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); 171 } 172 173 static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) 174 { 175 struct drm_framebuffer *fb = plane->state->fb; 176 struct drm_gem_cma_object *gem; 177 178 if (!fb) 179 return 0; 180 181 gem = drm_fb_cma_get_gem_obj(fb, 0); 182 if (!gem) 183 return 0; 184 185 return gem->paddr; 186 } 187 188 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) 189 { 190 struct drm_device *drm = mxsfb->crtc.dev; 191 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; 192 u32 bus_flags = mxsfb->connector->display_info.bus_flags; 193 u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; 194 int err; 195 196 /* 197 * It seems, you can't re-program the controller if it is still 198 * running. This may lead to shifted pictures (FIFO issue?), so 199 * first stop the controller and drain its FIFOs. 200 */ 201 202 /* Mandatory eLCDIF reset as per the Reference Manual */ 203 err = mxsfb_reset_block(mxsfb); 204 if (err) 205 return; 206 207 /* Clear the FIFOs */ 208 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); 209 210 if (mxsfb->devdata->has_overlay) 211 writel(0, mxsfb->base + LCDC_AS_CTRL); 212 213 mxsfb_set_formats(mxsfb); 214 215 clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); 216 217 if (mxsfb->bridge && mxsfb->bridge->timings) 218 bus_flags = mxsfb->bridge->timings->input_bus_flags; 219 220 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", 221 m->crtc_clock, 222 (int)(clk_get_rate(mxsfb->clk) / 1000)); 223 DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n", 224 bus_flags); 225 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); 226 227 writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) | 228 TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay), 229 mxsfb->base + mxsfb->devdata->transfer_count); 230 231 vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start; 232 233 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */ 234 VDCTRL0_VSYNC_PERIOD_UNIT | 235 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | 236 VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len); 237 if (m->flags & DRM_MODE_FLAG_PHSYNC) 238 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; 239 if (m->flags & DRM_MODE_FLAG_PVSYNC) 240 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; 241 /* Make sure Data Enable is high active by default */ 242 if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) 243 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; 244 /* 245 * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric, 246 * controllers VDCTRL0_DOTCLK is display centric. 247 * Drive on positive edge -> display samples on falling edge 248 * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING 249 */ 250 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 251 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; 252 253 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); 254 255 /* Frame length in lines. */ 256 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); 257 258 /* Line length in units of clocks or pixels. */ 259 hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start; 260 writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) | 261 VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal), 262 mxsfb->base + LCDC_VDCTRL2); 263 264 writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) | 265 SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start), 266 mxsfb->base + LCDC_VDCTRL3); 267 268 writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay), 269 mxsfb->base + LCDC_VDCTRL4); 270 } 271 272 static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, 273 struct drm_crtc_state *state) 274 { 275 bool has_primary = state->plane_mask & 276 drm_plane_mask(crtc->primary); 277 278 /* The primary plane has to be enabled when the CRTC is active. */ 279 if (state->active && !has_primary) 280 return -EINVAL; 281 282 /* TODO: Is this needed ? */ 283 return drm_atomic_add_affected_planes(state->state, crtc); 284 } 285 286 static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, 287 struct drm_crtc_state *old_state) 288 { 289 struct drm_pending_vblank_event *event; 290 291 event = crtc->state->event; 292 crtc->state->event = NULL; 293 294 if (!event) 295 return; 296 297 spin_lock_irq(&crtc->dev->event_lock); 298 if (drm_crtc_vblank_get(crtc) == 0) 299 drm_crtc_arm_vblank_event(crtc, event); 300 else 301 drm_crtc_send_vblank_event(crtc, event); 302 spin_unlock_irq(&crtc->dev->event_lock); 303 } 304 305 static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, 306 struct drm_crtc_state *old_state) 307 { 308 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 309 struct drm_device *drm = mxsfb->drm; 310 dma_addr_t paddr; 311 312 pm_runtime_get_sync(drm->dev); 313 mxsfb_enable_axi_clk(mxsfb); 314 315 drm_crtc_vblank_on(crtc); 316 317 mxsfb_crtc_mode_set_nofb(mxsfb); 318 319 /* Write cur_buf as well to avoid an initial corrupt frame */ 320 paddr = mxsfb_get_fb_paddr(crtc->primary); 321 if (paddr) { 322 writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); 323 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); 324 } 325 326 mxsfb_enable_controller(mxsfb); 327 } 328 329 static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, 330 struct drm_crtc_state *old_state) 331 { 332 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 333 struct drm_device *drm = mxsfb->drm; 334 struct drm_pending_vblank_event *event; 335 336 mxsfb_disable_controller(mxsfb); 337 338 spin_lock_irq(&drm->event_lock); 339 event = crtc->state->event; 340 if (event) { 341 crtc->state->event = NULL; 342 drm_crtc_send_vblank_event(crtc, event); 343 } 344 spin_unlock_irq(&drm->event_lock); 345 346 drm_crtc_vblank_off(crtc); 347 348 mxsfb_disable_axi_clk(mxsfb); 349 pm_runtime_put_sync(drm->dev); 350 } 351 352 static int mxsfb_crtc_enable_vblank(struct drm_crtc *crtc) 353 { 354 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 355 356 /* Clear and enable VBLANK IRQ */ 357 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); 358 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); 359 360 return 0; 361 } 362 363 static void mxsfb_crtc_disable_vblank(struct drm_crtc *crtc) 364 { 365 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 366 367 /* Disable and clear VBLANK IRQ */ 368 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); 369 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); 370 } 371 372 static const struct drm_crtc_helper_funcs mxsfb_crtc_helper_funcs = { 373 .atomic_check = mxsfb_crtc_atomic_check, 374 .atomic_flush = mxsfb_crtc_atomic_flush, 375 .atomic_enable = mxsfb_crtc_atomic_enable, 376 .atomic_disable = mxsfb_crtc_atomic_disable, 377 }; 378 379 static const struct drm_crtc_funcs mxsfb_crtc_funcs = { 380 .reset = drm_atomic_helper_crtc_reset, 381 .destroy = drm_crtc_cleanup, 382 .set_config = drm_atomic_helper_set_config, 383 .page_flip = drm_atomic_helper_page_flip, 384 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 385 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 386 .enable_vblank = mxsfb_crtc_enable_vblank, 387 .disable_vblank = mxsfb_crtc_disable_vblank, 388 }; 389 390 /* ----------------------------------------------------------------------------- 391 * Encoder 392 */ 393 394 static const struct drm_encoder_funcs mxsfb_encoder_funcs = { 395 .destroy = drm_encoder_cleanup, 396 }; 397 398 /* ----------------------------------------------------------------------------- 399 * Planes 400 */ 401 402 static int mxsfb_plane_atomic_check(struct drm_plane *plane, 403 struct drm_plane_state *plane_state) 404 { 405 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 406 struct drm_crtc_state *crtc_state; 407 408 crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, 409 &mxsfb->crtc); 410 411 return drm_atomic_helper_check_plane_state(plane_state, crtc_state, 412 DRM_PLANE_HELPER_NO_SCALING, 413 DRM_PLANE_HELPER_NO_SCALING, 414 false, true); 415 } 416 417 static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, 418 struct drm_plane_state *old_pstate) 419 { 420 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 421 dma_addr_t paddr; 422 423 paddr = mxsfb_get_fb_paddr(plane); 424 if (paddr) 425 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); 426 } 427 428 static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, 429 struct drm_plane_state *old_pstate) 430 { 431 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 432 struct drm_plane_state *state = plane->state; 433 dma_addr_t paddr; 434 u32 ctrl; 435 436 paddr = mxsfb_get_fb_paddr(plane); 437 if (!paddr) { 438 writel(0, mxsfb->base + LCDC_AS_CTRL); 439 return; 440 } 441 442 /* 443 * HACK: The hardware seems to output 64 bytes of data of unknown 444 * origin, and then to proceed with the framebuffer. Until the reason 445 * is understood, live with the 16 initial invalid pixels on the first 446 * line and start 64 bytes within the framebuffer. 447 */ 448 paddr += 64; 449 450 writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF); 451 452 /* 453 * If the plane was previously disabled, write LCDC_AS_BUF as well to 454 * provide the first buffer. 455 */ 456 if (!old_pstate->fb) 457 writel(paddr, mxsfb->base + LCDC_AS_BUF); 458 459 ctrl = AS_CTRL_AS_ENABLE | AS_CTRL_ALPHA(255); 460 461 switch (state->fb->format->format) { 462 case DRM_FORMAT_XRGB4444: 463 ctrl |= AS_CTRL_FORMAT_RGB444 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 464 break; 465 case DRM_FORMAT_ARGB4444: 466 ctrl |= AS_CTRL_FORMAT_ARGB4444 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 467 break; 468 case DRM_FORMAT_XRGB1555: 469 ctrl |= AS_CTRL_FORMAT_RGB555 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 470 break; 471 case DRM_FORMAT_ARGB1555: 472 ctrl |= AS_CTRL_FORMAT_ARGB1555 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 473 break; 474 case DRM_FORMAT_RGB565: 475 ctrl |= AS_CTRL_FORMAT_RGB565 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 476 break; 477 case DRM_FORMAT_XRGB8888: 478 ctrl |= AS_CTRL_FORMAT_RGB888 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 479 break; 480 case DRM_FORMAT_ARGB8888: 481 ctrl |= AS_CTRL_FORMAT_ARGB8888 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 482 break; 483 } 484 485 writel(ctrl, mxsfb->base + LCDC_AS_CTRL); 486 } 487 488 static bool mxsfb_format_mod_supported(struct drm_plane *plane, 489 uint32_t format, 490 uint64_t modifier) 491 { 492 return modifier == DRM_FORMAT_MOD_LINEAR; 493 } 494 495 static const struct drm_plane_helper_funcs mxsfb_plane_primary_helper_funcs = { 496 .prepare_fb = drm_gem_fb_prepare_fb, 497 .atomic_check = mxsfb_plane_atomic_check, 498 .atomic_update = mxsfb_plane_primary_atomic_update, 499 }; 500 501 static const struct drm_plane_helper_funcs mxsfb_plane_overlay_helper_funcs = { 502 .prepare_fb = drm_gem_fb_prepare_fb, 503 .atomic_check = mxsfb_plane_atomic_check, 504 .atomic_update = mxsfb_plane_overlay_atomic_update, 505 }; 506 507 static const struct drm_plane_funcs mxsfb_plane_funcs = { 508 .format_mod_supported = mxsfb_format_mod_supported, 509 .update_plane = drm_atomic_helper_update_plane, 510 .disable_plane = drm_atomic_helper_disable_plane, 511 .destroy = drm_plane_cleanup, 512 .reset = drm_atomic_helper_plane_reset, 513 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 514 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 515 }; 516 517 static const uint32_t mxsfb_primary_plane_formats[] = { 518 DRM_FORMAT_RGB565, 519 DRM_FORMAT_XRGB8888, 520 }; 521 522 static const uint32_t mxsfb_overlay_plane_formats[] = { 523 DRM_FORMAT_XRGB4444, 524 DRM_FORMAT_ARGB4444, 525 DRM_FORMAT_XRGB1555, 526 DRM_FORMAT_ARGB1555, 527 DRM_FORMAT_RGB565, 528 DRM_FORMAT_XRGB8888, 529 DRM_FORMAT_ARGB8888, 530 }; 531 532 static const uint64_t mxsfb_modifiers[] = { 533 DRM_FORMAT_MOD_LINEAR, 534 DRM_FORMAT_MOD_INVALID 535 }; 536 537 /* ----------------------------------------------------------------------------- 538 * Initialization 539 */ 540 541 int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb) 542 { 543 struct drm_encoder *encoder = &mxsfb->encoder; 544 struct drm_crtc *crtc = &mxsfb->crtc; 545 int ret; 546 547 drm_plane_helper_add(&mxsfb->planes.primary, 548 &mxsfb_plane_primary_helper_funcs); 549 ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1, 550 &mxsfb_plane_funcs, 551 mxsfb_primary_plane_formats, 552 ARRAY_SIZE(mxsfb_primary_plane_formats), 553 mxsfb_modifiers, DRM_PLANE_TYPE_PRIMARY, 554 NULL); 555 if (ret) 556 return ret; 557 558 if (mxsfb->devdata->has_overlay) { 559 drm_plane_helper_add(&mxsfb->planes.overlay, 560 &mxsfb_plane_overlay_helper_funcs); 561 ret = drm_universal_plane_init(mxsfb->drm, 562 &mxsfb->planes.overlay, 1, 563 &mxsfb_plane_funcs, 564 mxsfb_overlay_plane_formats, 565 ARRAY_SIZE(mxsfb_overlay_plane_formats), 566 mxsfb_modifiers, DRM_PLANE_TYPE_OVERLAY, 567 NULL); 568 if (ret) 569 return ret; 570 } 571 572 drm_crtc_helper_add(crtc, &mxsfb_crtc_helper_funcs); 573 ret = drm_crtc_init_with_planes(mxsfb->drm, crtc, 574 &mxsfb->planes.primary, NULL, 575 &mxsfb_crtc_funcs, NULL); 576 if (ret) 577 return ret; 578 579 encoder->possible_crtcs = drm_crtc_mask(crtc); 580 return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs, 581 DRM_MODE_ENCODER_NONE, NULL); 582 } 583