1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 4 * 5 * This code is based on drivers/video/fbdev/mxsfb.c : 6 * Copyright (C) 2010 Juergen Beisert, Pengutronix 7 * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/spinlock.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_crtc.h> 21 #include <drm/drm_encoder.h> 22 #include <drm/drm_fb_cma_helper.h> 23 #include <drm/drm_fourcc.h> 24 #include <drm/drm_gem_cma_helper.h> 25 #include <drm/drm_plane.h> 26 #include <drm/drm_plane_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "mxsfb_drv.h" 30 #include "mxsfb_regs.h" 31 32 /* 1 second delay should be plenty of time for block reset */ 33 #define RESET_TIMEOUT 1000000 34 35 /* ----------------------------------------------------------------------------- 36 * CRTC 37 */ 38 39 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) 40 { 41 return (val & mxsfb->devdata->hs_wdth_mask) << 42 mxsfb->devdata->hs_wdth_shift; 43 } 44 45 /* 46 * Setup the MXSFB registers for decoding the pixels out of the framebuffer and 47 * outputting them on the bus. 48 */ 49 static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb) 50 { 51 struct drm_device *drm = mxsfb->drm; 52 const u32 format = mxsfb->crtc.primary->state->fb->format->format; 53 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 54 u32 ctrl, ctrl1; 55 56 if (mxsfb->connector->display_info.num_bus_formats) 57 bus_format = mxsfb->connector->display_info.bus_formats[0]; 58 59 DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n", 60 bus_format); 61 62 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER; 63 64 /* CTRL1 contains IRQ config and status bits, preserve those. */ 65 ctrl1 = readl(mxsfb->base + LCDC_CTRL1); 66 ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ; 67 68 switch (format) { 69 case DRM_FORMAT_RGB565: 70 dev_dbg(drm->dev, "Setting up RGB565 mode\n"); 71 ctrl |= CTRL_WORD_LENGTH_16; 72 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf); 73 break; 74 case DRM_FORMAT_XRGB8888: 75 dev_dbg(drm->dev, "Setting up XRGB8888 mode\n"); 76 ctrl |= CTRL_WORD_LENGTH_24; 77 /* Do not use packed pixels = one pixel per word instead. */ 78 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7); 79 break; 80 } 81 82 switch (bus_format) { 83 case MEDIA_BUS_FMT_RGB565_1X16: 84 ctrl |= CTRL_BUS_WIDTH_16; 85 break; 86 case MEDIA_BUS_FMT_RGB666_1X18: 87 ctrl |= CTRL_BUS_WIDTH_18; 88 break; 89 case MEDIA_BUS_FMT_RGB888_1X24: 90 ctrl |= CTRL_BUS_WIDTH_24; 91 break; 92 default: 93 dev_err(drm->dev, "Unknown media bus format %d\n", bus_format); 94 break; 95 } 96 97 writel(ctrl1, mxsfb->base + LCDC_CTRL1); 98 writel(ctrl, mxsfb->base + LCDC_CTRL); 99 } 100 101 static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) 102 { 103 u32 reg; 104 105 if (mxsfb->clk_disp_axi) 106 clk_prepare_enable(mxsfb->clk_disp_axi); 107 clk_prepare_enable(mxsfb->clk); 108 109 /* If it was disabled, re-enable the mode again */ 110 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); 111 112 /* Enable the SYNC signals first, then the DMA engine */ 113 reg = readl(mxsfb->base + LCDC_VDCTRL4); 114 reg |= VDCTRL4_SYNC_SIGNALS_ON; 115 writel(reg, mxsfb->base + LCDC_VDCTRL4); 116 117 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); 118 } 119 120 static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) 121 { 122 u32 reg; 123 124 /* 125 * Even if we disable the controller here, it will still continue 126 * until its FIFOs are running out of data 127 */ 128 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); 129 130 readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN), 131 0, 1000); 132 133 reg = readl(mxsfb->base + LCDC_VDCTRL4); 134 reg &= ~VDCTRL4_SYNC_SIGNALS_ON; 135 writel(reg, mxsfb->base + LCDC_VDCTRL4); 136 137 clk_disable_unprepare(mxsfb->clk); 138 if (mxsfb->clk_disp_axi) 139 clk_disable_unprepare(mxsfb->clk_disp_axi); 140 } 141 142 /* 143 * Clear the bit and poll it cleared. This is usually called with 144 * a reset address and mask being either SFTRST(bit 31) or CLKGATE 145 * (bit 30). 146 */ 147 static int clear_poll_bit(void __iomem *addr, u32 mask) 148 { 149 u32 reg; 150 151 writel(mask, addr + REG_CLR); 152 return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT); 153 } 154 155 static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) 156 { 157 int ret; 158 159 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); 160 if (ret) 161 return ret; 162 163 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); 164 165 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); 166 if (ret) 167 return ret; 168 169 return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); 170 } 171 172 static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) 173 { 174 struct drm_framebuffer *fb = plane->state->fb; 175 struct drm_gem_cma_object *gem; 176 177 if (!fb) 178 return 0; 179 180 gem = drm_fb_cma_get_gem_obj(fb, 0); 181 if (!gem) 182 return 0; 183 184 return gem->paddr; 185 } 186 187 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) 188 { 189 struct drm_device *drm = mxsfb->crtc.dev; 190 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; 191 u32 bus_flags = mxsfb->connector->display_info.bus_flags; 192 u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; 193 int err; 194 195 /* 196 * It seems, you can't re-program the controller if it is still 197 * running. This may lead to shifted pictures (FIFO issue?), so 198 * first stop the controller and drain its FIFOs. 199 */ 200 201 /* Mandatory eLCDIF reset as per the Reference Manual */ 202 err = mxsfb_reset_block(mxsfb); 203 if (err) 204 return; 205 206 /* Clear the FIFOs */ 207 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); 208 209 if (mxsfb->devdata->has_overlay) 210 writel(0, mxsfb->base + LCDC_AS_CTRL); 211 212 mxsfb_set_formats(mxsfb); 213 214 clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); 215 216 if (mxsfb->bridge && mxsfb->bridge->timings) 217 bus_flags = mxsfb->bridge->timings->input_bus_flags; 218 219 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", 220 m->crtc_clock, 221 (int)(clk_get_rate(mxsfb->clk) / 1000)); 222 DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n", 223 bus_flags); 224 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); 225 226 writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) | 227 TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay), 228 mxsfb->base + mxsfb->devdata->transfer_count); 229 230 vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start; 231 232 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */ 233 VDCTRL0_VSYNC_PERIOD_UNIT | 234 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | 235 VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len); 236 if (m->flags & DRM_MODE_FLAG_PHSYNC) 237 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; 238 if (m->flags & DRM_MODE_FLAG_PVSYNC) 239 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; 240 /* Make sure Data Enable is high active by default */ 241 if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) 242 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; 243 /* 244 * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric, 245 * controllers VDCTRL0_DOTCLK is display centric. 246 * Drive on positive edge -> display samples on falling edge 247 * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING 248 */ 249 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 250 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; 251 252 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); 253 254 /* Frame length in lines. */ 255 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); 256 257 /* Line length in units of clocks or pixels. */ 258 hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start; 259 writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) | 260 VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal), 261 mxsfb->base + LCDC_VDCTRL2); 262 263 writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) | 264 SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start), 265 mxsfb->base + LCDC_VDCTRL3); 266 267 writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay), 268 mxsfb->base + LCDC_VDCTRL4); 269 } 270 271 static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, 272 struct drm_crtc_state *state) 273 { 274 bool has_primary = state->plane_mask & 275 drm_plane_mask(crtc->primary); 276 277 /* The primary plane has to be enabled when the CRTC is active. */ 278 if (state->active && !has_primary) 279 return -EINVAL; 280 281 /* TODO: Is this needed ? */ 282 return drm_atomic_add_affected_planes(state->state, crtc); 283 } 284 285 static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, 286 struct drm_crtc_state *old_state) 287 { 288 struct drm_pending_vblank_event *event; 289 290 event = crtc->state->event; 291 crtc->state->event = NULL; 292 293 if (!event) 294 return; 295 296 spin_lock_irq(&crtc->dev->event_lock); 297 if (drm_crtc_vblank_get(crtc) == 0) 298 drm_crtc_arm_vblank_event(crtc, event); 299 else 300 drm_crtc_send_vblank_event(crtc, event); 301 spin_unlock_irq(&crtc->dev->event_lock); 302 } 303 304 static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, 305 struct drm_crtc_state *old_state) 306 { 307 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 308 struct drm_device *drm = mxsfb->drm; 309 dma_addr_t paddr; 310 311 pm_runtime_get_sync(drm->dev); 312 mxsfb_enable_axi_clk(mxsfb); 313 314 drm_crtc_vblank_on(crtc); 315 316 mxsfb_crtc_mode_set_nofb(mxsfb); 317 318 /* Write cur_buf as well to avoid an initial corrupt frame */ 319 paddr = mxsfb_get_fb_paddr(crtc->primary); 320 if (paddr) { 321 writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); 322 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); 323 } 324 325 mxsfb_enable_controller(mxsfb); 326 } 327 328 static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, 329 struct drm_crtc_state *old_state) 330 { 331 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 332 struct drm_device *drm = mxsfb->drm; 333 struct drm_pending_vblank_event *event; 334 335 mxsfb_disable_controller(mxsfb); 336 337 spin_lock_irq(&drm->event_lock); 338 event = crtc->state->event; 339 if (event) { 340 crtc->state->event = NULL; 341 drm_crtc_send_vblank_event(crtc, event); 342 } 343 spin_unlock_irq(&drm->event_lock); 344 345 drm_crtc_vblank_off(crtc); 346 347 mxsfb_disable_axi_clk(mxsfb); 348 pm_runtime_put_sync(drm->dev); 349 } 350 351 static int mxsfb_crtc_enable_vblank(struct drm_crtc *crtc) 352 { 353 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 354 355 /* Clear and enable VBLANK IRQ */ 356 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); 357 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); 358 359 return 0; 360 } 361 362 static void mxsfb_crtc_disable_vblank(struct drm_crtc *crtc) 363 { 364 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); 365 366 /* Disable and clear VBLANK IRQ */ 367 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); 368 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); 369 } 370 371 static const struct drm_crtc_helper_funcs mxsfb_crtc_helper_funcs = { 372 .atomic_check = mxsfb_crtc_atomic_check, 373 .atomic_flush = mxsfb_crtc_atomic_flush, 374 .atomic_enable = mxsfb_crtc_atomic_enable, 375 .atomic_disable = mxsfb_crtc_atomic_disable, 376 }; 377 378 static const struct drm_crtc_funcs mxsfb_crtc_funcs = { 379 .reset = drm_atomic_helper_crtc_reset, 380 .destroy = drm_crtc_cleanup, 381 .set_config = drm_atomic_helper_set_config, 382 .page_flip = drm_atomic_helper_page_flip, 383 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 384 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 385 .enable_vblank = mxsfb_crtc_enable_vblank, 386 .disable_vblank = mxsfb_crtc_disable_vblank, 387 }; 388 389 /* ----------------------------------------------------------------------------- 390 * Encoder 391 */ 392 393 static const struct drm_encoder_funcs mxsfb_encoder_funcs = { 394 .destroy = drm_encoder_cleanup, 395 }; 396 397 /* ----------------------------------------------------------------------------- 398 * Planes 399 */ 400 401 static int mxsfb_plane_atomic_check(struct drm_plane *plane, 402 struct drm_plane_state *plane_state) 403 { 404 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 405 struct drm_crtc_state *crtc_state; 406 407 crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, 408 &mxsfb->crtc); 409 410 return drm_atomic_helper_check_plane_state(plane_state, crtc_state, 411 DRM_PLANE_HELPER_NO_SCALING, 412 DRM_PLANE_HELPER_NO_SCALING, 413 false, true); 414 } 415 416 static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, 417 struct drm_plane_state *old_pstate) 418 { 419 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 420 dma_addr_t paddr; 421 422 paddr = mxsfb_get_fb_paddr(plane); 423 if (paddr) 424 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); 425 } 426 427 static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, 428 struct drm_plane_state *old_pstate) 429 { 430 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); 431 struct drm_plane_state *state = plane->state; 432 dma_addr_t paddr; 433 u32 ctrl; 434 435 paddr = mxsfb_get_fb_paddr(plane); 436 if (!paddr) { 437 writel(0, mxsfb->base + LCDC_AS_CTRL); 438 return; 439 } 440 441 /* 442 * HACK: The hardware seems to output 64 bytes of data of unknown 443 * origin, and then to proceed with the framebuffer. Until the reason 444 * is understood, live with the 16 initial invalid pixels on the first 445 * line and start 64 bytes within the framebuffer. 446 */ 447 paddr += 64; 448 449 writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF); 450 451 /* 452 * If the plane was previously disabled, write LCDC_AS_BUF as well to 453 * provide the first buffer. 454 */ 455 if (!old_pstate->fb) 456 writel(paddr, mxsfb->base + LCDC_AS_BUF); 457 458 ctrl = AS_CTRL_AS_ENABLE | AS_CTRL_ALPHA(255); 459 460 switch (state->fb->format->format) { 461 case DRM_FORMAT_XRGB4444: 462 ctrl |= AS_CTRL_FORMAT_RGB444 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 463 break; 464 case DRM_FORMAT_ARGB4444: 465 ctrl |= AS_CTRL_FORMAT_ARGB4444 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 466 break; 467 case DRM_FORMAT_XRGB1555: 468 ctrl |= AS_CTRL_FORMAT_RGB555 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 469 break; 470 case DRM_FORMAT_ARGB1555: 471 ctrl |= AS_CTRL_FORMAT_ARGB1555 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 472 break; 473 case DRM_FORMAT_RGB565: 474 ctrl |= AS_CTRL_FORMAT_RGB565 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 475 break; 476 case DRM_FORMAT_XRGB8888: 477 ctrl |= AS_CTRL_FORMAT_RGB888 | AS_CTRL_ALPHA_CTRL_OVERRIDE; 478 break; 479 case DRM_FORMAT_ARGB8888: 480 ctrl |= AS_CTRL_FORMAT_ARGB8888 | AS_CTRL_ALPHA_CTRL_EMBEDDED; 481 break; 482 } 483 484 writel(ctrl, mxsfb->base + LCDC_AS_CTRL); 485 } 486 487 static const struct drm_plane_helper_funcs mxsfb_plane_primary_helper_funcs = { 488 .atomic_check = mxsfb_plane_atomic_check, 489 .atomic_update = mxsfb_plane_primary_atomic_update, 490 }; 491 492 static const struct drm_plane_helper_funcs mxsfb_plane_overlay_helper_funcs = { 493 .atomic_check = mxsfb_plane_atomic_check, 494 .atomic_update = mxsfb_plane_overlay_atomic_update, 495 }; 496 497 static const struct drm_plane_funcs mxsfb_plane_funcs = { 498 .update_plane = drm_atomic_helper_update_plane, 499 .disable_plane = drm_atomic_helper_disable_plane, 500 .destroy = drm_plane_cleanup, 501 .reset = drm_atomic_helper_plane_reset, 502 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 503 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 504 }; 505 506 static const uint32_t mxsfb_primary_plane_formats[] = { 507 DRM_FORMAT_RGB565, 508 DRM_FORMAT_XRGB8888, 509 }; 510 511 static const uint32_t mxsfb_overlay_plane_formats[] = { 512 DRM_FORMAT_XRGB4444, 513 DRM_FORMAT_ARGB4444, 514 DRM_FORMAT_XRGB1555, 515 DRM_FORMAT_ARGB1555, 516 DRM_FORMAT_RGB565, 517 DRM_FORMAT_XRGB8888, 518 DRM_FORMAT_ARGB8888, 519 }; 520 521 static const uint64_t mxsfb_modifiers[] = { 522 DRM_FORMAT_MOD_LINEAR, 523 DRM_FORMAT_MOD_INVALID 524 }; 525 526 /* ----------------------------------------------------------------------------- 527 * Initialization 528 */ 529 530 int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb) 531 { 532 struct drm_encoder *encoder = &mxsfb->encoder; 533 struct drm_crtc *crtc = &mxsfb->crtc; 534 int ret; 535 536 drm_plane_helper_add(&mxsfb->planes.primary, 537 &mxsfb_plane_primary_helper_funcs); 538 ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1, 539 &mxsfb_plane_funcs, 540 mxsfb_primary_plane_formats, 541 ARRAY_SIZE(mxsfb_primary_plane_formats), 542 mxsfb_modifiers, DRM_PLANE_TYPE_PRIMARY, 543 NULL); 544 if (ret) 545 return ret; 546 547 if (mxsfb->devdata->has_overlay) { 548 drm_plane_helper_add(&mxsfb->planes.overlay, 549 &mxsfb_plane_overlay_helper_funcs); 550 ret = drm_universal_plane_init(mxsfb->drm, 551 &mxsfb->planes.overlay, 1, 552 &mxsfb_plane_funcs, 553 mxsfb_overlay_plane_formats, 554 ARRAY_SIZE(mxsfb_overlay_plane_formats), 555 mxsfb_modifiers, DRM_PLANE_TYPE_OVERLAY, 556 NULL); 557 if (ret) 558 return ret; 559 } 560 561 drm_crtc_helper_add(crtc, &mxsfb_crtc_helper_funcs); 562 ret = drm_crtc_init_with_planes(mxsfb->drm, crtc, 563 &mxsfb->planes.primary, NULL, 564 &mxsfb_crtc_funcs, NULL); 565 if (ret) 566 return ret; 567 568 encoder->possible_crtcs = drm_crtc_mask(crtc); 569 return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs, 570 DRM_MODE_ENCODER_NONE, NULL); 571 } 572