1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 #include <linux/debugfs.h> 10 #include <linux/kthread.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_probe_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_hwio.h" 20 #include "dpu_hw_catalog.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_ctl.h" 23 #include "dpu_hw_dspp.h" 24 #include "dpu_formats.h" 25 #include "dpu_encoder_phys.h" 26 #include "dpu_crtc.h" 27 #include "dpu_trace.h" 28 #include "dpu_core_irq.h" 29 #include "disp/msm_disp_snapshot.h" 30 31 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ 32 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 33 34 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 35 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 36 37 #define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\ 38 (p) ? (p)->parent->base.id : -1, \ 39 (p) ? (p)->intf_idx - INTF_0 : -1, \ 40 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 41 ##__VA_ARGS__) 42 43 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 44 (p) ? (p)->parent->base.id : -1, \ 45 (p) ? (p)->intf_idx - INTF_0 : -1, \ 46 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 47 ##__VA_ARGS__) 48 49 /* 50 * Two to anticipate panels that can do cmd/vid dynamic switching 51 * plan is to create all possible physical encoder types, and switch between 52 * them at runtime 53 */ 54 #define NUM_PHYS_ENCODER_TYPES 2 55 56 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 57 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 58 59 #define MAX_CHANNELS_PER_ENC 2 60 61 #define IDLE_SHORT_TIMEOUT 1 62 63 #define MAX_HDISPLAY_SPLIT 1080 64 65 /* timeout in frames waiting for frame done */ 66 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 67 68 /** 69 * enum dpu_enc_rc_events - events for resource control state machine 70 * @DPU_ENC_RC_EVENT_KICKOFF: 71 * This event happens at NORMAL priority. 72 * Event that signals the start of the transfer. When this event is 73 * received, enable MDP/DSI core clocks. Regardless of the previous 74 * state, the resource should be in ON state at the end of this event. 75 * @DPU_ENC_RC_EVENT_FRAME_DONE: 76 * This event happens at INTERRUPT level. 77 * Event signals the end of the data transfer after the PP FRAME_DONE 78 * event. At the end of this event, a delayed work is scheduled to go to 79 * IDLE_PC state after IDLE_TIMEOUT time. 80 * @DPU_ENC_RC_EVENT_PRE_STOP: 81 * This event happens at NORMAL priority. 82 * This event, when received during the ON state, leave the RC STATE 83 * in the PRE_OFF state. It should be followed by the STOP event as 84 * part of encoder disable. 85 * If received during IDLE or OFF states, it will do nothing. 86 * @DPU_ENC_RC_EVENT_STOP: 87 * This event happens at NORMAL priority. 88 * When this event is received, disable all the MDP/DSI core clocks, and 89 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 90 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 91 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 92 * Resource state should be in OFF at the end of the event. 93 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 94 * This event happens at NORMAL priority from a work item. 95 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 96 * This would disable MDP/DSI core clocks and change the resource state 97 * to IDLE. 98 */ 99 enum dpu_enc_rc_events { 100 DPU_ENC_RC_EVENT_KICKOFF = 1, 101 DPU_ENC_RC_EVENT_FRAME_DONE, 102 DPU_ENC_RC_EVENT_PRE_STOP, 103 DPU_ENC_RC_EVENT_STOP, 104 DPU_ENC_RC_EVENT_ENTER_IDLE 105 }; 106 107 /* 108 * enum dpu_enc_rc_states - states that the resource control maintains 109 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 110 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 111 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 112 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 113 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 114 */ 115 enum dpu_enc_rc_states { 116 DPU_ENC_RC_STATE_OFF, 117 DPU_ENC_RC_STATE_PRE_OFF, 118 DPU_ENC_RC_STATE_ON, 119 DPU_ENC_RC_STATE_IDLE 120 }; 121 122 /** 123 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 124 * encoders. Virtual encoder manages one "logical" display. Physical 125 * encoders manage one intf block, tied to a specific panel/sub-panel. 126 * Virtual encoder defers as much as possible to the physical encoders. 127 * Virtual encoder registers itself with the DRM Framework as the encoder. 128 * @base: drm_encoder base class for registration with DRM 129 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 130 * @enabled: True if the encoder is active, protected by enc_lock 131 * @num_phys_encs: Actual number of physical encoders contained. 132 * @phys_encs: Container of physical encoders managed. 133 * @cur_master: Pointer to the current master in this mode. Optimization 134 * Only valid after enable. Cleared as disable. 135 * @cur_slave: As above but for the slave encoder. 136 * @hw_pp: Handle to the pingpong blocks used for the display. No. 137 * pingpong blocks can be different than num_phys_encs. 138 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped 139 * for partial update right-only cases, such as pingpong 140 * split where virtual pingpong does not generate IRQs 141 * @crtc: Pointer to the currently assigned crtc. Normally you 142 * would use crtc->state->encoder_mask to determine the 143 * link between encoder/crtc. However in this case we need 144 * to track crtc in the disable() hook which is called 145 * _after_ encoder_mask is cleared. 146 * @connector: If a mode is set, cached pointer to the active connector 147 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 148 * all CTL paths 149 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 150 * @debugfs_root: Debug file system root file node 151 * @enc_lock: Lock around physical encoder 152 * create/destroy/enable/disable 153 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 154 * busy processing current command. 155 * Bit0 = phys_encs[0] etc. 156 * @crtc_frame_event_cb: callback handler for frame event 157 * @crtc_frame_event_cb_data: callback handler private data 158 * @frame_done_timeout_ms: frame done timeout in ms 159 * @frame_done_timer: watchdog timer for frame done event 160 * @vsync_event_timer: vsync timer 161 * @disp_info: local copy of msm_display_info struct 162 * @idle_pc_supported: indicate if idle power collaps is supported 163 * @rc_lock: resource control mutex lock to protect 164 * virt encoder over various state changes 165 * @rc_state: resource controller state 166 * @delayed_off_work: delayed worker to schedule disabling of 167 * clks and resources after IDLE_TIMEOUT time. 168 * @vsync_event_work: worker to handle vsync event for autorefresh 169 * @topology: topology of the display 170 * @idle_timeout: idle timeout duration in milliseconds 171 */ 172 struct dpu_encoder_virt { 173 struct drm_encoder base; 174 spinlock_t enc_spinlock; 175 176 bool enabled; 177 178 unsigned int num_phys_encs; 179 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 180 struct dpu_encoder_phys *cur_master; 181 struct dpu_encoder_phys *cur_slave; 182 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 183 184 bool intfs_swapped; 185 186 struct drm_crtc *crtc; 187 struct drm_connector *connector; 188 189 struct dentry *debugfs_root; 190 struct mutex enc_lock; 191 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 192 void (*crtc_frame_event_cb)(void *, u32 event); 193 void *crtc_frame_event_cb_data; 194 195 atomic_t frame_done_timeout_ms; 196 struct timer_list frame_done_timer; 197 struct timer_list vsync_event_timer; 198 199 struct msm_display_info disp_info; 200 201 bool idle_pc_supported; 202 struct mutex rc_lock; 203 enum dpu_enc_rc_states rc_state; 204 struct delayed_work delayed_off_work; 205 struct kthread_work vsync_event_work; 206 struct msm_display_topology topology; 207 208 u32 idle_timeout; 209 }; 210 211 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 212 213 static u32 dither_matrix[DITHER_MATRIX_SZ] = { 214 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 215 }; 216 217 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) 218 { 219 struct dpu_hw_dither_cfg dither_cfg = { 0 }; 220 221 if (!hw_pp->ops.setup_dither) 222 return; 223 224 switch (bpc) { 225 case 6: 226 dither_cfg.c0_bitdepth = 6; 227 dither_cfg.c1_bitdepth = 6; 228 dither_cfg.c2_bitdepth = 6; 229 dither_cfg.c3_bitdepth = 6; 230 dither_cfg.temporal_en = 0; 231 break; 232 default: 233 hw_pp->ops.setup_dither(hw_pp, NULL); 234 return; 235 } 236 237 memcpy(&dither_cfg.matrix, dither_matrix, 238 sizeof(u32) * DITHER_MATRIX_SZ); 239 240 hw_pp->ops.setup_dither(hw_pp, &dither_cfg); 241 } 242 243 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 244 enum dpu_intr_idx intr_idx) 245 { 246 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 247 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 248 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 249 250 if (phys_enc->parent_ops->handle_frame_done) 251 phys_enc->parent_ops->handle_frame_done( 252 phys_enc->parent, phys_enc, 253 DPU_ENCODER_FRAME_EVENT_ERROR); 254 } 255 256 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 257 u32 irq_idx, struct dpu_encoder_wait_info *info); 258 259 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 260 enum dpu_intr_idx intr_idx, 261 struct dpu_encoder_wait_info *wait_info) 262 { 263 struct dpu_encoder_irq *irq; 264 u32 irq_status; 265 int ret; 266 267 if (!wait_info || intr_idx >= INTR_IDX_MAX) { 268 DPU_ERROR("invalid params\n"); 269 return -EINVAL; 270 } 271 irq = &phys_enc->irq[intr_idx]; 272 273 /* note: do master / slave checking outside */ 274 275 /* return EWOULDBLOCK since we know the wait isn't necessary */ 276 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 277 DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d\n", 278 DRMID(phys_enc->parent), intr_idx, 279 irq->irq_idx); 280 return -EWOULDBLOCK; 281 } 282 283 if (irq->irq_idx < 0) { 284 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s\n", 285 DRMID(phys_enc->parent), intr_idx, 286 irq->name); 287 return 0; 288 } 289 290 DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d\n", 291 DRMID(phys_enc->parent), intr_idx, 292 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 293 atomic_read(wait_info->atomic_cnt)); 294 295 ret = dpu_encoder_helper_wait_event_timeout( 296 DRMID(phys_enc->parent), 297 irq->irq_idx, 298 wait_info); 299 300 if (ret <= 0) { 301 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 302 irq->irq_idx, true); 303 if (irq_status) { 304 unsigned long flags; 305 306 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d\n", 307 DRMID(phys_enc->parent), intr_idx, 308 irq->irq_idx, 309 phys_enc->hw_pp->idx - PINGPONG_0, 310 atomic_read(wait_info->atomic_cnt)); 311 local_irq_save(flags); 312 irq->cb.func(phys_enc, irq->irq_idx); 313 local_irq_restore(flags); 314 ret = 0; 315 } else { 316 ret = -ETIMEDOUT; 317 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d\n", 318 DRMID(phys_enc->parent), intr_idx, 319 irq->irq_idx, 320 phys_enc->hw_pp->idx - PINGPONG_0, 321 atomic_read(wait_info->atomic_cnt)); 322 } 323 } else { 324 ret = 0; 325 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 326 intr_idx, irq->irq_idx, 327 phys_enc->hw_pp->idx - PINGPONG_0, 328 atomic_read(wait_info->atomic_cnt)); 329 } 330 331 return ret; 332 } 333 334 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 335 enum dpu_intr_idx intr_idx) 336 { 337 struct dpu_encoder_irq *irq; 338 int ret = 0; 339 340 if (intr_idx >= INTR_IDX_MAX) { 341 DPU_ERROR("invalid params\n"); 342 return -EINVAL; 343 } 344 irq = &phys_enc->irq[intr_idx]; 345 346 if (irq->irq_idx < 0) { 347 DPU_ERROR_PHYS(phys_enc, 348 "invalid IRQ index:%d\n", irq->irq_idx); 349 return -EINVAL; 350 } 351 352 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 353 &irq->cb); 354 if (ret) { 355 DPU_ERROR_PHYS(phys_enc, 356 "failed to register IRQ callback for %s\n", 357 irq->name); 358 irq->irq_idx = -EINVAL; 359 return ret; 360 } 361 362 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 363 irq->irq_idx); 364 365 return ret; 366 } 367 368 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 369 enum dpu_intr_idx intr_idx) 370 { 371 struct dpu_encoder_irq *irq; 372 int ret; 373 374 irq = &phys_enc->irq[intr_idx]; 375 376 /* silently skip irqs that weren't registered */ 377 if (irq->irq_idx < 0) { 378 DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d", 379 DRMID(phys_enc->parent), intr_idx, 380 irq->irq_idx); 381 return 0; 382 } 383 384 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 385 &irq->cb); 386 if (ret) { 387 DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d", 388 DRMID(phys_enc->parent), intr_idx, 389 irq->irq_idx, ret); 390 } 391 392 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 393 irq->irq_idx); 394 395 return 0; 396 } 397 398 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 399 { 400 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 401 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL; 402 return phys ? atomic_read(&phys->vsync_cnt) : 0; 403 } 404 405 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 406 { 407 struct dpu_encoder_virt *dpu_enc; 408 struct dpu_encoder_phys *phys; 409 int linecount = 0; 410 411 dpu_enc = to_dpu_encoder_virt(drm_enc); 412 phys = dpu_enc ? dpu_enc->cur_master : NULL; 413 414 if (phys && phys->ops.get_line_count) 415 linecount = phys->ops.get_line_count(phys); 416 417 return linecount; 418 } 419 420 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 421 { 422 struct dpu_encoder_virt *dpu_enc = NULL; 423 int i = 0; 424 425 if (!drm_enc) { 426 DPU_ERROR("invalid encoder\n"); 427 return; 428 } 429 430 dpu_enc = to_dpu_encoder_virt(drm_enc); 431 DPU_DEBUG_ENC(dpu_enc, "\n"); 432 433 mutex_lock(&dpu_enc->enc_lock); 434 435 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 436 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 437 438 if (phys->ops.destroy) { 439 phys->ops.destroy(phys); 440 --dpu_enc->num_phys_encs; 441 dpu_enc->phys_encs[i] = NULL; 442 } 443 } 444 445 if (dpu_enc->num_phys_encs) 446 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 447 dpu_enc->num_phys_encs); 448 dpu_enc->num_phys_encs = 0; 449 mutex_unlock(&dpu_enc->enc_lock); 450 451 drm_encoder_cleanup(drm_enc); 452 mutex_destroy(&dpu_enc->enc_lock); 453 } 454 455 void dpu_encoder_helper_split_config( 456 struct dpu_encoder_phys *phys_enc, 457 enum dpu_intf interface) 458 { 459 struct dpu_encoder_virt *dpu_enc; 460 struct split_pipe_cfg cfg = { 0 }; 461 struct dpu_hw_mdp *hw_mdptop; 462 struct msm_display_info *disp_info; 463 464 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 465 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 466 return; 467 } 468 469 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 470 hw_mdptop = phys_enc->hw_mdptop; 471 disp_info = &dpu_enc->disp_info; 472 473 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 474 return; 475 476 /** 477 * disable split modes since encoder will be operating in as the only 478 * encoder, either for the entire use case in the case of, for example, 479 * single DSI, or for this frame in the case of left/right only partial 480 * update. 481 */ 482 if (phys_enc->split_role == ENC_ROLE_SOLO) { 483 if (hw_mdptop->ops.setup_split_pipe) 484 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 485 return; 486 } 487 488 cfg.en = true; 489 cfg.mode = phys_enc->intf_mode; 490 cfg.intf = interface; 491 492 if (cfg.en && phys_enc->ops.needs_single_flush && 493 phys_enc->ops.needs_single_flush(phys_enc)) 494 cfg.split_flush_en = true; 495 496 if (phys_enc->split_role == ENC_ROLE_MASTER) { 497 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 498 499 if (hw_mdptop->ops.setup_split_pipe) 500 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 501 } 502 } 503 504 static struct msm_display_topology dpu_encoder_get_topology( 505 struct dpu_encoder_virt *dpu_enc, 506 struct dpu_kms *dpu_kms, 507 struct drm_display_mode *mode) 508 { 509 struct msm_display_topology topology = {0}; 510 int i, intf_count = 0; 511 512 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 513 if (dpu_enc->phys_encs[i]) 514 intf_count++; 515 516 /* Datapath topology selection 517 * 518 * Dual display 519 * 2 LM, 2 INTF ( Split display using 2 interfaces) 520 * 521 * Single display 522 * 1 LM, 1 INTF 523 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 524 * 525 * Adding color blocks only to primary interface if available in 526 * sufficient number 527 */ 528 if (intf_count == 2) 529 topology.num_lm = 2; 530 else if (!dpu_kms->catalog->caps->has_3d_merge) 531 topology.num_lm = 1; 532 else 533 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 534 535 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { 536 if (dpu_kms->catalog->dspp && 537 (dpu_kms->catalog->dspp_count >= topology.num_lm)) 538 topology.num_dspp = topology.num_lm; 539 } 540 541 topology.num_enc = 0; 542 topology.num_intf = intf_count; 543 544 return topology; 545 } 546 static int dpu_encoder_virt_atomic_check( 547 struct drm_encoder *drm_enc, 548 struct drm_crtc_state *crtc_state, 549 struct drm_connector_state *conn_state) 550 { 551 struct dpu_encoder_virt *dpu_enc; 552 struct msm_drm_private *priv; 553 struct dpu_kms *dpu_kms; 554 const struct drm_display_mode *mode; 555 struct drm_display_mode *adj_mode; 556 struct msm_display_topology topology; 557 struct dpu_global_state *global_state; 558 int i = 0; 559 int ret = 0; 560 561 if (!drm_enc || !crtc_state || !conn_state) { 562 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 563 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 564 return -EINVAL; 565 } 566 567 dpu_enc = to_dpu_encoder_virt(drm_enc); 568 DPU_DEBUG_ENC(dpu_enc, "\n"); 569 570 priv = drm_enc->dev->dev_private; 571 dpu_kms = to_dpu_kms(priv->kms); 572 mode = &crtc_state->mode; 573 adj_mode = &crtc_state->adjusted_mode; 574 global_state = dpu_kms_get_global_state(crtc_state->state); 575 if (IS_ERR(global_state)) 576 return PTR_ERR(global_state); 577 578 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 579 580 /* perform atomic check on the first physical encoder (master) */ 581 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 582 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 583 584 if (phys->ops.atomic_check) 585 ret = phys->ops.atomic_check(phys, crtc_state, 586 conn_state); 587 if (ret) { 588 DPU_ERROR_ENC(dpu_enc, 589 "mode unsupported, phys idx %d\n", i); 590 break; 591 } 592 } 593 594 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 595 596 /* Reserve dynamic resources now. */ 597 if (!ret) { 598 /* 599 * Release and Allocate resources on every modeset 600 * Dont allocate when active is false. 601 */ 602 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 603 dpu_rm_release(global_state, drm_enc); 604 605 if (!crtc_state->active_changed || crtc_state->active) 606 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 607 drm_enc, crtc_state, topology); 608 } 609 } 610 611 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 612 613 return ret; 614 } 615 616 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 617 struct msm_display_info *disp_info) 618 { 619 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 620 struct msm_drm_private *priv; 621 struct dpu_kms *dpu_kms; 622 struct dpu_hw_mdp *hw_mdptop; 623 struct drm_encoder *drm_enc; 624 int i; 625 626 if (!dpu_enc || !disp_info) { 627 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 628 dpu_enc != NULL, disp_info != NULL); 629 return; 630 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 631 DPU_ERROR("invalid num phys enc %d/%d\n", 632 dpu_enc->num_phys_encs, 633 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 634 return; 635 } 636 637 drm_enc = &dpu_enc->base; 638 /* this pointers are checked in virt_enable_helper */ 639 priv = drm_enc->dev->dev_private; 640 641 dpu_kms = to_dpu_kms(priv->kms); 642 hw_mdptop = dpu_kms->hw_mdp; 643 if (!hw_mdptop) { 644 DPU_ERROR("invalid mdptop\n"); 645 return; 646 } 647 648 if (hw_mdptop->ops.setup_vsync_source && 649 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 650 for (i = 0; i < dpu_enc->num_phys_encs; i++) 651 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 652 653 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 654 if (disp_info->is_te_using_watchdog_timer) 655 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 656 else 657 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 658 659 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 660 } 661 } 662 663 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 664 { 665 struct dpu_encoder_virt *dpu_enc; 666 int i; 667 668 if (!drm_enc) { 669 DPU_ERROR("invalid encoder\n"); 670 return; 671 } 672 673 dpu_enc = to_dpu_encoder_virt(drm_enc); 674 675 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 676 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 677 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 678 679 if (phys->ops.irq_control) 680 phys->ops.irq_control(phys, enable); 681 } 682 683 } 684 685 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 686 bool enable) 687 { 688 struct msm_drm_private *priv; 689 struct dpu_kms *dpu_kms; 690 struct dpu_encoder_virt *dpu_enc; 691 692 dpu_enc = to_dpu_encoder_virt(drm_enc); 693 priv = drm_enc->dev->dev_private; 694 dpu_kms = to_dpu_kms(priv->kms); 695 696 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 697 698 if (!dpu_enc->cur_master) { 699 DPU_ERROR("encoder master not set\n"); 700 return; 701 } 702 703 if (enable) { 704 /* enable DPU core clks */ 705 pm_runtime_get_sync(&dpu_kms->pdev->dev); 706 707 /* enable all the irq */ 708 _dpu_encoder_irq_control(drm_enc, true); 709 710 } else { 711 /* disable all the irq */ 712 _dpu_encoder_irq_control(drm_enc, false); 713 714 /* disable DPU core clks */ 715 pm_runtime_put_sync(&dpu_kms->pdev->dev); 716 } 717 718 } 719 720 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 721 u32 sw_event) 722 { 723 struct dpu_encoder_virt *dpu_enc; 724 struct msm_drm_private *priv; 725 bool is_vid_mode = false; 726 727 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 728 DPU_ERROR("invalid parameters\n"); 729 return -EINVAL; 730 } 731 dpu_enc = to_dpu_encoder_virt(drm_enc); 732 priv = drm_enc->dev->dev_private; 733 is_vid_mode = dpu_enc->disp_info.capabilities & 734 MSM_DISPLAY_CAP_VID_MODE; 735 736 /* 737 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 738 * events and return early for other events (ie wb display). 739 */ 740 if (!dpu_enc->idle_pc_supported && 741 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 742 sw_event != DPU_ENC_RC_EVENT_STOP && 743 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 744 return 0; 745 746 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 747 dpu_enc->rc_state, "begin"); 748 749 switch (sw_event) { 750 case DPU_ENC_RC_EVENT_KICKOFF: 751 /* cancel delayed off work, if any */ 752 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 753 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 754 sw_event); 755 756 mutex_lock(&dpu_enc->rc_lock); 757 758 /* return if the resource control is already in ON state */ 759 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 760 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", 761 DRMID(drm_enc), sw_event); 762 mutex_unlock(&dpu_enc->rc_lock); 763 return 0; 764 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 765 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 766 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", 767 DRMID(drm_enc), sw_event, 768 dpu_enc->rc_state); 769 mutex_unlock(&dpu_enc->rc_lock); 770 return -EINVAL; 771 } 772 773 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 774 _dpu_encoder_irq_control(drm_enc, true); 775 else 776 _dpu_encoder_resource_control_helper(drm_enc, true); 777 778 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 779 780 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 781 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 782 "kickoff"); 783 784 mutex_unlock(&dpu_enc->rc_lock); 785 break; 786 787 case DPU_ENC_RC_EVENT_FRAME_DONE: 788 /* 789 * mutex lock is not used as this event happens at interrupt 790 * context. And locking is not required as, the other events 791 * like KICKOFF and STOP does a wait-for-idle before executing 792 * the resource_control 793 */ 794 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 795 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 796 DRMID(drm_enc), sw_event, 797 dpu_enc->rc_state); 798 return -EINVAL; 799 } 800 801 /* 802 * schedule off work item only when there are no 803 * frames pending 804 */ 805 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 806 DRM_DEBUG_KMS("id:%d skip schedule work\n", 807 DRMID(drm_enc)); 808 return 0; 809 } 810 811 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 812 msecs_to_jiffies(dpu_enc->idle_timeout)); 813 814 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 815 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 816 "frame done"); 817 break; 818 819 case DPU_ENC_RC_EVENT_PRE_STOP: 820 /* cancel delayed off work, if any */ 821 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 822 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 823 sw_event); 824 825 mutex_lock(&dpu_enc->rc_lock); 826 827 if (is_vid_mode && 828 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 829 _dpu_encoder_irq_control(drm_enc, true); 830 } 831 /* skip if is already OFF or IDLE, resources are off already */ 832 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 833 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 834 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 835 DRMID(drm_enc), sw_event, 836 dpu_enc->rc_state); 837 mutex_unlock(&dpu_enc->rc_lock); 838 return 0; 839 } 840 841 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 842 843 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 844 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 845 "pre stop"); 846 847 mutex_unlock(&dpu_enc->rc_lock); 848 break; 849 850 case DPU_ENC_RC_EVENT_STOP: 851 mutex_lock(&dpu_enc->rc_lock); 852 853 /* return if the resource control is already in OFF state */ 854 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 855 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 856 DRMID(drm_enc), sw_event); 857 mutex_unlock(&dpu_enc->rc_lock); 858 return 0; 859 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 860 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 861 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 862 mutex_unlock(&dpu_enc->rc_lock); 863 return -EINVAL; 864 } 865 866 /** 867 * expect to arrive here only if in either idle state or pre-off 868 * and in IDLE state the resources are already disabled 869 */ 870 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 871 _dpu_encoder_resource_control_helper(drm_enc, false); 872 873 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 874 875 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 876 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 877 "stop"); 878 879 mutex_unlock(&dpu_enc->rc_lock); 880 break; 881 882 case DPU_ENC_RC_EVENT_ENTER_IDLE: 883 mutex_lock(&dpu_enc->rc_lock); 884 885 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 886 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 887 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 888 mutex_unlock(&dpu_enc->rc_lock); 889 return 0; 890 } 891 892 /* 893 * if we are in ON but a frame was just kicked off, 894 * ignore the IDLE event, it's probably a stale timer event 895 */ 896 if (dpu_enc->frame_busy_mask[0]) { 897 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 898 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 899 mutex_unlock(&dpu_enc->rc_lock); 900 return 0; 901 } 902 903 if (is_vid_mode) 904 _dpu_encoder_irq_control(drm_enc, false); 905 else 906 _dpu_encoder_resource_control_helper(drm_enc, false); 907 908 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 909 910 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 911 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 912 "idle"); 913 914 mutex_unlock(&dpu_enc->rc_lock); 915 break; 916 917 default: 918 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 919 sw_event); 920 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 921 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 922 "error"); 923 break; 924 } 925 926 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 927 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 928 "end"); 929 return 0; 930 } 931 932 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, 933 struct drm_crtc_state *crtc_state, 934 struct drm_connector_state *conn_state) 935 { 936 struct dpu_encoder_virt *dpu_enc; 937 struct msm_drm_private *priv; 938 struct dpu_kms *dpu_kms; 939 struct dpu_crtc_state *cstate; 940 struct dpu_global_state *global_state; 941 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 942 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 943 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 944 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 945 int num_lm, num_ctl, num_pp; 946 int i; 947 948 if (!drm_enc) { 949 DPU_ERROR("invalid encoder\n"); 950 return; 951 } 952 953 dpu_enc = to_dpu_encoder_virt(drm_enc); 954 DPU_DEBUG_ENC(dpu_enc, "\n"); 955 956 priv = drm_enc->dev->dev_private; 957 dpu_kms = to_dpu_kms(priv->kms); 958 959 global_state = dpu_kms_get_existing_global_state(dpu_kms); 960 if (IS_ERR_OR_NULL(global_state)) { 961 DPU_ERROR("Failed to get global state"); 962 return; 963 } 964 965 trace_dpu_enc_mode_set(DRMID(drm_enc)); 966 967 /* Query resource that have been reserved in atomic check step. */ 968 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 969 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 970 ARRAY_SIZE(hw_pp)); 971 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 972 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 973 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 974 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 975 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 976 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 977 ARRAY_SIZE(hw_dspp)); 978 979 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 980 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 981 : NULL; 982 983 cstate = to_dpu_crtc_state(crtc_state); 984 985 for (i = 0; i < num_lm; i++) { 986 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 987 988 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 989 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 990 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 991 } 992 993 cstate->num_mixers = num_lm; 994 995 dpu_enc->connector = conn_state->connector; 996 997 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 998 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 999 1000 if (!dpu_enc->hw_pp[i]) { 1001 DPU_ERROR_ENC(dpu_enc, 1002 "no pp block assigned at idx: %d\n", i); 1003 return; 1004 } 1005 1006 if (!hw_ctl[i]) { 1007 DPU_ERROR_ENC(dpu_enc, 1008 "no ctl block assigned at idx: %d\n", i); 1009 return; 1010 } 1011 1012 phys->hw_pp = dpu_enc->hw_pp[i]; 1013 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1014 1015 if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) 1016 phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx); 1017 1018 if (!phys->hw_intf) { 1019 DPU_ERROR_ENC(dpu_enc, 1020 "no intf block assigned at idx: %d\n", i); 1021 return; 1022 } 1023 1024 phys->cached_mode = crtc_state->adjusted_mode; 1025 if (phys->ops.atomic_mode_set) 1026 phys->ops.atomic_mode_set(phys, crtc_state, conn_state); 1027 } 1028 } 1029 1030 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1031 { 1032 struct dpu_encoder_virt *dpu_enc = NULL; 1033 int i; 1034 1035 if (!drm_enc || !drm_enc->dev) { 1036 DPU_ERROR("invalid parameters\n"); 1037 return; 1038 } 1039 1040 dpu_enc = to_dpu_encoder_virt(drm_enc); 1041 if (!dpu_enc || !dpu_enc->cur_master) { 1042 DPU_ERROR("invalid dpu encoder/master\n"); 1043 return; 1044 } 1045 1046 1047 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS && 1048 dpu_enc->cur_master->hw_mdptop && 1049 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) 1050 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( 1051 dpu_enc->cur_master->hw_mdptop); 1052 1053 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1054 1055 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1056 !WARN_ON(dpu_enc->num_phys_encs == 0)) { 1057 unsigned bpc = dpu_enc->connector->display_info.bpc; 1058 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1059 if (!dpu_enc->hw_pp[i]) 1060 continue; 1061 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc); 1062 } 1063 } 1064 } 1065 1066 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1067 { 1068 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1069 1070 mutex_lock(&dpu_enc->enc_lock); 1071 1072 if (!dpu_enc->enabled) 1073 goto out; 1074 1075 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1076 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1077 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1078 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1079 1080 _dpu_encoder_virt_enable_helper(drm_enc); 1081 1082 out: 1083 mutex_unlock(&dpu_enc->enc_lock); 1084 } 1085 1086 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1087 { 1088 struct dpu_encoder_virt *dpu_enc = NULL; 1089 int ret = 0; 1090 struct drm_display_mode *cur_mode = NULL; 1091 1092 dpu_enc = to_dpu_encoder_virt(drm_enc); 1093 1094 mutex_lock(&dpu_enc->enc_lock); 1095 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1096 1097 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1098 cur_mode->vdisplay); 1099 1100 /* always enable slave encoder before master */ 1101 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1102 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1103 1104 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1105 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1106 1107 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1108 if (ret) { 1109 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1110 ret); 1111 goto out; 1112 } 1113 1114 _dpu_encoder_virt_enable_helper(drm_enc); 1115 1116 dpu_enc->enabled = true; 1117 1118 out: 1119 mutex_unlock(&dpu_enc->enc_lock); 1120 } 1121 1122 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1123 { 1124 struct dpu_encoder_virt *dpu_enc = NULL; 1125 int i = 0; 1126 1127 dpu_enc = to_dpu_encoder_virt(drm_enc); 1128 DPU_DEBUG_ENC(dpu_enc, "\n"); 1129 1130 mutex_lock(&dpu_enc->enc_lock); 1131 dpu_enc->enabled = false; 1132 1133 trace_dpu_enc_disable(DRMID(drm_enc)); 1134 1135 /* wait for idle */ 1136 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1137 1138 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1139 1140 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1141 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1142 1143 if (phys->ops.disable) 1144 phys->ops.disable(phys); 1145 } 1146 1147 1148 /* after phys waits for frame-done, should be no more frames pending */ 1149 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1150 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1151 del_timer_sync(&dpu_enc->frame_done_timer); 1152 } 1153 1154 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1155 1156 dpu_enc->connector = NULL; 1157 1158 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1159 1160 mutex_unlock(&dpu_enc->enc_lock); 1161 } 1162 1163 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1164 enum dpu_intf_type type, u32 controller_id) 1165 { 1166 int i = 0; 1167 1168 for (i = 0; i < catalog->intf_count; i++) { 1169 if (catalog->intf[i].type == type 1170 && catalog->intf[i].controller_id == controller_id) { 1171 return catalog->intf[i].id; 1172 } 1173 } 1174 1175 return INTF_MAX; 1176 } 1177 1178 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1179 struct dpu_encoder_phys *phy_enc) 1180 { 1181 struct dpu_encoder_virt *dpu_enc = NULL; 1182 unsigned long lock_flags; 1183 1184 if (!drm_enc || !phy_enc) 1185 return; 1186 1187 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1188 dpu_enc = to_dpu_encoder_virt(drm_enc); 1189 1190 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1191 if (dpu_enc->crtc) 1192 dpu_crtc_vblank_callback(dpu_enc->crtc); 1193 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1194 1195 atomic_inc(&phy_enc->vsync_cnt); 1196 DPU_ATRACE_END("encoder_vblank_callback"); 1197 } 1198 1199 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1200 struct dpu_encoder_phys *phy_enc) 1201 { 1202 if (!phy_enc) 1203 return; 1204 1205 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1206 atomic_inc(&phy_enc->underrun_cnt); 1207 1208 /* trigger dump only on the first underrun */ 1209 if (atomic_read(&phy_enc->underrun_cnt) == 1) 1210 msm_disp_snapshot_state(drm_enc->dev); 1211 1212 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1213 atomic_read(&phy_enc->underrun_cnt)); 1214 DPU_ATRACE_END("encoder_underrun_callback"); 1215 } 1216 1217 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1218 { 1219 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1220 unsigned long lock_flags; 1221 1222 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1223 /* crtc should always be cleared before re-assigning */ 1224 WARN_ON(crtc && dpu_enc->crtc); 1225 dpu_enc->crtc = crtc; 1226 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1227 } 1228 1229 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1230 struct drm_crtc *crtc, bool enable) 1231 { 1232 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1233 unsigned long lock_flags; 1234 int i; 1235 1236 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1237 1238 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1239 if (dpu_enc->crtc != crtc) { 1240 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1241 return; 1242 } 1243 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1244 1245 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1246 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1247 1248 if (phys->ops.control_vblank_irq) 1249 phys->ops.control_vblank_irq(phys, enable); 1250 } 1251 } 1252 1253 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1254 void (*frame_event_cb)(void *, u32 event), 1255 void *frame_event_cb_data) 1256 { 1257 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1258 unsigned long lock_flags; 1259 bool enable; 1260 1261 enable = frame_event_cb ? true : false; 1262 1263 if (!drm_enc) { 1264 DPU_ERROR("invalid encoder\n"); 1265 return; 1266 } 1267 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1268 1269 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1270 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1271 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1272 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1273 } 1274 1275 static void dpu_encoder_frame_done_callback( 1276 struct drm_encoder *drm_enc, 1277 struct dpu_encoder_phys *ready_phys, u32 event) 1278 { 1279 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1280 unsigned int i; 1281 1282 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1283 | DPU_ENCODER_FRAME_EVENT_ERROR 1284 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1285 1286 if (!dpu_enc->frame_busy_mask[0]) { 1287 /** 1288 * suppress frame_done without waiter, 1289 * likely autorefresh 1290 */ 1291 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1292 event, ready_phys->intf_idx); 1293 return; 1294 } 1295 1296 /* One of the physical encoders has become idle */ 1297 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1298 if (dpu_enc->phys_encs[i] == ready_phys) { 1299 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1300 dpu_enc->frame_busy_mask[0]); 1301 clear_bit(i, dpu_enc->frame_busy_mask); 1302 } 1303 } 1304 1305 if (!dpu_enc->frame_busy_mask[0]) { 1306 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1307 del_timer(&dpu_enc->frame_done_timer); 1308 1309 dpu_encoder_resource_control(drm_enc, 1310 DPU_ENC_RC_EVENT_FRAME_DONE); 1311 1312 if (dpu_enc->crtc_frame_event_cb) 1313 dpu_enc->crtc_frame_event_cb( 1314 dpu_enc->crtc_frame_event_cb_data, 1315 event); 1316 } 1317 } else { 1318 if (dpu_enc->crtc_frame_event_cb) 1319 dpu_enc->crtc_frame_event_cb( 1320 dpu_enc->crtc_frame_event_cb_data, event); 1321 } 1322 } 1323 1324 static void dpu_encoder_off_work(struct work_struct *work) 1325 { 1326 struct dpu_encoder_virt *dpu_enc = container_of(work, 1327 struct dpu_encoder_virt, delayed_off_work.work); 1328 1329 dpu_encoder_resource_control(&dpu_enc->base, 1330 DPU_ENC_RC_EVENT_ENTER_IDLE); 1331 1332 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1333 DPU_ENCODER_FRAME_EVENT_IDLE); 1334 } 1335 1336 /** 1337 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1338 * @drm_enc: Pointer to drm encoder structure 1339 * @phys: Pointer to physical encoder structure 1340 * @extra_flush_bits: Additional bit mask to include in flush trigger 1341 */ 1342 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1343 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1344 { 1345 struct dpu_hw_ctl *ctl; 1346 int pending_kickoff_cnt; 1347 u32 ret = UINT_MAX; 1348 1349 if (!phys->hw_pp) { 1350 DPU_ERROR("invalid pingpong hw\n"); 1351 return; 1352 } 1353 1354 ctl = phys->hw_ctl; 1355 if (!ctl->ops.trigger_flush) { 1356 DPU_ERROR("missing trigger cb\n"); 1357 return; 1358 } 1359 1360 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1361 1362 if (extra_flush_bits && ctl->ops.update_pending_flush) 1363 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1364 1365 ctl->ops.trigger_flush(ctl); 1366 1367 if (ctl->ops.get_pending_flush) 1368 ret = ctl->ops.get_pending_flush(ctl); 1369 1370 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1371 pending_kickoff_cnt, ctl->idx, 1372 extra_flush_bits, ret); 1373 } 1374 1375 /** 1376 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1377 * @phys: Pointer to physical encoder structure 1378 */ 1379 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1380 { 1381 if (!phys) { 1382 DPU_ERROR("invalid argument(s)\n"); 1383 return; 1384 } 1385 1386 if (!phys->hw_pp) { 1387 DPU_ERROR("invalid pingpong hw\n"); 1388 return; 1389 } 1390 1391 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1392 phys->ops.trigger_start(phys); 1393 } 1394 1395 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1396 { 1397 struct dpu_hw_ctl *ctl; 1398 1399 ctl = phys_enc->hw_ctl; 1400 if (ctl->ops.trigger_start) { 1401 ctl->ops.trigger_start(ctl); 1402 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1403 } 1404 } 1405 1406 static int dpu_encoder_helper_wait_event_timeout( 1407 int32_t drm_id, 1408 u32 irq_idx, 1409 struct dpu_encoder_wait_info *info) 1410 { 1411 int rc = 0; 1412 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1413 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1414 s64 time; 1415 1416 do { 1417 rc = wait_event_timeout(*(info->wq), 1418 atomic_read(info->atomic_cnt) == 0, jiffies); 1419 time = ktime_to_ms(ktime_get()); 1420 1421 trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time, 1422 expected_time, 1423 atomic_read(info->atomic_cnt)); 1424 /* If we timed out, counter is valid and time is less, wait again */ 1425 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1426 (time < expected_time)); 1427 1428 return rc; 1429 } 1430 1431 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1432 { 1433 struct dpu_encoder_virt *dpu_enc; 1434 struct dpu_hw_ctl *ctl; 1435 int rc; 1436 struct drm_encoder *drm_enc; 1437 1438 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1439 ctl = phys_enc->hw_ctl; 1440 drm_enc = phys_enc->parent; 1441 1442 if (!ctl->ops.reset) 1443 return; 1444 1445 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), 1446 ctl->idx); 1447 1448 rc = ctl->ops.reset(ctl); 1449 if (rc) { 1450 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1451 msm_disp_snapshot_state(drm_enc->dev); 1452 } 1453 1454 phys_enc->enable_state = DPU_ENC_ENABLED; 1455 } 1456 1457 /** 1458 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1459 * Iterate through the physical encoders and perform consolidated flush 1460 * and/or control start triggering as needed. This is done in the virtual 1461 * encoder rather than the individual physical ones in order to handle 1462 * use cases that require visibility into multiple physical encoders at 1463 * a time. 1464 * @dpu_enc: Pointer to virtual encoder structure 1465 */ 1466 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1467 { 1468 struct dpu_hw_ctl *ctl; 1469 uint32_t i, pending_flush; 1470 unsigned long lock_flags; 1471 1472 pending_flush = 0x0; 1473 1474 /* update pending counts and trigger kickoff ctl flush atomically */ 1475 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1476 1477 /* don't perform flush/start operations for slave encoders */ 1478 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1479 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1480 1481 if (phys->enable_state == DPU_ENC_DISABLED) 1482 continue; 1483 1484 ctl = phys->hw_ctl; 1485 1486 /* 1487 * This is cleared in frame_done worker, which isn't invoked 1488 * for async commits. So don't set this for async, since it'll 1489 * roll over to the next commit. 1490 */ 1491 if (phys->split_role != ENC_ROLE_SLAVE) 1492 set_bit(i, dpu_enc->frame_busy_mask); 1493 1494 if (!phys->ops.needs_single_flush || 1495 !phys->ops.needs_single_flush(phys)) 1496 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1497 else if (ctl->ops.get_pending_flush) 1498 pending_flush |= ctl->ops.get_pending_flush(ctl); 1499 } 1500 1501 /* for split flush, combine pending flush masks and send to master */ 1502 if (pending_flush && dpu_enc->cur_master) { 1503 _dpu_encoder_trigger_flush( 1504 &dpu_enc->base, 1505 dpu_enc->cur_master, 1506 pending_flush); 1507 } 1508 1509 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1510 1511 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1512 } 1513 1514 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1515 { 1516 struct dpu_encoder_virt *dpu_enc; 1517 struct dpu_encoder_phys *phys; 1518 unsigned int i; 1519 struct dpu_hw_ctl *ctl; 1520 struct msm_display_info *disp_info; 1521 1522 if (!drm_enc) { 1523 DPU_ERROR("invalid encoder\n"); 1524 return; 1525 } 1526 dpu_enc = to_dpu_encoder_virt(drm_enc); 1527 disp_info = &dpu_enc->disp_info; 1528 1529 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1530 phys = dpu_enc->phys_encs[i]; 1531 1532 ctl = phys->hw_ctl; 1533 if (ctl->ops.clear_pending_flush) 1534 ctl->ops.clear_pending_flush(ctl); 1535 1536 /* update only for command mode primary ctl */ 1537 if ((phys == dpu_enc->cur_master) && 1538 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1539 && ctl->ops.trigger_pending) 1540 ctl->ops.trigger_pending(ctl); 1541 } 1542 } 1543 1544 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1545 struct drm_display_mode *mode) 1546 { 1547 u64 pclk_rate; 1548 u32 pclk_period; 1549 u32 line_time; 1550 1551 /* 1552 * For linetime calculation, only operate on master encoder. 1553 */ 1554 if (!dpu_enc->cur_master) 1555 return 0; 1556 1557 if (!dpu_enc->cur_master->ops.get_line_count) { 1558 DPU_ERROR("get_line_count function not defined\n"); 1559 return 0; 1560 } 1561 1562 pclk_rate = mode->clock; /* pixel clock in kHz */ 1563 if (pclk_rate == 0) { 1564 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1565 return 0; 1566 } 1567 1568 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1569 if (pclk_period == 0) { 1570 DPU_ERROR("pclk period is 0\n"); 1571 return 0; 1572 } 1573 1574 /* 1575 * Line time calculation based on Pixel clock and HTOTAL. 1576 * Final unit is in ns. 1577 */ 1578 line_time = (pclk_period * mode->htotal) / 1000; 1579 if (line_time == 0) { 1580 DPU_ERROR("line time calculation is 0\n"); 1581 return 0; 1582 } 1583 1584 DPU_DEBUG_ENC(dpu_enc, 1585 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1586 pclk_rate, pclk_period, line_time); 1587 1588 return line_time; 1589 } 1590 1591 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1592 { 1593 struct drm_display_mode *mode; 1594 struct dpu_encoder_virt *dpu_enc; 1595 u32 cur_line; 1596 u32 line_time; 1597 u32 vtotal, time_to_vsync; 1598 ktime_t cur_time; 1599 1600 dpu_enc = to_dpu_encoder_virt(drm_enc); 1601 1602 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1603 DPU_ERROR("crtc/crtc state object is NULL\n"); 1604 return -EINVAL; 1605 } 1606 mode = &drm_enc->crtc->state->adjusted_mode; 1607 1608 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1609 if (!line_time) 1610 return -EINVAL; 1611 1612 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1613 1614 vtotal = mode->vtotal; 1615 if (cur_line >= vtotal) 1616 time_to_vsync = line_time * vtotal; 1617 else 1618 time_to_vsync = line_time * (vtotal - cur_line); 1619 1620 if (time_to_vsync == 0) { 1621 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1622 vtotal); 1623 return -EINVAL; 1624 } 1625 1626 cur_time = ktime_get(); 1627 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1628 1629 DPU_DEBUG_ENC(dpu_enc, 1630 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1631 cur_line, vtotal, time_to_vsync, 1632 ktime_to_ms(cur_time), 1633 ktime_to_ms(*wakeup_time)); 1634 return 0; 1635 } 1636 1637 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1638 { 1639 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1640 vsync_event_timer); 1641 struct drm_encoder *drm_enc = &dpu_enc->base; 1642 struct msm_drm_private *priv; 1643 struct msm_drm_thread *event_thread; 1644 1645 if (!drm_enc->dev || !drm_enc->crtc) { 1646 DPU_ERROR("invalid parameters\n"); 1647 return; 1648 } 1649 1650 priv = drm_enc->dev->dev_private; 1651 1652 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1653 DPU_ERROR("invalid crtc index\n"); 1654 return; 1655 } 1656 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1657 if (!event_thread) { 1658 DPU_ERROR("event_thread not found for crtc:%d\n", 1659 drm_enc->crtc->index); 1660 return; 1661 } 1662 1663 del_timer(&dpu_enc->vsync_event_timer); 1664 } 1665 1666 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1667 { 1668 struct dpu_encoder_virt *dpu_enc = container_of(work, 1669 struct dpu_encoder_virt, vsync_event_work); 1670 ktime_t wakeup_time; 1671 1672 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) 1673 return; 1674 1675 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1676 mod_timer(&dpu_enc->vsync_event_timer, 1677 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1678 } 1679 1680 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1681 { 1682 struct dpu_encoder_virt *dpu_enc; 1683 struct dpu_encoder_phys *phys; 1684 bool needs_hw_reset = false; 1685 unsigned int i; 1686 1687 dpu_enc = to_dpu_encoder_virt(drm_enc); 1688 1689 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1690 1691 /* prepare for next kickoff, may include waiting on previous kickoff */ 1692 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1693 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1694 phys = dpu_enc->phys_encs[i]; 1695 if (phys->ops.prepare_for_kickoff) 1696 phys->ops.prepare_for_kickoff(phys); 1697 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1698 needs_hw_reset = true; 1699 } 1700 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1701 1702 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1703 1704 /* if any phys needs reset, reset all phys, in-order */ 1705 if (needs_hw_reset) { 1706 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1707 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1708 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1709 } 1710 } 1711 } 1712 1713 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1714 { 1715 struct dpu_encoder_virt *dpu_enc; 1716 struct dpu_encoder_phys *phys; 1717 ktime_t wakeup_time; 1718 unsigned long timeout_ms; 1719 unsigned int i; 1720 1721 DPU_ATRACE_BEGIN("encoder_kickoff"); 1722 dpu_enc = to_dpu_encoder_virt(drm_enc); 1723 1724 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1725 1726 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1727 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1728 1729 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1730 mod_timer(&dpu_enc->frame_done_timer, 1731 jiffies + msecs_to_jiffies(timeout_ms)); 1732 1733 /* All phys encs are ready to go, trigger the kickoff */ 1734 _dpu_encoder_kickoff_phys(dpu_enc); 1735 1736 /* allow phys encs to handle any post-kickoff business */ 1737 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1738 phys = dpu_enc->phys_encs[i]; 1739 if (phys->ops.handle_post_kickoff) 1740 phys->ops.handle_post_kickoff(phys); 1741 } 1742 1743 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1744 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { 1745 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1746 ktime_to_ms(wakeup_time)); 1747 mod_timer(&dpu_enc->vsync_event_timer, 1748 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1749 } 1750 1751 DPU_ATRACE_END("encoder_kickoff"); 1752 } 1753 1754 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1755 { 1756 struct dpu_encoder_virt *dpu_enc; 1757 struct dpu_encoder_phys *phys; 1758 int i; 1759 1760 if (!drm_enc) { 1761 DPU_ERROR("invalid encoder\n"); 1762 return; 1763 } 1764 dpu_enc = to_dpu_encoder_virt(drm_enc); 1765 1766 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1767 phys = dpu_enc->phys_encs[i]; 1768 if (phys->ops.prepare_commit) 1769 phys->ops.prepare_commit(phys); 1770 } 1771 } 1772 1773 #ifdef CONFIG_DEBUG_FS 1774 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1775 { 1776 struct dpu_encoder_virt *dpu_enc = s->private; 1777 int i; 1778 1779 mutex_lock(&dpu_enc->enc_lock); 1780 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1781 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1782 1783 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1784 phys->intf_idx - INTF_0, 1785 atomic_read(&phys->vsync_cnt), 1786 atomic_read(&phys->underrun_cnt)); 1787 1788 switch (phys->intf_mode) { 1789 case INTF_MODE_VIDEO: 1790 seq_puts(s, "mode: video\n"); 1791 break; 1792 case INTF_MODE_CMD: 1793 seq_puts(s, "mode: command\n"); 1794 break; 1795 default: 1796 seq_puts(s, "mode: ???\n"); 1797 break; 1798 } 1799 } 1800 mutex_unlock(&dpu_enc->enc_lock); 1801 1802 return 0; 1803 } 1804 1805 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status); 1806 1807 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1808 { 1809 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1810 int i; 1811 1812 char name[DPU_NAME_SIZE]; 1813 1814 if (!drm_enc->dev) { 1815 DPU_ERROR("invalid encoder or kms\n"); 1816 return -EINVAL; 1817 } 1818 1819 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1820 1821 /* create overall sub-directory for the encoder */ 1822 dpu_enc->debugfs_root = debugfs_create_dir(name, 1823 drm_enc->dev->primary->debugfs_root); 1824 1825 /* don't error check these */ 1826 debugfs_create_file("status", 0600, 1827 dpu_enc->debugfs_root, dpu_enc, &_dpu_encoder_status_fops); 1828 1829 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1830 if (dpu_enc->phys_encs[i]->ops.late_register) 1831 dpu_enc->phys_encs[i]->ops.late_register( 1832 dpu_enc->phys_encs[i], 1833 dpu_enc->debugfs_root); 1834 1835 return 0; 1836 } 1837 #else 1838 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1839 { 1840 return 0; 1841 } 1842 #endif 1843 1844 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1845 { 1846 return _dpu_encoder_init_debugfs(encoder); 1847 } 1848 1849 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1850 { 1851 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1852 1853 debugfs_remove_recursive(dpu_enc->debugfs_root); 1854 } 1855 1856 static int dpu_encoder_virt_add_phys_encs( 1857 u32 display_caps, 1858 struct dpu_encoder_virt *dpu_enc, 1859 struct dpu_enc_phys_init_params *params) 1860 { 1861 struct dpu_encoder_phys *enc = NULL; 1862 1863 DPU_DEBUG_ENC(dpu_enc, "\n"); 1864 1865 /* 1866 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1867 * in this function, check up-front. 1868 */ 1869 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1870 ARRAY_SIZE(dpu_enc->phys_encs)) { 1871 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1872 dpu_enc->num_phys_encs); 1873 return -EINVAL; 1874 } 1875 1876 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1877 enc = dpu_encoder_phys_vid_init(params); 1878 1879 if (IS_ERR_OR_NULL(enc)) { 1880 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1881 PTR_ERR(enc)); 1882 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1883 } 1884 1885 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1886 ++dpu_enc->num_phys_encs; 1887 } 1888 1889 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 1890 enc = dpu_encoder_phys_cmd_init(params); 1891 1892 if (IS_ERR_OR_NULL(enc)) { 1893 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 1894 PTR_ERR(enc)); 1895 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1896 } 1897 1898 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1899 ++dpu_enc->num_phys_encs; 1900 } 1901 1902 if (params->split_role == ENC_ROLE_SLAVE) 1903 dpu_enc->cur_slave = enc; 1904 else 1905 dpu_enc->cur_master = enc; 1906 1907 return 0; 1908 } 1909 1910 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 1911 .handle_vblank_virt = dpu_encoder_vblank_callback, 1912 .handle_underrun_virt = dpu_encoder_underrun_callback, 1913 .handle_frame_done = dpu_encoder_frame_done_callback, 1914 }; 1915 1916 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 1917 struct dpu_kms *dpu_kms, 1918 struct msm_display_info *disp_info) 1919 { 1920 int ret = 0; 1921 int i = 0; 1922 enum dpu_intf_type intf_type = INTF_NONE; 1923 struct dpu_enc_phys_init_params phys_params; 1924 1925 if (!dpu_enc) { 1926 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 1927 return -EINVAL; 1928 } 1929 1930 dpu_enc->cur_master = NULL; 1931 1932 memset(&phys_params, 0, sizeof(phys_params)); 1933 phys_params.dpu_kms = dpu_kms; 1934 phys_params.parent = &dpu_enc->base; 1935 phys_params.parent_ops = &dpu_encoder_parent_ops; 1936 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 1937 1938 switch (disp_info->intf_type) { 1939 case DRM_MODE_ENCODER_DSI: 1940 intf_type = INTF_DSI; 1941 break; 1942 case DRM_MODE_ENCODER_TMDS: 1943 intf_type = INTF_DP; 1944 break; 1945 } 1946 1947 WARN_ON(disp_info->num_of_h_tiles < 1); 1948 1949 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 1950 1951 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 1952 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 1953 dpu_enc->idle_pc_supported = 1954 dpu_kms->catalog->caps->has_idle_pc; 1955 1956 mutex_lock(&dpu_enc->enc_lock); 1957 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 1958 /* 1959 * Left-most tile is at index 0, content is controller id 1960 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 1961 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 1962 */ 1963 u32 controller_id = disp_info->h_tile_instance[i]; 1964 1965 if (disp_info->num_of_h_tiles > 1) { 1966 if (i == 0) 1967 phys_params.split_role = ENC_ROLE_MASTER; 1968 else 1969 phys_params.split_role = ENC_ROLE_SLAVE; 1970 } else { 1971 phys_params.split_role = ENC_ROLE_SOLO; 1972 } 1973 1974 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 1975 i, controller_id, phys_params.split_role); 1976 1977 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 1978 intf_type, 1979 controller_id); 1980 if (phys_params.intf_idx == INTF_MAX) { 1981 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 1982 intf_type, controller_id); 1983 ret = -EINVAL; 1984 } 1985 1986 if (!ret) { 1987 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 1988 dpu_enc, 1989 &phys_params); 1990 if (ret) 1991 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 1992 } 1993 } 1994 1995 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1996 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1997 atomic_set(&phys->vsync_cnt, 0); 1998 atomic_set(&phys->underrun_cnt, 0); 1999 } 2000 mutex_unlock(&dpu_enc->enc_lock); 2001 2002 return ret; 2003 } 2004 2005 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2006 { 2007 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2008 frame_done_timer); 2009 struct drm_encoder *drm_enc = &dpu_enc->base; 2010 u32 event; 2011 2012 if (!drm_enc->dev) { 2013 DPU_ERROR("invalid parameters\n"); 2014 return; 2015 } 2016 2017 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2018 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2019 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2020 return; 2021 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2022 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2023 return; 2024 } 2025 2026 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2027 2028 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2029 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2030 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2031 } 2032 2033 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2034 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set, 2035 .disable = dpu_encoder_virt_disable, 2036 .enable = dpu_encoder_virt_enable, 2037 .atomic_check = dpu_encoder_virt_atomic_check, 2038 }; 2039 2040 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2041 .destroy = dpu_encoder_destroy, 2042 .late_register = dpu_encoder_late_register, 2043 .early_unregister = dpu_encoder_early_unregister, 2044 }; 2045 2046 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2047 struct msm_display_info *disp_info) 2048 { 2049 struct msm_drm_private *priv = dev->dev_private; 2050 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2051 struct drm_encoder *drm_enc = NULL; 2052 struct dpu_encoder_virt *dpu_enc = NULL; 2053 int ret = 0; 2054 2055 dpu_enc = to_dpu_encoder_virt(enc); 2056 2057 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2058 if (ret) 2059 goto fail; 2060 2061 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2062 timer_setup(&dpu_enc->frame_done_timer, 2063 dpu_encoder_frame_done_timeout, 0); 2064 2065 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2066 timer_setup(&dpu_enc->vsync_event_timer, 2067 dpu_encoder_vsync_event_handler, 2068 0); 2069 2070 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2071 dpu_encoder_off_work); 2072 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2073 2074 kthread_init_work(&dpu_enc->vsync_event_work, 2075 dpu_encoder_vsync_event_work_handler); 2076 2077 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2078 2079 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2080 2081 return ret; 2082 2083 fail: 2084 DPU_ERROR("failed to create encoder\n"); 2085 if (drm_enc) 2086 dpu_encoder_destroy(drm_enc); 2087 2088 return ret; 2089 2090 2091 } 2092 2093 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2094 int drm_enc_mode) 2095 { 2096 struct dpu_encoder_virt *dpu_enc = NULL; 2097 int rc = 0; 2098 2099 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2100 if (!dpu_enc) 2101 return ERR_PTR(-ENOMEM); 2102 2103 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2104 drm_enc_mode, NULL); 2105 if (rc) { 2106 devm_kfree(dev->dev, dpu_enc); 2107 return ERR_PTR(rc); 2108 } 2109 2110 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2111 2112 spin_lock_init(&dpu_enc->enc_spinlock); 2113 dpu_enc->enabled = false; 2114 mutex_init(&dpu_enc->enc_lock); 2115 mutex_init(&dpu_enc->rc_lock); 2116 2117 return &dpu_enc->base; 2118 } 2119 2120 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2121 enum msm_event_wait event) 2122 { 2123 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2124 struct dpu_encoder_virt *dpu_enc = NULL; 2125 int i, ret = 0; 2126 2127 if (!drm_enc) { 2128 DPU_ERROR("invalid encoder\n"); 2129 return -EINVAL; 2130 } 2131 dpu_enc = to_dpu_encoder_virt(drm_enc); 2132 DPU_DEBUG_ENC(dpu_enc, "\n"); 2133 2134 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2135 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2136 2137 switch (event) { 2138 case MSM_ENC_COMMIT_DONE: 2139 fn_wait = phys->ops.wait_for_commit_done; 2140 break; 2141 case MSM_ENC_TX_COMPLETE: 2142 fn_wait = phys->ops.wait_for_tx_complete; 2143 break; 2144 case MSM_ENC_VBLANK: 2145 fn_wait = phys->ops.wait_for_vblank; 2146 break; 2147 default: 2148 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2149 event); 2150 return -EINVAL; 2151 } 2152 2153 if (fn_wait) { 2154 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2155 ret = fn_wait(phys); 2156 DPU_ATRACE_END("wait_for_completion_event"); 2157 if (ret) 2158 return ret; 2159 } 2160 } 2161 2162 return ret; 2163 } 2164 2165 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2166 { 2167 struct dpu_encoder_virt *dpu_enc = NULL; 2168 2169 if (!encoder) { 2170 DPU_ERROR("invalid encoder\n"); 2171 return INTF_MODE_NONE; 2172 } 2173 dpu_enc = to_dpu_encoder_virt(encoder); 2174 2175 if (dpu_enc->cur_master) 2176 return dpu_enc->cur_master->intf_mode; 2177 2178 if (dpu_enc->num_phys_encs) 2179 return dpu_enc->phys_encs[0]->intf_mode; 2180 2181 return INTF_MODE_NONE; 2182 } 2183