1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 #include <linux/debugfs.h> 10 #include <linux/kthread.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_probe_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_hwio.h" 20 #include "dpu_hw_catalog.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_ctl.h" 23 #include "dpu_hw_dspp.h" 24 #include "dpu_formats.h" 25 #include "dpu_encoder_phys.h" 26 #include "dpu_crtc.h" 27 #include "dpu_trace.h" 28 #include "dpu_core_irq.h" 29 30 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ 31 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 32 33 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 34 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 35 36 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ 37 (p) ? (p)->parent->base.id : -1, \ 38 (p) ? (p)->intf_idx - INTF_0 : -1, \ 39 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 40 ##__VA_ARGS__) 41 42 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 43 (p) ? (p)->parent->base.id : -1, \ 44 (p) ? (p)->intf_idx - INTF_0 : -1, \ 45 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 46 ##__VA_ARGS__) 47 48 /* 49 * Two to anticipate panels that can do cmd/vid dynamic switching 50 * plan is to create all possible physical encoder types, and switch between 51 * them at runtime 52 */ 53 #define NUM_PHYS_ENCODER_TYPES 2 54 55 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 56 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 57 58 #define MAX_CHANNELS_PER_ENC 2 59 60 #define IDLE_SHORT_TIMEOUT 1 61 62 #define MAX_HDISPLAY_SPLIT 1080 63 64 /* timeout in frames waiting for frame done */ 65 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 66 67 /** 68 * enum dpu_enc_rc_events - events for resource control state machine 69 * @DPU_ENC_RC_EVENT_KICKOFF: 70 * This event happens at NORMAL priority. 71 * Event that signals the start of the transfer. When this event is 72 * received, enable MDP/DSI core clocks. Regardless of the previous 73 * state, the resource should be in ON state at the end of this event. 74 * @DPU_ENC_RC_EVENT_FRAME_DONE: 75 * This event happens at INTERRUPT level. 76 * Event signals the end of the data transfer after the PP FRAME_DONE 77 * event. At the end of this event, a delayed work is scheduled to go to 78 * IDLE_PC state after IDLE_TIMEOUT time. 79 * @DPU_ENC_RC_EVENT_PRE_STOP: 80 * This event happens at NORMAL priority. 81 * This event, when received during the ON state, leave the RC STATE 82 * in the PRE_OFF state. It should be followed by the STOP event as 83 * part of encoder disable. 84 * If received during IDLE or OFF states, it will do nothing. 85 * @DPU_ENC_RC_EVENT_STOP: 86 * This event happens at NORMAL priority. 87 * When this event is received, disable all the MDP/DSI core clocks, and 88 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 89 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 90 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 91 * Resource state should be in OFF at the end of the event. 92 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 93 * This event happens at NORMAL priority from a work item. 94 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 95 * This would disable MDP/DSI core clocks and change the resource state 96 * to IDLE. 97 */ 98 enum dpu_enc_rc_events { 99 DPU_ENC_RC_EVENT_KICKOFF = 1, 100 DPU_ENC_RC_EVENT_FRAME_DONE, 101 DPU_ENC_RC_EVENT_PRE_STOP, 102 DPU_ENC_RC_EVENT_STOP, 103 DPU_ENC_RC_EVENT_ENTER_IDLE 104 }; 105 106 /* 107 * enum dpu_enc_rc_states - states that the resource control maintains 108 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 109 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 110 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 111 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 112 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 113 */ 114 enum dpu_enc_rc_states { 115 DPU_ENC_RC_STATE_OFF, 116 DPU_ENC_RC_STATE_PRE_OFF, 117 DPU_ENC_RC_STATE_ON, 118 DPU_ENC_RC_STATE_IDLE 119 }; 120 121 /** 122 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 123 * encoders. Virtual encoder manages one "logical" display. Physical 124 * encoders manage one intf block, tied to a specific panel/sub-panel. 125 * Virtual encoder defers as much as possible to the physical encoders. 126 * Virtual encoder registers itself with the DRM Framework as the encoder. 127 * @base: drm_encoder base class for registration with DRM 128 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 129 * @bus_scaling_client: Client handle to the bus scaling interface 130 * @enabled: True if the encoder is active, protected by enc_lock 131 * @num_phys_encs: Actual number of physical encoders contained. 132 * @phys_encs: Container of physical encoders managed. 133 * @cur_master: Pointer to the current master in this mode. Optimization 134 * Only valid after enable. Cleared as disable. 135 * @hw_pp Handle to the pingpong blocks used for the display. No. 136 * pingpong blocks can be different than num_phys_encs. 137 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped 138 * for partial update right-only cases, such as pingpong 139 * split where virtual pingpong does not generate IRQs 140 * @crtc: Pointer to the currently assigned crtc. Normally you 141 * would use crtc->state->encoder_mask to determine the 142 * link between encoder/crtc. However in this case we need 143 * to track crtc in the disable() hook which is called 144 * _after_ encoder_mask is cleared. 145 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 146 * all CTL paths 147 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 148 * @debugfs_root: Debug file system root file node 149 * @enc_lock: Lock around physical encoder 150 * create/destroy/enable/disable 151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 152 * busy processing current command. 153 * Bit0 = phys_encs[0] etc. 154 * @crtc_frame_event_cb: callback handler for frame event 155 * @crtc_frame_event_cb_data: callback handler private data 156 * @frame_done_timeout_ms: frame done timeout in ms 157 * @frame_done_timer: watchdog timer for frame done event 158 * @vsync_event_timer: vsync timer 159 * @disp_info: local copy of msm_display_info struct 160 * @idle_pc_supported: indicate if idle power collaps is supported 161 * @rc_lock: resource control mutex lock to protect 162 * virt encoder over various state changes 163 * @rc_state: resource controller state 164 * @delayed_off_work: delayed worker to schedule disabling of 165 * clks and resources after IDLE_TIMEOUT time. 166 * @vsync_event_work: worker to handle vsync event for autorefresh 167 * @topology: topology of the display 168 * @idle_timeout: idle timeout duration in milliseconds 169 */ 170 struct dpu_encoder_virt { 171 struct drm_encoder base; 172 spinlock_t enc_spinlock; 173 uint32_t bus_scaling_client; 174 175 bool enabled; 176 177 unsigned int num_phys_encs; 178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 179 struct dpu_encoder_phys *cur_master; 180 struct dpu_encoder_phys *cur_slave; 181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 182 183 bool intfs_swapped; 184 185 struct drm_crtc *crtc; 186 187 struct dentry *debugfs_root; 188 struct mutex enc_lock; 189 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 190 void (*crtc_frame_event_cb)(void *, u32 event); 191 void *crtc_frame_event_cb_data; 192 193 atomic_t frame_done_timeout_ms; 194 struct timer_list frame_done_timer; 195 struct timer_list vsync_event_timer; 196 197 struct msm_display_info disp_info; 198 199 bool idle_pc_supported; 200 struct mutex rc_lock; 201 enum dpu_enc_rc_states rc_state; 202 struct delayed_work delayed_off_work; 203 struct kthread_work vsync_event_work; 204 struct msm_display_topology topology; 205 206 u32 idle_timeout; 207 }; 208 209 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 210 211 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 212 enum dpu_intr_idx intr_idx) 213 { 214 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 215 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 216 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 217 218 if (phys_enc->parent_ops->handle_frame_done) 219 phys_enc->parent_ops->handle_frame_done( 220 phys_enc->parent, phys_enc, 221 DPU_ENCODER_FRAME_EVENT_ERROR); 222 } 223 224 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 225 int32_t hw_id, struct dpu_encoder_wait_info *info); 226 227 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 228 enum dpu_intr_idx intr_idx, 229 struct dpu_encoder_wait_info *wait_info) 230 { 231 struct dpu_encoder_irq *irq; 232 u32 irq_status; 233 int ret; 234 235 if (!wait_info || intr_idx >= INTR_IDX_MAX) { 236 DPU_ERROR("invalid params\n"); 237 return -EINVAL; 238 } 239 irq = &phys_enc->irq[intr_idx]; 240 241 /* note: do master / slave checking outside */ 242 243 /* return EWOULDBLOCK since we know the wait isn't necessary */ 244 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 245 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", 246 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 247 irq->irq_idx); 248 return -EWOULDBLOCK; 249 } 250 251 if (irq->irq_idx < 0) { 252 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", 253 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 254 irq->name); 255 return 0; 256 } 257 258 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", 259 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 260 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 261 atomic_read(wait_info->atomic_cnt)); 262 263 ret = dpu_encoder_helper_wait_event_timeout( 264 DRMID(phys_enc->parent), 265 irq->hw_idx, 266 wait_info); 267 268 if (ret <= 0) { 269 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 270 irq->irq_idx, true); 271 if (irq_status) { 272 unsigned long flags; 273 274 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " 275 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 276 DRMID(phys_enc->parent), intr_idx, 277 irq->hw_idx, irq->irq_idx, 278 phys_enc->hw_pp->idx - PINGPONG_0, 279 atomic_read(wait_info->atomic_cnt)); 280 local_irq_save(flags); 281 irq->cb.func(phys_enc, irq->irq_idx); 282 local_irq_restore(flags); 283 ret = 0; 284 } else { 285 ret = -ETIMEDOUT; 286 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " 287 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 288 DRMID(phys_enc->parent), intr_idx, 289 irq->hw_idx, irq->irq_idx, 290 phys_enc->hw_pp->idx - PINGPONG_0, 291 atomic_read(wait_info->atomic_cnt)); 292 } 293 } else { 294 ret = 0; 295 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 296 intr_idx, irq->hw_idx, irq->irq_idx, 297 phys_enc->hw_pp->idx - PINGPONG_0, 298 atomic_read(wait_info->atomic_cnt)); 299 } 300 301 return ret; 302 } 303 304 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 305 enum dpu_intr_idx intr_idx) 306 { 307 struct dpu_encoder_irq *irq; 308 int ret = 0; 309 310 if (intr_idx >= INTR_IDX_MAX) { 311 DPU_ERROR("invalid params\n"); 312 return -EINVAL; 313 } 314 irq = &phys_enc->irq[intr_idx]; 315 316 if (irq->irq_idx >= 0) { 317 DPU_DEBUG_PHYS(phys_enc, 318 "skipping already registered irq %s type %d\n", 319 irq->name, irq->intr_type); 320 return 0; 321 } 322 323 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, 324 irq->intr_type, irq->hw_idx); 325 if (irq->irq_idx < 0) { 326 DPU_ERROR_PHYS(phys_enc, 327 "failed to lookup IRQ index for %s type:%d\n", 328 irq->name, irq->intr_type); 329 return -EINVAL; 330 } 331 332 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 333 &irq->cb); 334 if (ret) { 335 DPU_ERROR_PHYS(phys_enc, 336 "failed to register IRQ callback for %s\n", 337 irq->name); 338 irq->irq_idx = -EINVAL; 339 return ret; 340 } 341 342 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); 343 if (ret) { 344 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", 345 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 346 irq->irq_idx); 347 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 348 irq->irq_idx, &irq->cb); 349 irq->irq_idx = -EINVAL; 350 return ret; 351 } 352 353 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 354 irq->hw_idx, irq->irq_idx); 355 356 return ret; 357 } 358 359 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 360 enum dpu_intr_idx intr_idx) 361 { 362 struct dpu_encoder_irq *irq; 363 int ret; 364 365 irq = &phys_enc->irq[intr_idx]; 366 367 /* silently skip irqs that weren't registered */ 368 if (irq->irq_idx < 0) { 369 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", 370 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 371 irq->irq_idx); 372 return 0; 373 } 374 375 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); 376 if (ret) { 377 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", 378 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 379 irq->irq_idx, ret); 380 } 381 382 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 383 &irq->cb); 384 if (ret) { 385 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", 386 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 387 irq->irq_idx, ret); 388 } 389 390 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 391 irq->hw_idx, irq->irq_idx); 392 393 irq->irq_idx = -EINVAL; 394 395 return 0; 396 } 397 398 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, 399 struct dpu_encoder_hw_resources *hw_res) 400 { 401 struct dpu_encoder_virt *dpu_enc = NULL; 402 int i = 0; 403 404 dpu_enc = to_dpu_encoder_virt(drm_enc); 405 DPU_DEBUG_ENC(dpu_enc, "\n"); 406 407 /* Query resources used by phys encs, expected to be without overlap */ 408 memset(hw_res, 0, sizeof(*hw_res)); 409 410 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 411 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 412 413 if (phys->ops.get_hw_resources) 414 phys->ops.get_hw_resources(phys, hw_res); 415 } 416 } 417 418 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 419 { 420 struct dpu_encoder_virt *dpu_enc = NULL; 421 int i = 0; 422 423 if (!drm_enc) { 424 DPU_ERROR("invalid encoder\n"); 425 return; 426 } 427 428 dpu_enc = to_dpu_encoder_virt(drm_enc); 429 DPU_DEBUG_ENC(dpu_enc, "\n"); 430 431 mutex_lock(&dpu_enc->enc_lock); 432 433 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 434 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 435 436 if (phys->ops.destroy) { 437 phys->ops.destroy(phys); 438 --dpu_enc->num_phys_encs; 439 dpu_enc->phys_encs[i] = NULL; 440 } 441 } 442 443 if (dpu_enc->num_phys_encs) 444 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 445 dpu_enc->num_phys_encs); 446 dpu_enc->num_phys_encs = 0; 447 mutex_unlock(&dpu_enc->enc_lock); 448 449 drm_encoder_cleanup(drm_enc); 450 mutex_destroy(&dpu_enc->enc_lock); 451 } 452 453 void dpu_encoder_helper_split_config( 454 struct dpu_encoder_phys *phys_enc, 455 enum dpu_intf interface) 456 { 457 struct dpu_encoder_virt *dpu_enc; 458 struct split_pipe_cfg cfg = { 0 }; 459 struct dpu_hw_mdp *hw_mdptop; 460 struct msm_display_info *disp_info; 461 462 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 463 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 464 return; 465 } 466 467 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 468 hw_mdptop = phys_enc->hw_mdptop; 469 disp_info = &dpu_enc->disp_info; 470 471 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 472 return; 473 474 /** 475 * disable split modes since encoder will be operating in as the only 476 * encoder, either for the entire use case in the case of, for example, 477 * single DSI, or for this frame in the case of left/right only partial 478 * update. 479 */ 480 if (phys_enc->split_role == ENC_ROLE_SOLO) { 481 if (hw_mdptop->ops.setup_split_pipe) 482 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 483 return; 484 } 485 486 cfg.en = true; 487 cfg.mode = phys_enc->intf_mode; 488 cfg.intf = interface; 489 490 if (cfg.en && phys_enc->ops.needs_single_flush && 491 phys_enc->ops.needs_single_flush(phys_enc)) 492 cfg.split_flush_en = true; 493 494 if (phys_enc->split_role == ENC_ROLE_MASTER) { 495 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 496 497 if (hw_mdptop->ops.setup_split_pipe) 498 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 499 } 500 } 501 502 static void _dpu_encoder_adjust_mode(struct drm_connector *connector, 503 struct drm_display_mode *adj_mode) 504 { 505 struct drm_display_mode *cur_mode; 506 507 if (!connector || !adj_mode) 508 return; 509 510 list_for_each_entry(cur_mode, &connector->modes, head) { 511 if (cur_mode->vdisplay == adj_mode->vdisplay && 512 cur_mode->hdisplay == adj_mode->hdisplay && 513 drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) { 514 adj_mode->private_flags |= cur_mode->private_flags; 515 } 516 } 517 } 518 519 static struct msm_display_topology dpu_encoder_get_topology( 520 struct dpu_encoder_virt *dpu_enc, 521 struct dpu_kms *dpu_kms, 522 struct drm_display_mode *mode) 523 { 524 struct msm_display_topology topology = {0}; 525 int i, intf_count = 0; 526 527 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 528 if (dpu_enc->phys_encs[i]) 529 intf_count++; 530 531 /* Datapath topology selection 532 * 533 * Dual display 534 * 2 LM, 2 INTF ( Split display using 2 interfaces) 535 * 536 * Single display 537 * 1 LM, 1 INTF 538 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 539 * 540 * Adding color blocks only to primary interface if available in 541 * sufficient number 542 */ 543 if (intf_count == 2) 544 topology.num_lm = 2; 545 else if (!dpu_kms->catalog->caps->has_3d_merge) 546 topology.num_lm = 1; 547 else 548 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 549 550 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { 551 if (dpu_kms->catalog->dspp && 552 (dpu_kms->catalog->dspp_count >= topology.num_lm)) 553 topology.num_dspp = topology.num_lm; 554 } 555 556 topology.num_enc = 0; 557 topology.num_intf = intf_count; 558 559 return topology; 560 } 561 static int dpu_encoder_virt_atomic_check( 562 struct drm_encoder *drm_enc, 563 struct drm_crtc_state *crtc_state, 564 struct drm_connector_state *conn_state) 565 { 566 struct dpu_encoder_virt *dpu_enc; 567 struct msm_drm_private *priv; 568 struct dpu_kms *dpu_kms; 569 const struct drm_display_mode *mode; 570 struct drm_display_mode *adj_mode; 571 struct msm_display_topology topology; 572 struct dpu_global_state *global_state; 573 int i = 0; 574 int ret = 0; 575 576 if (!drm_enc || !crtc_state || !conn_state) { 577 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 578 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 579 return -EINVAL; 580 } 581 582 dpu_enc = to_dpu_encoder_virt(drm_enc); 583 DPU_DEBUG_ENC(dpu_enc, "\n"); 584 585 priv = drm_enc->dev->dev_private; 586 dpu_kms = to_dpu_kms(priv->kms); 587 mode = &crtc_state->mode; 588 adj_mode = &crtc_state->adjusted_mode; 589 global_state = dpu_kms_get_existing_global_state(dpu_kms); 590 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 591 592 /* 593 * display drivers may populate private fields of the drm display mode 594 * structure while registering possible modes of a connector with DRM. 595 * These private fields are not populated back while DRM invokes 596 * the mode_set callbacks. This module retrieves and populates the 597 * private fields of the given mode. 598 */ 599 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode); 600 601 /* perform atomic check on the first physical encoder (master) */ 602 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 603 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 604 605 if (phys->ops.atomic_check) 606 ret = phys->ops.atomic_check(phys, crtc_state, 607 conn_state); 608 else if (phys->ops.mode_fixup) 609 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) 610 ret = -EINVAL; 611 612 if (ret) { 613 DPU_ERROR_ENC(dpu_enc, 614 "mode unsupported, phys idx %d\n", i); 615 break; 616 } 617 } 618 619 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 620 621 /* Reserve dynamic resources now. */ 622 if (!ret) { 623 /* 624 * Avoid reserving resources when mode set is pending. Topology 625 * info may not be available to complete reservation. 626 */ 627 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 628 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 629 drm_enc, crtc_state, topology); 630 } 631 } 632 633 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags, 634 adj_mode->private_flags); 635 636 return ret; 637 } 638 639 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 640 struct msm_display_info *disp_info) 641 { 642 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 643 struct msm_drm_private *priv; 644 struct dpu_kms *dpu_kms; 645 struct dpu_hw_mdp *hw_mdptop; 646 struct drm_encoder *drm_enc; 647 int i; 648 649 if (!dpu_enc || !disp_info) { 650 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 651 dpu_enc != NULL, disp_info != NULL); 652 return; 653 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 654 DPU_ERROR("invalid num phys enc %d/%d\n", 655 dpu_enc->num_phys_encs, 656 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 657 return; 658 } 659 660 drm_enc = &dpu_enc->base; 661 /* this pointers are checked in virt_enable_helper */ 662 priv = drm_enc->dev->dev_private; 663 664 dpu_kms = to_dpu_kms(priv->kms); 665 hw_mdptop = dpu_kms->hw_mdp; 666 if (!hw_mdptop) { 667 DPU_ERROR("invalid mdptop\n"); 668 return; 669 } 670 671 if (hw_mdptop->ops.setup_vsync_source && 672 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 673 for (i = 0; i < dpu_enc->num_phys_encs; i++) 674 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 675 676 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 677 if (disp_info->is_te_using_watchdog_timer) 678 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 679 else 680 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 681 682 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 683 } 684 } 685 686 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 687 { 688 struct dpu_encoder_virt *dpu_enc; 689 int i; 690 691 if (!drm_enc) { 692 DPU_ERROR("invalid encoder\n"); 693 return; 694 } 695 696 dpu_enc = to_dpu_encoder_virt(drm_enc); 697 698 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 699 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 700 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 701 702 if (phys->ops.irq_control) 703 phys->ops.irq_control(phys, enable); 704 } 705 706 } 707 708 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 709 bool enable) 710 { 711 struct msm_drm_private *priv; 712 struct dpu_kms *dpu_kms; 713 struct dpu_encoder_virt *dpu_enc; 714 715 dpu_enc = to_dpu_encoder_virt(drm_enc); 716 priv = drm_enc->dev->dev_private; 717 dpu_kms = to_dpu_kms(priv->kms); 718 719 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 720 721 if (!dpu_enc->cur_master) { 722 DPU_ERROR("encoder master not set\n"); 723 return; 724 } 725 726 if (enable) { 727 /* enable DPU core clks */ 728 pm_runtime_get_sync(&dpu_kms->pdev->dev); 729 730 /* enable all the irq */ 731 _dpu_encoder_irq_control(drm_enc, true); 732 733 } else { 734 /* disable all the irq */ 735 _dpu_encoder_irq_control(drm_enc, false); 736 737 /* disable DPU core clks */ 738 pm_runtime_put_sync(&dpu_kms->pdev->dev); 739 } 740 741 } 742 743 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 744 u32 sw_event) 745 { 746 struct dpu_encoder_virt *dpu_enc; 747 struct msm_drm_private *priv; 748 bool is_vid_mode = false; 749 750 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 751 DPU_ERROR("invalid parameters\n"); 752 return -EINVAL; 753 } 754 dpu_enc = to_dpu_encoder_virt(drm_enc); 755 priv = drm_enc->dev->dev_private; 756 is_vid_mode = dpu_enc->disp_info.capabilities & 757 MSM_DISPLAY_CAP_VID_MODE; 758 759 /* 760 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 761 * events and return early for other events (ie wb display). 762 */ 763 if (!dpu_enc->idle_pc_supported && 764 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 765 sw_event != DPU_ENC_RC_EVENT_STOP && 766 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 767 return 0; 768 769 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 770 dpu_enc->rc_state, "begin"); 771 772 switch (sw_event) { 773 case DPU_ENC_RC_EVENT_KICKOFF: 774 /* cancel delayed off work, if any */ 775 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 776 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 777 sw_event); 778 779 mutex_lock(&dpu_enc->rc_lock); 780 781 /* return if the resource control is already in ON state */ 782 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 783 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", 784 DRMID(drm_enc), sw_event); 785 mutex_unlock(&dpu_enc->rc_lock); 786 return 0; 787 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 788 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 789 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", 790 DRMID(drm_enc), sw_event, 791 dpu_enc->rc_state); 792 mutex_unlock(&dpu_enc->rc_lock); 793 return -EINVAL; 794 } 795 796 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 797 _dpu_encoder_irq_control(drm_enc, true); 798 else 799 _dpu_encoder_resource_control_helper(drm_enc, true); 800 801 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 802 803 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 804 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 805 "kickoff"); 806 807 mutex_unlock(&dpu_enc->rc_lock); 808 break; 809 810 case DPU_ENC_RC_EVENT_FRAME_DONE: 811 /* 812 * mutex lock is not used as this event happens at interrupt 813 * context. And locking is not required as, the other events 814 * like KICKOFF and STOP does a wait-for-idle before executing 815 * the resource_control 816 */ 817 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 818 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 819 DRMID(drm_enc), sw_event, 820 dpu_enc->rc_state); 821 return -EINVAL; 822 } 823 824 /* 825 * schedule off work item only when there are no 826 * frames pending 827 */ 828 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 829 DRM_DEBUG_KMS("id:%d skip schedule work\n", 830 DRMID(drm_enc)); 831 return 0; 832 } 833 834 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 835 msecs_to_jiffies(dpu_enc->idle_timeout)); 836 837 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 838 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 839 "frame done"); 840 break; 841 842 case DPU_ENC_RC_EVENT_PRE_STOP: 843 /* cancel delayed off work, if any */ 844 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 845 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 846 sw_event); 847 848 mutex_lock(&dpu_enc->rc_lock); 849 850 if (is_vid_mode && 851 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 852 _dpu_encoder_irq_control(drm_enc, true); 853 } 854 /* skip if is already OFF or IDLE, resources are off already */ 855 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 856 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 857 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 858 DRMID(drm_enc), sw_event, 859 dpu_enc->rc_state); 860 mutex_unlock(&dpu_enc->rc_lock); 861 return 0; 862 } 863 864 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 865 866 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 867 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 868 "pre stop"); 869 870 mutex_unlock(&dpu_enc->rc_lock); 871 break; 872 873 case DPU_ENC_RC_EVENT_STOP: 874 mutex_lock(&dpu_enc->rc_lock); 875 876 /* return if the resource control is already in OFF state */ 877 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 878 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 879 DRMID(drm_enc), sw_event); 880 mutex_unlock(&dpu_enc->rc_lock); 881 return 0; 882 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 883 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 884 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 885 mutex_unlock(&dpu_enc->rc_lock); 886 return -EINVAL; 887 } 888 889 /** 890 * expect to arrive here only if in either idle state or pre-off 891 * and in IDLE state the resources are already disabled 892 */ 893 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 894 _dpu_encoder_resource_control_helper(drm_enc, false); 895 896 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 897 898 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 899 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 900 "stop"); 901 902 mutex_unlock(&dpu_enc->rc_lock); 903 break; 904 905 case DPU_ENC_RC_EVENT_ENTER_IDLE: 906 mutex_lock(&dpu_enc->rc_lock); 907 908 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 909 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 910 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 911 mutex_unlock(&dpu_enc->rc_lock); 912 return 0; 913 } 914 915 /* 916 * if we are in ON but a frame was just kicked off, 917 * ignore the IDLE event, it's probably a stale timer event 918 */ 919 if (dpu_enc->frame_busy_mask[0]) { 920 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 921 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 922 mutex_unlock(&dpu_enc->rc_lock); 923 return 0; 924 } 925 926 if (is_vid_mode) 927 _dpu_encoder_irq_control(drm_enc, false); 928 else 929 _dpu_encoder_resource_control_helper(drm_enc, false); 930 931 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 932 933 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 934 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 935 "idle"); 936 937 mutex_unlock(&dpu_enc->rc_lock); 938 break; 939 940 default: 941 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 942 sw_event); 943 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 944 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 945 "error"); 946 break; 947 } 948 949 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 950 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 951 "end"); 952 return 0; 953 } 954 955 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 956 struct drm_display_mode *mode, 957 struct drm_display_mode *adj_mode) 958 { 959 struct dpu_encoder_virt *dpu_enc; 960 struct msm_drm_private *priv; 961 struct dpu_kms *dpu_kms; 962 struct list_head *connector_list; 963 struct drm_connector *conn = NULL, *conn_iter; 964 struct drm_crtc *drm_crtc; 965 struct dpu_crtc_state *cstate; 966 struct dpu_global_state *global_state; 967 struct msm_display_topology topology; 968 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 969 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 970 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 971 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; 972 int num_lm, num_ctl, num_pp, num_dspp; 973 int i, j; 974 975 if (!drm_enc) { 976 DPU_ERROR("invalid encoder\n"); 977 return; 978 } 979 980 dpu_enc = to_dpu_encoder_virt(drm_enc); 981 DPU_DEBUG_ENC(dpu_enc, "\n"); 982 983 priv = drm_enc->dev->dev_private; 984 dpu_kms = to_dpu_kms(priv->kms); 985 connector_list = &dpu_kms->dev->mode_config.connector_list; 986 987 global_state = dpu_kms_get_existing_global_state(dpu_kms); 988 if (IS_ERR_OR_NULL(global_state)) { 989 DPU_ERROR("Failed to get global state"); 990 return; 991 } 992 993 trace_dpu_enc_mode_set(DRMID(drm_enc)); 994 995 list_for_each_entry(conn_iter, connector_list, head) 996 if (conn_iter->encoder == drm_enc) 997 conn = conn_iter; 998 999 if (!conn) { 1000 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); 1001 return; 1002 } else if (!conn->state) { 1003 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); 1004 return; 1005 } 1006 1007 drm_for_each_crtc(drm_crtc, drm_enc->dev) 1008 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc)) 1009 break; 1010 1011 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 1012 1013 /* Query resource that have been reserved in atomic check step. */ 1014 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1015 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1016 ARRAY_SIZE(hw_pp)); 1017 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1018 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1019 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1020 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1021 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1022 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, 1023 ARRAY_SIZE(hw_dspp)); 1024 1025 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1026 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1027 : NULL; 1028 1029 cstate = to_dpu_crtc_state(drm_crtc->state); 1030 1031 for (i = 0; i < num_lm; i++) { 1032 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1033 1034 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1035 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1036 cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); 1037 } 1038 1039 cstate->num_mixers = num_lm; 1040 1041 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1042 int num_blk; 1043 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; 1044 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1045 1046 if (!dpu_enc->hw_pp[i]) { 1047 DPU_ERROR_ENC(dpu_enc, 1048 "no pp block assigned at idx: %d\n", i); 1049 return; 1050 } 1051 1052 if (!hw_ctl[i]) { 1053 DPU_ERROR_ENC(dpu_enc, 1054 "no ctl block assigned at idx: %d\n", i); 1055 return; 1056 } 1057 1058 phys->hw_pp = dpu_enc->hw_pp[i]; 1059 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1060 1061 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm, 1062 global_state, drm_enc->base.id, DPU_HW_BLK_INTF, 1063 hw_blk, ARRAY_SIZE(hw_blk)); 1064 for (j = 0; j < num_blk; j++) { 1065 struct dpu_hw_intf *hw_intf; 1066 1067 hw_intf = to_dpu_hw_intf(hw_blk[i]); 1068 if (hw_intf->idx == phys->intf_idx) 1069 phys->hw_intf = hw_intf; 1070 } 1071 1072 if (!phys->hw_intf) { 1073 DPU_ERROR_ENC(dpu_enc, 1074 "no intf block assigned at idx: %d\n", i); 1075 return; 1076 } 1077 1078 phys->connector = conn->state->connector; 1079 if (phys->ops.mode_set) 1080 phys->ops.mode_set(phys, mode, adj_mode); 1081 } 1082 } 1083 1084 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1085 { 1086 struct dpu_encoder_virt *dpu_enc = NULL; 1087 struct msm_drm_private *priv; 1088 struct dpu_kms *dpu_kms; 1089 1090 if (!drm_enc || !drm_enc->dev) { 1091 DPU_ERROR("invalid parameters\n"); 1092 return; 1093 } 1094 1095 priv = drm_enc->dev->dev_private; 1096 dpu_kms = to_dpu_kms(priv->kms); 1097 1098 dpu_enc = to_dpu_encoder_virt(drm_enc); 1099 if (!dpu_enc || !dpu_enc->cur_master) { 1100 DPU_ERROR("invalid dpu encoder/master\n"); 1101 return; 1102 } 1103 1104 if (dpu_enc->cur_master->hw_mdptop && 1105 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) 1106 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( 1107 dpu_enc->cur_master->hw_mdptop, 1108 dpu_kms->catalog); 1109 1110 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1111 } 1112 1113 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1114 { 1115 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1116 1117 mutex_lock(&dpu_enc->enc_lock); 1118 1119 if (!dpu_enc->enabled) 1120 goto out; 1121 1122 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1123 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1124 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1125 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1126 1127 _dpu_encoder_virt_enable_helper(drm_enc); 1128 1129 out: 1130 mutex_unlock(&dpu_enc->enc_lock); 1131 } 1132 1133 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1134 { 1135 struct dpu_encoder_virt *dpu_enc = NULL; 1136 int ret = 0; 1137 struct drm_display_mode *cur_mode = NULL; 1138 1139 if (!drm_enc) { 1140 DPU_ERROR("invalid encoder\n"); 1141 return; 1142 } 1143 dpu_enc = to_dpu_encoder_virt(drm_enc); 1144 1145 mutex_lock(&dpu_enc->enc_lock); 1146 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1147 1148 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1149 cur_mode->vdisplay); 1150 1151 /* always enable slave encoder before master */ 1152 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1153 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1154 1155 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1156 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1157 1158 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1159 if (ret) { 1160 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1161 ret); 1162 goto out; 1163 } 1164 1165 _dpu_encoder_virt_enable_helper(drm_enc); 1166 1167 dpu_enc->enabled = true; 1168 1169 out: 1170 mutex_unlock(&dpu_enc->enc_lock); 1171 } 1172 1173 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1174 { 1175 struct dpu_encoder_virt *dpu_enc = NULL; 1176 struct msm_drm_private *priv; 1177 struct dpu_kms *dpu_kms; 1178 struct dpu_global_state *global_state; 1179 int i = 0; 1180 1181 if (!drm_enc) { 1182 DPU_ERROR("invalid encoder\n"); 1183 return; 1184 } else if (!drm_enc->dev) { 1185 DPU_ERROR("invalid dev\n"); 1186 return; 1187 } 1188 1189 dpu_enc = to_dpu_encoder_virt(drm_enc); 1190 DPU_DEBUG_ENC(dpu_enc, "\n"); 1191 1192 mutex_lock(&dpu_enc->enc_lock); 1193 dpu_enc->enabled = false; 1194 1195 priv = drm_enc->dev->dev_private; 1196 dpu_kms = to_dpu_kms(priv->kms); 1197 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1198 1199 trace_dpu_enc_disable(DRMID(drm_enc)); 1200 1201 /* wait for idle */ 1202 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1203 1204 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1205 1206 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1207 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1208 1209 if (phys->ops.disable) 1210 phys->ops.disable(phys); 1211 } 1212 1213 /* after phys waits for frame-done, should be no more frames pending */ 1214 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1215 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1216 del_timer_sync(&dpu_enc->frame_done_timer); 1217 } 1218 1219 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1220 1221 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1222 dpu_enc->phys_encs[i]->connector = NULL; 1223 } 1224 1225 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1226 1227 dpu_rm_release(global_state, drm_enc); 1228 1229 mutex_unlock(&dpu_enc->enc_lock); 1230 } 1231 1232 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1233 enum dpu_intf_type type, u32 controller_id) 1234 { 1235 int i = 0; 1236 1237 for (i = 0; i < catalog->intf_count; i++) { 1238 if (catalog->intf[i].type == type 1239 && catalog->intf[i].controller_id == controller_id) { 1240 return catalog->intf[i].id; 1241 } 1242 } 1243 1244 return INTF_MAX; 1245 } 1246 1247 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1248 struct dpu_encoder_phys *phy_enc) 1249 { 1250 struct dpu_encoder_virt *dpu_enc = NULL; 1251 unsigned long lock_flags; 1252 1253 if (!drm_enc || !phy_enc) 1254 return; 1255 1256 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1257 dpu_enc = to_dpu_encoder_virt(drm_enc); 1258 1259 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1260 if (dpu_enc->crtc) 1261 dpu_crtc_vblank_callback(dpu_enc->crtc); 1262 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1263 1264 atomic_inc(&phy_enc->vsync_cnt); 1265 DPU_ATRACE_END("encoder_vblank_callback"); 1266 } 1267 1268 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1269 struct dpu_encoder_phys *phy_enc) 1270 { 1271 if (!phy_enc) 1272 return; 1273 1274 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1275 atomic_inc(&phy_enc->underrun_cnt); 1276 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1277 atomic_read(&phy_enc->underrun_cnt)); 1278 DPU_ATRACE_END("encoder_underrun_callback"); 1279 } 1280 1281 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1282 { 1283 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1284 unsigned long lock_flags; 1285 1286 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1287 /* crtc should always be cleared before re-assigning */ 1288 WARN_ON(crtc && dpu_enc->crtc); 1289 dpu_enc->crtc = crtc; 1290 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1291 } 1292 1293 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1294 struct drm_crtc *crtc, bool enable) 1295 { 1296 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1297 unsigned long lock_flags; 1298 int i; 1299 1300 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1301 1302 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1303 if (dpu_enc->crtc != crtc) { 1304 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1305 return; 1306 } 1307 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1308 1309 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1310 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1311 1312 if (phys->ops.control_vblank_irq) 1313 phys->ops.control_vblank_irq(phys, enable); 1314 } 1315 } 1316 1317 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1318 void (*frame_event_cb)(void *, u32 event), 1319 void *frame_event_cb_data) 1320 { 1321 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1322 unsigned long lock_flags; 1323 bool enable; 1324 1325 enable = frame_event_cb ? true : false; 1326 1327 if (!drm_enc) { 1328 DPU_ERROR("invalid encoder\n"); 1329 return; 1330 } 1331 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1332 1333 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1334 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1335 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1336 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1337 } 1338 1339 static void dpu_encoder_frame_done_callback( 1340 struct drm_encoder *drm_enc, 1341 struct dpu_encoder_phys *ready_phys, u32 event) 1342 { 1343 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1344 unsigned int i; 1345 1346 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1347 | DPU_ENCODER_FRAME_EVENT_ERROR 1348 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1349 1350 if (!dpu_enc->frame_busy_mask[0]) { 1351 /** 1352 * suppress frame_done without waiter, 1353 * likely autorefresh 1354 */ 1355 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1356 event, ready_phys->intf_idx); 1357 return; 1358 } 1359 1360 /* One of the physical encoders has become idle */ 1361 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1362 if (dpu_enc->phys_encs[i] == ready_phys) { 1363 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1364 dpu_enc->frame_busy_mask[0]); 1365 clear_bit(i, dpu_enc->frame_busy_mask); 1366 } 1367 } 1368 1369 if (!dpu_enc->frame_busy_mask[0]) { 1370 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1371 del_timer(&dpu_enc->frame_done_timer); 1372 1373 dpu_encoder_resource_control(drm_enc, 1374 DPU_ENC_RC_EVENT_FRAME_DONE); 1375 1376 if (dpu_enc->crtc_frame_event_cb) 1377 dpu_enc->crtc_frame_event_cb( 1378 dpu_enc->crtc_frame_event_cb_data, 1379 event); 1380 } 1381 } else { 1382 if (dpu_enc->crtc_frame_event_cb) 1383 dpu_enc->crtc_frame_event_cb( 1384 dpu_enc->crtc_frame_event_cb_data, event); 1385 } 1386 } 1387 1388 static void dpu_encoder_off_work(struct work_struct *work) 1389 { 1390 struct dpu_encoder_virt *dpu_enc = container_of(work, 1391 struct dpu_encoder_virt, delayed_off_work.work); 1392 1393 if (!dpu_enc) { 1394 DPU_ERROR("invalid dpu encoder\n"); 1395 return; 1396 } 1397 1398 dpu_encoder_resource_control(&dpu_enc->base, 1399 DPU_ENC_RC_EVENT_ENTER_IDLE); 1400 1401 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1402 DPU_ENCODER_FRAME_EVENT_IDLE); 1403 } 1404 1405 /** 1406 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1407 * drm_enc: Pointer to drm encoder structure 1408 * phys: Pointer to physical encoder structure 1409 * extra_flush_bits: Additional bit mask to include in flush trigger 1410 */ 1411 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1412 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1413 { 1414 struct dpu_hw_ctl *ctl; 1415 int pending_kickoff_cnt; 1416 u32 ret = UINT_MAX; 1417 1418 if (!phys->hw_pp) { 1419 DPU_ERROR("invalid pingpong hw\n"); 1420 return; 1421 } 1422 1423 ctl = phys->hw_ctl; 1424 if (!ctl->ops.trigger_flush) { 1425 DPU_ERROR("missing trigger cb\n"); 1426 return; 1427 } 1428 1429 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1430 1431 if (extra_flush_bits && ctl->ops.update_pending_flush) 1432 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1433 1434 ctl->ops.trigger_flush(ctl); 1435 1436 if (ctl->ops.get_pending_flush) 1437 ret = ctl->ops.get_pending_flush(ctl); 1438 1439 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1440 pending_kickoff_cnt, ctl->idx, 1441 extra_flush_bits, ret); 1442 } 1443 1444 /** 1445 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1446 * phys: Pointer to physical encoder structure 1447 */ 1448 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1449 { 1450 if (!phys) { 1451 DPU_ERROR("invalid argument(s)\n"); 1452 return; 1453 } 1454 1455 if (!phys->hw_pp) { 1456 DPU_ERROR("invalid pingpong hw\n"); 1457 return; 1458 } 1459 1460 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1461 phys->ops.trigger_start(phys); 1462 } 1463 1464 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1465 { 1466 struct dpu_hw_ctl *ctl; 1467 1468 ctl = phys_enc->hw_ctl; 1469 if (ctl->ops.trigger_start) { 1470 ctl->ops.trigger_start(ctl); 1471 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1472 } 1473 } 1474 1475 static int dpu_encoder_helper_wait_event_timeout( 1476 int32_t drm_id, 1477 int32_t hw_id, 1478 struct dpu_encoder_wait_info *info) 1479 { 1480 int rc = 0; 1481 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1482 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1483 s64 time; 1484 1485 do { 1486 rc = wait_event_timeout(*(info->wq), 1487 atomic_read(info->atomic_cnt) == 0, jiffies); 1488 time = ktime_to_ms(ktime_get()); 1489 1490 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, 1491 expected_time, 1492 atomic_read(info->atomic_cnt)); 1493 /* If we timed out, counter is valid and time is less, wait again */ 1494 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1495 (time < expected_time)); 1496 1497 return rc; 1498 } 1499 1500 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1501 { 1502 struct dpu_encoder_virt *dpu_enc; 1503 struct dpu_hw_ctl *ctl; 1504 int rc; 1505 1506 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1507 ctl = phys_enc->hw_ctl; 1508 1509 if (!ctl->ops.reset) 1510 return; 1511 1512 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), 1513 ctl->idx); 1514 1515 rc = ctl->ops.reset(ctl); 1516 if (rc) 1517 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1518 1519 phys_enc->enable_state = DPU_ENC_ENABLED; 1520 } 1521 1522 /** 1523 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1524 * Iterate through the physical encoders and perform consolidated flush 1525 * and/or control start triggering as needed. This is done in the virtual 1526 * encoder rather than the individual physical ones in order to handle 1527 * use cases that require visibility into multiple physical encoders at 1528 * a time. 1529 * dpu_enc: Pointer to virtual encoder structure 1530 */ 1531 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1532 { 1533 struct dpu_hw_ctl *ctl; 1534 uint32_t i, pending_flush; 1535 unsigned long lock_flags; 1536 1537 pending_flush = 0x0; 1538 1539 /* update pending counts and trigger kickoff ctl flush atomically */ 1540 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1541 1542 /* don't perform flush/start operations for slave encoders */ 1543 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1544 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1545 1546 if (phys->enable_state == DPU_ENC_DISABLED) 1547 continue; 1548 1549 ctl = phys->hw_ctl; 1550 1551 /* 1552 * This is cleared in frame_done worker, which isn't invoked 1553 * for async commits. So don't set this for async, since it'll 1554 * roll over to the next commit. 1555 */ 1556 if (phys->split_role != ENC_ROLE_SLAVE) 1557 set_bit(i, dpu_enc->frame_busy_mask); 1558 1559 if (!phys->ops.needs_single_flush || 1560 !phys->ops.needs_single_flush(phys)) 1561 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1562 else if (ctl->ops.get_pending_flush) 1563 pending_flush |= ctl->ops.get_pending_flush(ctl); 1564 } 1565 1566 /* for split flush, combine pending flush masks and send to master */ 1567 if (pending_flush && dpu_enc->cur_master) { 1568 _dpu_encoder_trigger_flush( 1569 &dpu_enc->base, 1570 dpu_enc->cur_master, 1571 pending_flush); 1572 } 1573 1574 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1575 1576 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1577 } 1578 1579 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1580 { 1581 struct dpu_encoder_virt *dpu_enc; 1582 struct dpu_encoder_phys *phys; 1583 unsigned int i; 1584 struct dpu_hw_ctl *ctl; 1585 struct msm_display_info *disp_info; 1586 1587 if (!drm_enc) { 1588 DPU_ERROR("invalid encoder\n"); 1589 return; 1590 } 1591 dpu_enc = to_dpu_encoder_virt(drm_enc); 1592 disp_info = &dpu_enc->disp_info; 1593 1594 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1595 phys = dpu_enc->phys_encs[i]; 1596 1597 ctl = phys->hw_ctl; 1598 if (ctl->ops.clear_pending_flush) 1599 ctl->ops.clear_pending_flush(ctl); 1600 1601 /* update only for command mode primary ctl */ 1602 if ((phys == dpu_enc->cur_master) && 1603 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1604 && ctl->ops.trigger_pending) 1605 ctl->ops.trigger_pending(ctl); 1606 } 1607 } 1608 1609 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1610 struct drm_display_mode *mode) 1611 { 1612 u64 pclk_rate; 1613 u32 pclk_period; 1614 u32 line_time; 1615 1616 /* 1617 * For linetime calculation, only operate on master encoder. 1618 */ 1619 if (!dpu_enc->cur_master) 1620 return 0; 1621 1622 if (!dpu_enc->cur_master->ops.get_line_count) { 1623 DPU_ERROR("get_line_count function not defined\n"); 1624 return 0; 1625 } 1626 1627 pclk_rate = mode->clock; /* pixel clock in kHz */ 1628 if (pclk_rate == 0) { 1629 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1630 return 0; 1631 } 1632 1633 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1634 if (pclk_period == 0) { 1635 DPU_ERROR("pclk period is 0\n"); 1636 return 0; 1637 } 1638 1639 /* 1640 * Line time calculation based on Pixel clock and HTOTAL. 1641 * Final unit is in ns. 1642 */ 1643 line_time = (pclk_period * mode->htotal) / 1000; 1644 if (line_time == 0) { 1645 DPU_ERROR("line time calculation is 0\n"); 1646 return 0; 1647 } 1648 1649 DPU_DEBUG_ENC(dpu_enc, 1650 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1651 pclk_rate, pclk_period, line_time); 1652 1653 return line_time; 1654 } 1655 1656 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1657 { 1658 struct drm_display_mode *mode; 1659 struct dpu_encoder_virt *dpu_enc; 1660 u32 cur_line; 1661 u32 line_time; 1662 u32 vtotal, time_to_vsync; 1663 ktime_t cur_time; 1664 1665 dpu_enc = to_dpu_encoder_virt(drm_enc); 1666 1667 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1668 DPU_ERROR("crtc/crtc state object is NULL\n"); 1669 return -EINVAL; 1670 } 1671 mode = &drm_enc->crtc->state->adjusted_mode; 1672 1673 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1674 if (!line_time) 1675 return -EINVAL; 1676 1677 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1678 1679 vtotal = mode->vtotal; 1680 if (cur_line >= vtotal) 1681 time_to_vsync = line_time * vtotal; 1682 else 1683 time_to_vsync = line_time * (vtotal - cur_line); 1684 1685 if (time_to_vsync == 0) { 1686 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1687 vtotal); 1688 return -EINVAL; 1689 } 1690 1691 cur_time = ktime_get(); 1692 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1693 1694 DPU_DEBUG_ENC(dpu_enc, 1695 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1696 cur_line, vtotal, time_to_vsync, 1697 ktime_to_ms(cur_time), 1698 ktime_to_ms(*wakeup_time)); 1699 return 0; 1700 } 1701 1702 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1703 { 1704 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1705 vsync_event_timer); 1706 struct drm_encoder *drm_enc = &dpu_enc->base; 1707 struct msm_drm_private *priv; 1708 struct msm_drm_thread *event_thread; 1709 1710 if (!drm_enc->dev || !drm_enc->crtc) { 1711 DPU_ERROR("invalid parameters\n"); 1712 return; 1713 } 1714 1715 priv = drm_enc->dev->dev_private; 1716 1717 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1718 DPU_ERROR("invalid crtc index\n"); 1719 return; 1720 } 1721 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1722 if (!event_thread) { 1723 DPU_ERROR("event_thread not found for crtc:%d\n", 1724 drm_enc->crtc->index); 1725 return; 1726 } 1727 1728 del_timer(&dpu_enc->vsync_event_timer); 1729 } 1730 1731 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1732 { 1733 struct dpu_encoder_virt *dpu_enc = container_of(work, 1734 struct dpu_encoder_virt, vsync_event_work); 1735 ktime_t wakeup_time; 1736 1737 if (!dpu_enc) { 1738 DPU_ERROR("invalid dpu encoder\n"); 1739 return; 1740 } 1741 1742 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) 1743 return; 1744 1745 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1746 mod_timer(&dpu_enc->vsync_event_timer, 1747 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1748 } 1749 1750 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1751 { 1752 struct dpu_encoder_virt *dpu_enc; 1753 struct dpu_encoder_phys *phys; 1754 bool needs_hw_reset = false; 1755 unsigned int i; 1756 1757 dpu_enc = to_dpu_encoder_virt(drm_enc); 1758 1759 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1760 1761 /* prepare for next kickoff, may include waiting on previous kickoff */ 1762 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1763 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1764 phys = dpu_enc->phys_encs[i]; 1765 if (phys->ops.prepare_for_kickoff) 1766 phys->ops.prepare_for_kickoff(phys); 1767 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1768 needs_hw_reset = true; 1769 } 1770 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1771 1772 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1773 1774 /* if any phys needs reset, reset all phys, in-order */ 1775 if (needs_hw_reset) { 1776 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1777 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1778 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1779 } 1780 } 1781 } 1782 1783 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1784 { 1785 struct dpu_encoder_virt *dpu_enc; 1786 struct dpu_encoder_phys *phys; 1787 ktime_t wakeup_time; 1788 unsigned long timeout_ms; 1789 unsigned int i; 1790 1791 DPU_ATRACE_BEGIN("encoder_kickoff"); 1792 dpu_enc = to_dpu_encoder_virt(drm_enc); 1793 1794 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1795 1796 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1797 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1798 1799 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1800 mod_timer(&dpu_enc->frame_done_timer, 1801 jiffies + msecs_to_jiffies(timeout_ms)); 1802 1803 /* All phys encs are ready to go, trigger the kickoff */ 1804 _dpu_encoder_kickoff_phys(dpu_enc); 1805 1806 /* allow phys encs to handle any post-kickoff business */ 1807 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1808 phys = dpu_enc->phys_encs[i]; 1809 if (phys->ops.handle_post_kickoff) 1810 phys->ops.handle_post_kickoff(phys); 1811 } 1812 1813 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1814 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { 1815 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1816 ktime_to_ms(wakeup_time)); 1817 mod_timer(&dpu_enc->vsync_event_timer, 1818 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1819 } 1820 1821 DPU_ATRACE_END("encoder_kickoff"); 1822 } 1823 1824 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1825 { 1826 struct dpu_encoder_virt *dpu_enc; 1827 struct dpu_encoder_phys *phys; 1828 int i; 1829 1830 if (!drm_enc) { 1831 DPU_ERROR("invalid encoder\n"); 1832 return; 1833 } 1834 dpu_enc = to_dpu_encoder_virt(drm_enc); 1835 1836 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1837 phys = dpu_enc->phys_encs[i]; 1838 if (phys->ops.prepare_commit) 1839 phys->ops.prepare_commit(phys); 1840 } 1841 } 1842 1843 #ifdef CONFIG_DEBUG_FS 1844 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1845 { 1846 struct dpu_encoder_virt *dpu_enc = s->private; 1847 int i; 1848 1849 mutex_lock(&dpu_enc->enc_lock); 1850 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1851 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1852 1853 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1854 phys->intf_idx - INTF_0, 1855 atomic_read(&phys->vsync_cnt), 1856 atomic_read(&phys->underrun_cnt)); 1857 1858 switch (phys->intf_mode) { 1859 case INTF_MODE_VIDEO: 1860 seq_puts(s, "mode: video\n"); 1861 break; 1862 case INTF_MODE_CMD: 1863 seq_puts(s, "mode: command\n"); 1864 break; 1865 default: 1866 seq_puts(s, "mode: ???\n"); 1867 break; 1868 } 1869 } 1870 mutex_unlock(&dpu_enc->enc_lock); 1871 1872 return 0; 1873 } 1874 1875 static int _dpu_encoder_debugfs_status_open(struct inode *inode, 1876 struct file *file) 1877 { 1878 return single_open(file, _dpu_encoder_status_show, inode->i_private); 1879 } 1880 1881 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1882 { 1883 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1884 int i; 1885 1886 static const struct file_operations debugfs_status_fops = { 1887 .open = _dpu_encoder_debugfs_status_open, 1888 .read = seq_read, 1889 .llseek = seq_lseek, 1890 .release = single_release, 1891 }; 1892 1893 char name[DPU_NAME_SIZE]; 1894 1895 if (!drm_enc->dev) { 1896 DPU_ERROR("invalid encoder or kms\n"); 1897 return -EINVAL; 1898 } 1899 1900 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1901 1902 /* create overall sub-directory for the encoder */ 1903 dpu_enc->debugfs_root = debugfs_create_dir(name, 1904 drm_enc->dev->primary->debugfs_root); 1905 1906 /* don't error check these */ 1907 debugfs_create_file("status", 0600, 1908 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); 1909 1910 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1911 if (dpu_enc->phys_encs[i]->ops.late_register) 1912 dpu_enc->phys_encs[i]->ops.late_register( 1913 dpu_enc->phys_encs[i], 1914 dpu_enc->debugfs_root); 1915 1916 return 0; 1917 } 1918 #else 1919 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1920 { 1921 return 0; 1922 } 1923 #endif 1924 1925 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1926 { 1927 return _dpu_encoder_init_debugfs(encoder); 1928 } 1929 1930 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1931 { 1932 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1933 1934 debugfs_remove_recursive(dpu_enc->debugfs_root); 1935 } 1936 1937 static int dpu_encoder_virt_add_phys_encs( 1938 u32 display_caps, 1939 struct dpu_encoder_virt *dpu_enc, 1940 struct dpu_enc_phys_init_params *params) 1941 { 1942 struct dpu_encoder_phys *enc = NULL; 1943 1944 DPU_DEBUG_ENC(dpu_enc, "\n"); 1945 1946 /* 1947 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1948 * in this function, check up-front. 1949 */ 1950 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1951 ARRAY_SIZE(dpu_enc->phys_encs)) { 1952 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1953 dpu_enc->num_phys_encs); 1954 return -EINVAL; 1955 } 1956 1957 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1958 enc = dpu_encoder_phys_vid_init(params); 1959 1960 if (IS_ERR_OR_NULL(enc)) { 1961 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1962 PTR_ERR(enc)); 1963 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1964 } 1965 1966 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1967 ++dpu_enc->num_phys_encs; 1968 } 1969 1970 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 1971 enc = dpu_encoder_phys_cmd_init(params); 1972 1973 if (IS_ERR_OR_NULL(enc)) { 1974 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 1975 PTR_ERR(enc)); 1976 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1977 } 1978 1979 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1980 ++dpu_enc->num_phys_encs; 1981 } 1982 1983 if (params->split_role == ENC_ROLE_SLAVE) 1984 dpu_enc->cur_slave = enc; 1985 else 1986 dpu_enc->cur_master = enc; 1987 1988 return 0; 1989 } 1990 1991 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 1992 .handle_vblank_virt = dpu_encoder_vblank_callback, 1993 .handle_underrun_virt = dpu_encoder_underrun_callback, 1994 .handle_frame_done = dpu_encoder_frame_done_callback, 1995 }; 1996 1997 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 1998 struct dpu_kms *dpu_kms, 1999 struct msm_display_info *disp_info) 2000 { 2001 int ret = 0; 2002 int i = 0; 2003 enum dpu_intf_type intf_type; 2004 struct dpu_enc_phys_init_params phys_params; 2005 2006 if (!dpu_enc) { 2007 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 2008 return -EINVAL; 2009 } 2010 2011 dpu_enc->cur_master = NULL; 2012 2013 memset(&phys_params, 0, sizeof(phys_params)); 2014 phys_params.dpu_kms = dpu_kms; 2015 phys_params.parent = &dpu_enc->base; 2016 phys_params.parent_ops = &dpu_encoder_parent_ops; 2017 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2018 2019 DPU_DEBUG("\n"); 2020 2021 switch (disp_info->intf_type) { 2022 case DRM_MODE_ENCODER_DSI: 2023 intf_type = INTF_DSI; 2024 break; 2025 default: 2026 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); 2027 return -EINVAL; 2028 } 2029 2030 WARN_ON(disp_info->num_of_h_tiles < 1); 2031 2032 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2033 2034 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 2035 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 2036 dpu_enc->idle_pc_supported = 2037 dpu_kms->catalog->caps->has_idle_pc; 2038 2039 mutex_lock(&dpu_enc->enc_lock); 2040 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2041 /* 2042 * Left-most tile is at index 0, content is controller id 2043 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2044 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2045 */ 2046 u32 controller_id = disp_info->h_tile_instance[i]; 2047 2048 if (disp_info->num_of_h_tiles > 1) { 2049 if (i == 0) 2050 phys_params.split_role = ENC_ROLE_MASTER; 2051 else 2052 phys_params.split_role = ENC_ROLE_SLAVE; 2053 } else { 2054 phys_params.split_role = ENC_ROLE_SOLO; 2055 } 2056 2057 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2058 i, controller_id, phys_params.split_role); 2059 2060 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 2061 intf_type, 2062 controller_id); 2063 if (phys_params.intf_idx == INTF_MAX) { 2064 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 2065 intf_type, controller_id); 2066 ret = -EINVAL; 2067 } 2068 2069 if (!ret) { 2070 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 2071 dpu_enc, 2072 &phys_params); 2073 if (ret) 2074 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2075 } 2076 } 2077 2078 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2079 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2080 atomic_set(&phys->vsync_cnt, 0); 2081 atomic_set(&phys->underrun_cnt, 0); 2082 } 2083 mutex_unlock(&dpu_enc->enc_lock); 2084 2085 return ret; 2086 } 2087 2088 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2089 { 2090 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2091 frame_done_timer); 2092 struct drm_encoder *drm_enc = &dpu_enc->base; 2093 u32 event; 2094 2095 if (!drm_enc->dev) { 2096 DPU_ERROR("invalid parameters\n"); 2097 return; 2098 } 2099 2100 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2101 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2102 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2103 return; 2104 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2105 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2106 return; 2107 } 2108 2109 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2110 2111 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2112 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2113 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2114 } 2115 2116 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2117 .mode_set = dpu_encoder_virt_mode_set, 2118 .disable = dpu_encoder_virt_disable, 2119 .enable = dpu_kms_encoder_enable, 2120 .atomic_check = dpu_encoder_virt_atomic_check, 2121 2122 /* This is called by dpu_kms_encoder_enable */ 2123 .commit = dpu_encoder_virt_enable, 2124 }; 2125 2126 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2127 .destroy = dpu_encoder_destroy, 2128 .late_register = dpu_encoder_late_register, 2129 .early_unregister = dpu_encoder_early_unregister, 2130 }; 2131 2132 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2133 struct msm_display_info *disp_info) 2134 { 2135 struct msm_drm_private *priv = dev->dev_private; 2136 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2137 struct drm_encoder *drm_enc = NULL; 2138 struct dpu_encoder_virt *dpu_enc = NULL; 2139 int ret = 0; 2140 2141 dpu_enc = to_dpu_encoder_virt(enc); 2142 2143 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2144 if (ret) 2145 goto fail; 2146 2147 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2148 timer_setup(&dpu_enc->frame_done_timer, 2149 dpu_encoder_frame_done_timeout, 0); 2150 2151 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2152 timer_setup(&dpu_enc->vsync_event_timer, 2153 dpu_encoder_vsync_event_handler, 2154 0); 2155 2156 2157 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2158 dpu_encoder_off_work); 2159 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2160 2161 kthread_init_work(&dpu_enc->vsync_event_work, 2162 dpu_encoder_vsync_event_work_handler); 2163 2164 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2165 2166 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2167 2168 return ret; 2169 2170 fail: 2171 DPU_ERROR("failed to create encoder\n"); 2172 if (drm_enc) 2173 dpu_encoder_destroy(drm_enc); 2174 2175 return ret; 2176 2177 2178 } 2179 2180 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2181 int drm_enc_mode) 2182 { 2183 struct dpu_encoder_virt *dpu_enc = NULL; 2184 int rc = 0; 2185 2186 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2187 if (!dpu_enc) 2188 return ERR_PTR(-ENOMEM); 2189 2190 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2191 drm_enc_mode, NULL); 2192 if (rc) { 2193 devm_kfree(dev->dev, dpu_enc); 2194 return ERR_PTR(rc); 2195 } 2196 2197 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2198 2199 spin_lock_init(&dpu_enc->enc_spinlock); 2200 dpu_enc->enabled = false; 2201 mutex_init(&dpu_enc->enc_lock); 2202 mutex_init(&dpu_enc->rc_lock); 2203 2204 return &dpu_enc->base; 2205 } 2206 2207 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2208 enum msm_event_wait event) 2209 { 2210 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2211 struct dpu_encoder_virt *dpu_enc = NULL; 2212 int i, ret = 0; 2213 2214 if (!drm_enc) { 2215 DPU_ERROR("invalid encoder\n"); 2216 return -EINVAL; 2217 } 2218 dpu_enc = to_dpu_encoder_virt(drm_enc); 2219 DPU_DEBUG_ENC(dpu_enc, "\n"); 2220 2221 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2222 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2223 2224 switch (event) { 2225 case MSM_ENC_COMMIT_DONE: 2226 fn_wait = phys->ops.wait_for_commit_done; 2227 break; 2228 case MSM_ENC_TX_COMPLETE: 2229 fn_wait = phys->ops.wait_for_tx_complete; 2230 break; 2231 case MSM_ENC_VBLANK: 2232 fn_wait = phys->ops.wait_for_vblank; 2233 break; 2234 default: 2235 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2236 event); 2237 return -EINVAL; 2238 } 2239 2240 if (fn_wait) { 2241 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2242 ret = fn_wait(phys); 2243 DPU_ATRACE_END("wait_for_completion_event"); 2244 if (ret) 2245 return ret; 2246 } 2247 } 2248 2249 return ret; 2250 } 2251 2252 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2253 { 2254 struct dpu_encoder_virt *dpu_enc = NULL; 2255 2256 if (!encoder) { 2257 DPU_ERROR("invalid encoder\n"); 2258 return INTF_MODE_NONE; 2259 } 2260 dpu_enc = to_dpu_encoder_virt(encoder); 2261 2262 if (dpu_enc->cur_master) 2263 return dpu_enc->cur_master->intf_mode; 2264 2265 if (dpu_enc->num_phys_encs) 2266 return dpu_enc->phys_encs[0]->intf_mode; 2267 2268 return INTF_MODE_NONE; 2269 } 2270