1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 #include <linux/debugfs.h> 10 #include <linux/kthread.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_probe_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_hwio.h" 20 #include "dpu_hw_catalog.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_ctl.h" 23 #include "dpu_formats.h" 24 #include "dpu_encoder_phys.h" 25 #include "dpu_crtc.h" 26 #include "dpu_trace.h" 27 #include "dpu_core_irq.h" 28 29 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ 30 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 33 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ 36 (p) ? (p)->parent->base.id : -1, \ 37 (p) ? (p)->intf_idx - INTF_0 : -1, \ 38 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 39 ##__VA_ARGS__) 40 41 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 42 (p) ? (p)->parent->base.id : -1, \ 43 (p) ? (p)->intf_idx - INTF_0 : -1, \ 44 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 45 ##__VA_ARGS__) 46 47 /* 48 * Two to anticipate panels that can do cmd/vid dynamic switching 49 * plan is to create all possible physical encoder types, and switch between 50 * them at runtime 51 */ 52 #define NUM_PHYS_ENCODER_TYPES 2 53 54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 56 57 #define MAX_CHANNELS_PER_ENC 2 58 59 #define IDLE_SHORT_TIMEOUT 1 60 61 #define MAX_HDISPLAY_SPLIT 1080 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @bus_scaling_client: Client handle to the bus scaling interface 129 * @enabled: True if the encoder is active, protected by enc_lock 130 * @num_phys_encs: Actual number of physical encoders contained. 131 * @phys_encs: Container of physical encoders managed. 132 * @cur_master: Pointer to the current master in this mode. Optimization 133 * Only valid after enable. Cleared as disable. 134 * @hw_pp Handle to the pingpong blocks used for the display. No. 135 * pingpong blocks can be different than num_phys_encs. 136 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped 137 * for partial update right-only cases, such as pingpong 138 * split where virtual pingpong does not generate IRQs 139 * @crtc: Pointer to the currently assigned crtc. Normally you 140 * would use crtc->state->encoder_mask to determine the 141 * link between encoder/crtc. However in this case we need 142 * to track crtc in the disable() hook which is called 143 * _after_ encoder_mask is cleared. 144 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 145 * all CTL paths 146 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 147 * @debugfs_root: Debug file system root file node 148 * @enc_lock: Lock around physical encoder 149 * create/destroy/enable/disable 150 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 151 * busy processing current command. 152 * Bit0 = phys_encs[0] etc. 153 * @crtc_frame_event_cb: callback handler for frame event 154 * @crtc_frame_event_cb_data: callback handler private data 155 * @frame_done_timeout_ms: frame done timeout in ms 156 * @frame_done_timer: watchdog timer for frame done event 157 * @vsync_event_timer: vsync timer 158 * @disp_info: local copy of msm_display_info struct 159 * @idle_pc_supported: indicate if idle power collaps is supported 160 * @rc_lock: resource control mutex lock to protect 161 * virt encoder over various state changes 162 * @rc_state: resource controller state 163 * @delayed_off_work: delayed worker to schedule disabling of 164 * clks and resources after IDLE_TIMEOUT time. 165 * @vsync_event_work: worker to handle vsync event for autorefresh 166 * @topology: topology of the display 167 * @idle_timeout: idle timeout duration in milliseconds 168 */ 169 struct dpu_encoder_virt { 170 struct drm_encoder base; 171 spinlock_t enc_spinlock; 172 uint32_t bus_scaling_client; 173 174 bool enabled; 175 176 unsigned int num_phys_encs; 177 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 178 struct dpu_encoder_phys *cur_master; 179 struct dpu_encoder_phys *cur_slave; 180 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 181 182 bool intfs_swapped; 183 184 struct drm_crtc *crtc; 185 186 struct dentry *debugfs_root; 187 struct mutex enc_lock; 188 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 189 void (*crtc_frame_event_cb)(void *, u32 event); 190 void *crtc_frame_event_cb_data; 191 192 atomic_t frame_done_timeout_ms; 193 struct timer_list frame_done_timer; 194 struct timer_list vsync_event_timer; 195 196 struct msm_display_info disp_info; 197 198 bool idle_pc_supported; 199 struct mutex rc_lock; 200 enum dpu_enc_rc_states rc_state; 201 struct delayed_work delayed_off_work; 202 struct kthread_work vsync_event_work; 203 struct msm_display_topology topology; 204 205 u32 idle_timeout; 206 }; 207 208 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 209 210 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 211 enum dpu_intr_idx intr_idx) 212 { 213 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 214 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 215 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 216 217 if (phys_enc->parent_ops->handle_frame_done) 218 phys_enc->parent_ops->handle_frame_done( 219 phys_enc->parent, phys_enc, 220 DPU_ENCODER_FRAME_EVENT_ERROR); 221 } 222 223 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 224 int32_t hw_id, struct dpu_encoder_wait_info *info); 225 226 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 227 enum dpu_intr_idx intr_idx, 228 struct dpu_encoder_wait_info *wait_info) 229 { 230 struct dpu_encoder_irq *irq; 231 u32 irq_status; 232 int ret; 233 234 if (!wait_info || intr_idx >= INTR_IDX_MAX) { 235 DPU_ERROR("invalid params\n"); 236 return -EINVAL; 237 } 238 irq = &phys_enc->irq[intr_idx]; 239 240 /* note: do master / slave checking outside */ 241 242 /* return EWOULDBLOCK since we know the wait isn't necessary */ 243 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 244 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", 245 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 246 irq->irq_idx); 247 return -EWOULDBLOCK; 248 } 249 250 if (irq->irq_idx < 0) { 251 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", 252 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 253 irq->name); 254 return 0; 255 } 256 257 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", 258 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 259 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 260 atomic_read(wait_info->atomic_cnt)); 261 262 ret = dpu_encoder_helper_wait_event_timeout( 263 DRMID(phys_enc->parent), 264 irq->hw_idx, 265 wait_info); 266 267 if (ret <= 0) { 268 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 269 irq->irq_idx, true); 270 if (irq_status) { 271 unsigned long flags; 272 273 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " 274 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 275 DRMID(phys_enc->parent), intr_idx, 276 irq->hw_idx, irq->irq_idx, 277 phys_enc->hw_pp->idx - PINGPONG_0, 278 atomic_read(wait_info->atomic_cnt)); 279 local_irq_save(flags); 280 irq->cb.func(phys_enc, irq->irq_idx); 281 local_irq_restore(flags); 282 ret = 0; 283 } else { 284 ret = -ETIMEDOUT; 285 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " 286 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 287 DRMID(phys_enc->parent), intr_idx, 288 irq->hw_idx, irq->irq_idx, 289 phys_enc->hw_pp->idx - PINGPONG_0, 290 atomic_read(wait_info->atomic_cnt)); 291 } 292 } else { 293 ret = 0; 294 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 295 intr_idx, irq->hw_idx, irq->irq_idx, 296 phys_enc->hw_pp->idx - PINGPONG_0, 297 atomic_read(wait_info->atomic_cnt)); 298 } 299 300 return ret; 301 } 302 303 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 304 enum dpu_intr_idx intr_idx) 305 { 306 struct dpu_encoder_irq *irq; 307 int ret = 0; 308 309 if (intr_idx >= INTR_IDX_MAX) { 310 DPU_ERROR("invalid params\n"); 311 return -EINVAL; 312 } 313 irq = &phys_enc->irq[intr_idx]; 314 315 if (irq->irq_idx >= 0) { 316 DPU_DEBUG_PHYS(phys_enc, 317 "skipping already registered irq %s type %d\n", 318 irq->name, irq->intr_type); 319 return 0; 320 } 321 322 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, 323 irq->intr_type, irq->hw_idx); 324 if (irq->irq_idx < 0) { 325 DPU_ERROR_PHYS(phys_enc, 326 "failed to lookup IRQ index for %s type:%d\n", 327 irq->name, irq->intr_type); 328 return -EINVAL; 329 } 330 331 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 332 &irq->cb); 333 if (ret) { 334 DPU_ERROR_PHYS(phys_enc, 335 "failed to register IRQ callback for %s\n", 336 irq->name); 337 irq->irq_idx = -EINVAL; 338 return ret; 339 } 340 341 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); 342 if (ret) { 343 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", 344 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 345 irq->irq_idx); 346 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 347 irq->irq_idx, &irq->cb); 348 irq->irq_idx = -EINVAL; 349 return ret; 350 } 351 352 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 353 irq->hw_idx, irq->irq_idx); 354 355 return ret; 356 } 357 358 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 359 enum dpu_intr_idx intr_idx) 360 { 361 struct dpu_encoder_irq *irq; 362 int ret; 363 364 irq = &phys_enc->irq[intr_idx]; 365 366 /* silently skip irqs that weren't registered */ 367 if (irq->irq_idx < 0) { 368 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", 369 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 370 irq->irq_idx); 371 return 0; 372 } 373 374 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); 375 if (ret) { 376 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", 377 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 378 irq->irq_idx, ret); 379 } 380 381 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 382 &irq->cb); 383 if (ret) { 384 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", 385 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 386 irq->irq_idx, ret); 387 } 388 389 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 390 irq->hw_idx, irq->irq_idx); 391 392 irq->irq_idx = -EINVAL; 393 394 return 0; 395 } 396 397 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, 398 struct dpu_encoder_hw_resources *hw_res) 399 { 400 struct dpu_encoder_virt *dpu_enc = NULL; 401 int i = 0; 402 403 dpu_enc = to_dpu_encoder_virt(drm_enc); 404 DPU_DEBUG_ENC(dpu_enc, "\n"); 405 406 /* Query resources used by phys encs, expected to be without overlap */ 407 memset(hw_res, 0, sizeof(*hw_res)); 408 409 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 410 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 411 412 if (phys->ops.get_hw_resources) 413 phys->ops.get_hw_resources(phys, hw_res); 414 } 415 } 416 417 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 418 { 419 struct dpu_encoder_virt *dpu_enc = NULL; 420 int i = 0; 421 422 if (!drm_enc) { 423 DPU_ERROR("invalid encoder\n"); 424 return; 425 } 426 427 dpu_enc = to_dpu_encoder_virt(drm_enc); 428 DPU_DEBUG_ENC(dpu_enc, "\n"); 429 430 mutex_lock(&dpu_enc->enc_lock); 431 432 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 433 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 434 435 if (phys->ops.destroy) { 436 phys->ops.destroy(phys); 437 --dpu_enc->num_phys_encs; 438 dpu_enc->phys_encs[i] = NULL; 439 } 440 } 441 442 if (dpu_enc->num_phys_encs) 443 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 444 dpu_enc->num_phys_encs); 445 dpu_enc->num_phys_encs = 0; 446 mutex_unlock(&dpu_enc->enc_lock); 447 448 drm_encoder_cleanup(drm_enc); 449 mutex_destroy(&dpu_enc->enc_lock); 450 } 451 452 void dpu_encoder_helper_split_config( 453 struct dpu_encoder_phys *phys_enc, 454 enum dpu_intf interface) 455 { 456 struct dpu_encoder_virt *dpu_enc; 457 struct split_pipe_cfg cfg = { 0 }; 458 struct dpu_hw_mdp *hw_mdptop; 459 struct msm_display_info *disp_info; 460 461 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 462 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 463 return; 464 } 465 466 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 467 hw_mdptop = phys_enc->hw_mdptop; 468 disp_info = &dpu_enc->disp_info; 469 470 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 471 return; 472 473 /** 474 * disable split modes since encoder will be operating in as the only 475 * encoder, either for the entire use case in the case of, for example, 476 * single DSI, or for this frame in the case of left/right only partial 477 * update. 478 */ 479 if (phys_enc->split_role == ENC_ROLE_SOLO) { 480 if (hw_mdptop->ops.setup_split_pipe) 481 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 482 return; 483 } 484 485 cfg.en = true; 486 cfg.mode = phys_enc->intf_mode; 487 cfg.intf = interface; 488 489 if (cfg.en && phys_enc->ops.needs_single_flush && 490 phys_enc->ops.needs_single_flush(phys_enc)) 491 cfg.split_flush_en = true; 492 493 if (phys_enc->split_role == ENC_ROLE_MASTER) { 494 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 495 496 if (hw_mdptop->ops.setup_split_pipe) 497 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 498 } 499 } 500 501 static void _dpu_encoder_adjust_mode(struct drm_connector *connector, 502 struct drm_display_mode *adj_mode) 503 { 504 struct drm_display_mode *cur_mode; 505 506 if (!connector || !adj_mode) 507 return; 508 509 list_for_each_entry(cur_mode, &connector->modes, head) { 510 if (cur_mode->vdisplay == adj_mode->vdisplay && 511 cur_mode->hdisplay == adj_mode->hdisplay && 512 drm_mode_vrefresh(cur_mode) == drm_mode_vrefresh(adj_mode)) { 513 adj_mode->private_flags |= cur_mode->private_flags; 514 } 515 } 516 } 517 518 static struct msm_display_topology dpu_encoder_get_topology( 519 struct dpu_encoder_virt *dpu_enc, 520 struct dpu_kms *dpu_kms, 521 struct drm_display_mode *mode) 522 { 523 struct msm_display_topology topology; 524 int i, intf_count = 0; 525 526 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 527 if (dpu_enc->phys_encs[i]) 528 intf_count++; 529 530 /* Datapath topology selection 531 * 532 * Dual display 533 * 2 LM, 2 INTF ( Split display using 2 interfaces) 534 * 535 * Single display 536 * 1 LM, 1 INTF 537 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 538 * 539 */ 540 if (intf_count == 2) 541 topology.num_lm = 2; 542 else if (!dpu_kms->catalog->caps->has_3d_merge) 543 topology.num_lm = 1; 544 else 545 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 546 547 topology.num_enc = 0; 548 topology.num_intf = intf_count; 549 550 return topology; 551 } 552 static int dpu_encoder_virt_atomic_check( 553 struct drm_encoder *drm_enc, 554 struct drm_crtc_state *crtc_state, 555 struct drm_connector_state *conn_state) 556 { 557 struct dpu_encoder_virt *dpu_enc; 558 struct msm_drm_private *priv; 559 struct dpu_kms *dpu_kms; 560 const struct drm_display_mode *mode; 561 struct drm_display_mode *adj_mode; 562 struct msm_display_topology topology; 563 struct dpu_global_state *global_state; 564 int i = 0; 565 int ret = 0; 566 567 if (!drm_enc || !crtc_state || !conn_state) { 568 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 569 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 570 return -EINVAL; 571 } 572 573 dpu_enc = to_dpu_encoder_virt(drm_enc); 574 DPU_DEBUG_ENC(dpu_enc, "\n"); 575 576 priv = drm_enc->dev->dev_private; 577 dpu_kms = to_dpu_kms(priv->kms); 578 mode = &crtc_state->mode; 579 adj_mode = &crtc_state->adjusted_mode; 580 global_state = dpu_kms_get_existing_global_state(dpu_kms); 581 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 582 583 /* 584 * display drivers may populate private fields of the drm display mode 585 * structure while registering possible modes of a connector with DRM. 586 * These private fields are not populated back while DRM invokes 587 * the mode_set callbacks. This module retrieves and populates the 588 * private fields of the given mode. 589 */ 590 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode); 591 592 /* perform atomic check on the first physical encoder (master) */ 593 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 594 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 595 596 if (phys->ops.atomic_check) 597 ret = phys->ops.atomic_check(phys, crtc_state, 598 conn_state); 599 else if (phys->ops.mode_fixup) 600 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) 601 ret = -EINVAL; 602 603 if (ret) { 604 DPU_ERROR_ENC(dpu_enc, 605 "mode unsupported, phys idx %d\n", i); 606 break; 607 } 608 } 609 610 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 611 612 /* Reserve dynamic resources now. */ 613 if (!ret) { 614 /* 615 * Avoid reserving resources when mode set is pending. Topology 616 * info may not be available to complete reservation. 617 */ 618 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 619 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 620 drm_enc, crtc_state, topology); 621 } 622 } 623 624 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags, 625 adj_mode->private_flags); 626 627 return ret; 628 } 629 630 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 631 struct msm_display_info *disp_info) 632 { 633 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 634 struct msm_drm_private *priv; 635 struct dpu_kms *dpu_kms; 636 struct dpu_hw_mdp *hw_mdptop; 637 struct drm_encoder *drm_enc; 638 int i; 639 640 if (!dpu_enc || !disp_info) { 641 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 642 dpu_enc != NULL, disp_info != NULL); 643 return; 644 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 645 DPU_ERROR("invalid num phys enc %d/%d\n", 646 dpu_enc->num_phys_encs, 647 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 648 return; 649 } 650 651 drm_enc = &dpu_enc->base; 652 /* this pointers are checked in virt_enable_helper */ 653 priv = drm_enc->dev->dev_private; 654 655 dpu_kms = to_dpu_kms(priv->kms); 656 hw_mdptop = dpu_kms->hw_mdp; 657 if (!hw_mdptop) { 658 DPU_ERROR("invalid mdptop\n"); 659 return; 660 } 661 662 if (hw_mdptop->ops.setup_vsync_source && 663 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 664 for (i = 0; i < dpu_enc->num_phys_encs; i++) 665 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 666 667 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 668 if (disp_info->is_te_using_watchdog_timer) 669 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 670 else 671 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 672 673 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 674 } 675 } 676 677 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 678 { 679 struct dpu_encoder_virt *dpu_enc; 680 int i; 681 682 if (!drm_enc) { 683 DPU_ERROR("invalid encoder\n"); 684 return; 685 } 686 687 dpu_enc = to_dpu_encoder_virt(drm_enc); 688 689 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 690 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 691 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 692 693 if (phys->ops.irq_control) 694 phys->ops.irq_control(phys, enable); 695 } 696 697 } 698 699 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 700 bool enable) 701 { 702 struct msm_drm_private *priv; 703 struct dpu_kms *dpu_kms; 704 struct dpu_encoder_virt *dpu_enc; 705 706 dpu_enc = to_dpu_encoder_virt(drm_enc); 707 priv = drm_enc->dev->dev_private; 708 dpu_kms = to_dpu_kms(priv->kms); 709 710 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 711 712 if (!dpu_enc->cur_master) { 713 DPU_ERROR("encoder master not set\n"); 714 return; 715 } 716 717 if (enable) { 718 /* enable DPU core clks */ 719 pm_runtime_get_sync(&dpu_kms->pdev->dev); 720 721 /* enable all the irq */ 722 _dpu_encoder_irq_control(drm_enc, true); 723 724 } else { 725 /* disable all the irq */ 726 _dpu_encoder_irq_control(drm_enc, false); 727 728 /* disable DPU core clks */ 729 pm_runtime_put_sync(&dpu_kms->pdev->dev); 730 } 731 732 } 733 734 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 735 u32 sw_event) 736 { 737 struct dpu_encoder_virt *dpu_enc; 738 struct msm_drm_private *priv; 739 bool is_vid_mode = false; 740 741 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 742 DPU_ERROR("invalid parameters\n"); 743 return -EINVAL; 744 } 745 dpu_enc = to_dpu_encoder_virt(drm_enc); 746 priv = drm_enc->dev->dev_private; 747 is_vid_mode = dpu_enc->disp_info.capabilities & 748 MSM_DISPLAY_CAP_VID_MODE; 749 750 /* 751 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 752 * events and return early for other events (ie wb display). 753 */ 754 if (!dpu_enc->idle_pc_supported && 755 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 756 sw_event != DPU_ENC_RC_EVENT_STOP && 757 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 758 return 0; 759 760 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 761 dpu_enc->rc_state, "begin"); 762 763 switch (sw_event) { 764 case DPU_ENC_RC_EVENT_KICKOFF: 765 /* cancel delayed off work, if any */ 766 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 767 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 768 sw_event); 769 770 mutex_lock(&dpu_enc->rc_lock); 771 772 /* return if the resource control is already in ON state */ 773 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 774 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", 775 DRMID(drm_enc), sw_event); 776 mutex_unlock(&dpu_enc->rc_lock); 777 return 0; 778 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 779 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 780 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", 781 DRMID(drm_enc), sw_event, 782 dpu_enc->rc_state); 783 mutex_unlock(&dpu_enc->rc_lock); 784 return -EINVAL; 785 } 786 787 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 788 _dpu_encoder_irq_control(drm_enc, true); 789 else 790 _dpu_encoder_resource_control_helper(drm_enc, true); 791 792 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 793 794 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 795 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 796 "kickoff"); 797 798 mutex_unlock(&dpu_enc->rc_lock); 799 break; 800 801 case DPU_ENC_RC_EVENT_FRAME_DONE: 802 /* 803 * mutex lock is not used as this event happens at interrupt 804 * context. And locking is not required as, the other events 805 * like KICKOFF and STOP does a wait-for-idle before executing 806 * the resource_control 807 */ 808 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 809 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 810 DRMID(drm_enc), sw_event, 811 dpu_enc->rc_state); 812 return -EINVAL; 813 } 814 815 /* 816 * schedule off work item only when there are no 817 * frames pending 818 */ 819 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 820 DRM_DEBUG_KMS("id:%d skip schedule work\n", 821 DRMID(drm_enc)); 822 return 0; 823 } 824 825 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 826 msecs_to_jiffies(dpu_enc->idle_timeout)); 827 828 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 829 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 830 "frame done"); 831 break; 832 833 case DPU_ENC_RC_EVENT_PRE_STOP: 834 /* cancel delayed off work, if any */ 835 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 836 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 837 sw_event); 838 839 mutex_lock(&dpu_enc->rc_lock); 840 841 if (is_vid_mode && 842 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 843 _dpu_encoder_irq_control(drm_enc, true); 844 } 845 /* skip if is already OFF or IDLE, resources are off already */ 846 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 847 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 848 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 849 DRMID(drm_enc), sw_event, 850 dpu_enc->rc_state); 851 mutex_unlock(&dpu_enc->rc_lock); 852 return 0; 853 } 854 855 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 856 857 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 858 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 859 "pre stop"); 860 861 mutex_unlock(&dpu_enc->rc_lock); 862 break; 863 864 case DPU_ENC_RC_EVENT_STOP: 865 mutex_lock(&dpu_enc->rc_lock); 866 867 /* return if the resource control is already in OFF state */ 868 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 869 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 870 DRMID(drm_enc), sw_event); 871 mutex_unlock(&dpu_enc->rc_lock); 872 return 0; 873 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 874 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 875 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 876 mutex_unlock(&dpu_enc->rc_lock); 877 return -EINVAL; 878 } 879 880 /** 881 * expect to arrive here only if in either idle state or pre-off 882 * and in IDLE state the resources are already disabled 883 */ 884 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 885 _dpu_encoder_resource_control_helper(drm_enc, false); 886 887 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 888 889 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 890 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 891 "stop"); 892 893 mutex_unlock(&dpu_enc->rc_lock); 894 break; 895 896 case DPU_ENC_RC_EVENT_ENTER_IDLE: 897 mutex_lock(&dpu_enc->rc_lock); 898 899 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 900 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 901 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 902 mutex_unlock(&dpu_enc->rc_lock); 903 return 0; 904 } 905 906 /* 907 * if we are in ON but a frame was just kicked off, 908 * ignore the IDLE event, it's probably a stale timer event 909 */ 910 if (dpu_enc->frame_busy_mask[0]) { 911 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 912 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 913 mutex_unlock(&dpu_enc->rc_lock); 914 return 0; 915 } 916 917 if (is_vid_mode) 918 _dpu_encoder_irq_control(drm_enc, false); 919 else 920 _dpu_encoder_resource_control_helper(drm_enc, false); 921 922 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 923 924 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 925 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 926 "idle"); 927 928 mutex_unlock(&dpu_enc->rc_lock); 929 break; 930 931 default: 932 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 933 sw_event); 934 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 935 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 936 "error"); 937 break; 938 } 939 940 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 941 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 942 "end"); 943 return 0; 944 } 945 946 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 947 struct drm_display_mode *mode, 948 struct drm_display_mode *adj_mode) 949 { 950 struct dpu_encoder_virt *dpu_enc; 951 struct msm_drm_private *priv; 952 struct dpu_kms *dpu_kms; 953 struct list_head *connector_list; 954 struct drm_connector *conn = NULL, *conn_iter; 955 struct drm_crtc *drm_crtc; 956 struct dpu_crtc_state *cstate; 957 struct dpu_global_state *global_state; 958 struct msm_display_topology topology; 959 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 960 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 961 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 962 int num_lm, num_ctl, num_pp; 963 int i, j; 964 965 if (!drm_enc) { 966 DPU_ERROR("invalid encoder\n"); 967 return; 968 } 969 970 dpu_enc = to_dpu_encoder_virt(drm_enc); 971 DPU_DEBUG_ENC(dpu_enc, "\n"); 972 973 priv = drm_enc->dev->dev_private; 974 dpu_kms = to_dpu_kms(priv->kms); 975 connector_list = &dpu_kms->dev->mode_config.connector_list; 976 977 global_state = dpu_kms_get_existing_global_state(dpu_kms); 978 if (IS_ERR_OR_NULL(global_state)) { 979 DPU_ERROR("Failed to get global state"); 980 return; 981 } 982 983 trace_dpu_enc_mode_set(DRMID(drm_enc)); 984 985 list_for_each_entry(conn_iter, connector_list, head) 986 if (conn_iter->encoder == drm_enc) 987 conn = conn_iter; 988 989 if (!conn) { 990 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); 991 return; 992 } else if (!conn->state) { 993 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); 994 return; 995 } 996 997 drm_for_each_crtc(drm_crtc, drm_enc->dev) 998 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc)) 999 break; 1000 1001 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 1002 1003 /* Query resource that have been reserved in atomic check step. */ 1004 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1005 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 1006 ARRAY_SIZE(hw_pp)); 1007 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1008 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 1009 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 1010 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 1011 1012 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 1013 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 1014 : NULL; 1015 1016 cstate = to_dpu_crtc_state(drm_crtc->state); 1017 1018 for (i = 0; i < num_lm; i++) { 1019 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 1020 1021 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 1022 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 1023 } 1024 1025 cstate->num_mixers = num_lm; 1026 1027 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1028 int num_blk; 1029 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; 1030 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1031 1032 if (!dpu_enc->hw_pp[i]) { 1033 DPU_ERROR_ENC(dpu_enc, 1034 "no pp block assigned at idx: %d\n", i); 1035 return; 1036 } 1037 1038 if (!hw_ctl[i]) { 1039 DPU_ERROR_ENC(dpu_enc, 1040 "no ctl block assigned at idx: %d\n", i); 1041 return; 1042 } 1043 1044 phys->hw_pp = dpu_enc->hw_pp[i]; 1045 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1046 1047 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm, 1048 global_state, drm_enc->base.id, DPU_HW_BLK_INTF, 1049 hw_blk, ARRAY_SIZE(hw_blk)); 1050 for (j = 0; j < num_blk; j++) { 1051 struct dpu_hw_intf *hw_intf; 1052 1053 hw_intf = to_dpu_hw_intf(hw_blk[i]); 1054 if (hw_intf->idx == phys->intf_idx) 1055 phys->hw_intf = hw_intf; 1056 } 1057 1058 if (!phys->hw_intf) { 1059 DPU_ERROR_ENC(dpu_enc, 1060 "no intf block assigned at idx: %d\n", i); 1061 return; 1062 } 1063 1064 phys->connector = conn->state->connector; 1065 if (phys->ops.mode_set) 1066 phys->ops.mode_set(phys, mode, adj_mode); 1067 } 1068 } 1069 1070 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1071 { 1072 struct dpu_encoder_virt *dpu_enc = NULL; 1073 struct msm_drm_private *priv; 1074 struct dpu_kms *dpu_kms; 1075 1076 if (!drm_enc || !drm_enc->dev) { 1077 DPU_ERROR("invalid parameters\n"); 1078 return; 1079 } 1080 1081 priv = drm_enc->dev->dev_private; 1082 dpu_kms = to_dpu_kms(priv->kms); 1083 1084 dpu_enc = to_dpu_encoder_virt(drm_enc); 1085 if (!dpu_enc || !dpu_enc->cur_master) { 1086 DPU_ERROR("invalid dpu encoder/master\n"); 1087 return; 1088 } 1089 1090 if (dpu_enc->cur_master->hw_mdptop && 1091 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) 1092 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( 1093 dpu_enc->cur_master->hw_mdptop, 1094 dpu_kms->catalog); 1095 1096 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1097 } 1098 1099 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1100 { 1101 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1102 1103 mutex_lock(&dpu_enc->enc_lock); 1104 1105 if (!dpu_enc->enabled) 1106 goto out; 1107 1108 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1109 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1110 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1111 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1112 1113 _dpu_encoder_virt_enable_helper(drm_enc); 1114 1115 out: 1116 mutex_unlock(&dpu_enc->enc_lock); 1117 } 1118 1119 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1120 { 1121 struct dpu_encoder_virt *dpu_enc = NULL; 1122 int ret = 0; 1123 struct drm_display_mode *cur_mode = NULL; 1124 1125 if (!drm_enc) { 1126 DPU_ERROR("invalid encoder\n"); 1127 return; 1128 } 1129 dpu_enc = to_dpu_encoder_virt(drm_enc); 1130 1131 mutex_lock(&dpu_enc->enc_lock); 1132 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1133 1134 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1135 cur_mode->vdisplay); 1136 1137 /* always enable slave encoder before master */ 1138 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1139 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1140 1141 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1142 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1143 1144 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1145 if (ret) { 1146 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1147 ret); 1148 goto out; 1149 } 1150 1151 _dpu_encoder_virt_enable_helper(drm_enc); 1152 1153 dpu_enc->enabled = true; 1154 1155 out: 1156 mutex_unlock(&dpu_enc->enc_lock); 1157 } 1158 1159 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1160 { 1161 struct dpu_encoder_virt *dpu_enc = NULL; 1162 struct msm_drm_private *priv; 1163 struct dpu_kms *dpu_kms; 1164 struct dpu_global_state *global_state; 1165 int i = 0; 1166 1167 if (!drm_enc) { 1168 DPU_ERROR("invalid encoder\n"); 1169 return; 1170 } else if (!drm_enc->dev) { 1171 DPU_ERROR("invalid dev\n"); 1172 return; 1173 } 1174 1175 dpu_enc = to_dpu_encoder_virt(drm_enc); 1176 DPU_DEBUG_ENC(dpu_enc, "\n"); 1177 1178 mutex_lock(&dpu_enc->enc_lock); 1179 dpu_enc->enabled = false; 1180 1181 priv = drm_enc->dev->dev_private; 1182 dpu_kms = to_dpu_kms(priv->kms); 1183 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1184 1185 trace_dpu_enc_disable(DRMID(drm_enc)); 1186 1187 /* wait for idle */ 1188 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1189 1190 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1191 1192 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1193 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1194 1195 if (phys->ops.disable) 1196 phys->ops.disable(phys); 1197 } 1198 1199 /* after phys waits for frame-done, should be no more frames pending */ 1200 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1201 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1202 del_timer_sync(&dpu_enc->frame_done_timer); 1203 } 1204 1205 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1206 1207 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1208 dpu_enc->phys_encs[i]->connector = NULL; 1209 } 1210 1211 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1212 1213 dpu_rm_release(global_state, drm_enc); 1214 1215 mutex_unlock(&dpu_enc->enc_lock); 1216 } 1217 1218 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1219 enum dpu_intf_type type, u32 controller_id) 1220 { 1221 int i = 0; 1222 1223 for (i = 0; i < catalog->intf_count; i++) { 1224 if (catalog->intf[i].type == type 1225 && catalog->intf[i].controller_id == controller_id) { 1226 return catalog->intf[i].id; 1227 } 1228 } 1229 1230 return INTF_MAX; 1231 } 1232 1233 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1234 struct dpu_encoder_phys *phy_enc) 1235 { 1236 struct dpu_encoder_virt *dpu_enc = NULL; 1237 unsigned long lock_flags; 1238 1239 if (!drm_enc || !phy_enc) 1240 return; 1241 1242 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1243 dpu_enc = to_dpu_encoder_virt(drm_enc); 1244 1245 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1246 if (dpu_enc->crtc) 1247 dpu_crtc_vblank_callback(dpu_enc->crtc); 1248 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1249 1250 atomic_inc(&phy_enc->vsync_cnt); 1251 DPU_ATRACE_END("encoder_vblank_callback"); 1252 } 1253 1254 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1255 struct dpu_encoder_phys *phy_enc) 1256 { 1257 if (!phy_enc) 1258 return; 1259 1260 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1261 atomic_inc(&phy_enc->underrun_cnt); 1262 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1263 atomic_read(&phy_enc->underrun_cnt)); 1264 DPU_ATRACE_END("encoder_underrun_callback"); 1265 } 1266 1267 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1268 { 1269 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1270 unsigned long lock_flags; 1271 1272 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1273 /* crtc should always be cleared before re-assigning */ 1274 WARN_ON(crtc && dpu_enc->crtc); 1275 dpu_enc->crtc = crtc; 1276 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1277 } 1278 1279 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1280 struct drm_crtc *crtc, bool enable) 1281 { 1282 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1283 unsigned long lock_flags; 1284 int i; 1285 1286 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1287 1288 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1289 if (dpu_enc->crtc != crtc) { 1290 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1291 return; 1292 } 1293 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1294 1295 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1296 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1297 1298 if (phys->ops.control_vblank_irq) 1299 phys->ops.control_vblank_irq(phys, enable); 1300 } 1301 } 1302 1303 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1304 void (*frame_event_cb)(void *, u32 event), 1305 void *frame_event_cb_data) 1306 { 1307 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1308 unsigned long lock_flags; 1309 bool enable; 1310 1311 enable = frame_event_cb ? true : false; 1312 1313 if (!drm_enc) { 1314 DPU_ERROR("invalid encoder\n"); 1315 return; 1316 } 1317 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1318 1319 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1320 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1321 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1322 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1323 } 1324 1325 static void dpu_encoder_frame_done_callback( 1326 struct drm_encoder *drm_enc, 1327 struct dpu_encoder_phys *ready_phys, u32 event) 1328 { 1329 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1330 unsigned int i; 1331 1332 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1333 | DPU_ENCODER_FRAME_EVENT_ERROR 1334 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1335 1336 if (!dpu_enc->frame_busy_mask[0]) { 1337 /** 1338 * suppress frame_done without waiter, 1339 * likely autorefresh 1340 */ 1341 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1342 event, ready_phys->intf_idx); 1343 return; 1344 } 1345 1346 /* One of the physical encoders has become idle */ 1347 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1348 if (dpu_enc->phys_encs[i] == ready_phys) { 1349 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1350 dpu_enc->frame_busy_mask[0]); 1351 clear_bit(i, dpu_enc->frame_busy_mask); 1352 } 1353 } 1354 1355 if (!dpu_enc->frame_busy_mask[0]) { 1356 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1357 del_timer(&dpu_enc->frame_done_timer); 1358 1359 dpu_encoder_resource_control(drm_enc, 1360 DPU_ENC_RC_EVENT_FRAME_DONE); 1361 1362 if (dpu_enc->crtc_frame_event_cb) 1363 dpu_enc->crtc_frame_event_cb( 1364 dpu_enc->crtc_frame_event_cb_data, 1365 event); 1366 } 1367 } else { 1368 if (dpu_enc->crtc_frame_event_cb) 1369 dpu_enc->crtc_frame_event_cb( 1370 dpu_enc->crtc_frame_event_cb_data, event); 1371 } 1372 } 1373 1374 static void dpu_encoder_off_work(struct work_struct *work) 1375 { 1376 struct dpu_encoder_virt *dpu_enc = container_of(work, 1377 struct dpu_encoder_virt, delayed_off_work.work); 1378 1379 if (!dpu_enc) { 1380 DPU_ERROR("invalid dpu encoder\n"); 1381 return; 1382 } 1383 1384 dpu_encoder_resource_control(&dpu_enc->base, 1385 DPU_ENC_RC_EVENT_ENTER_IDLE); 1386 1387 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1388 DPU_ENCODER_FRAME_EVENT_IDLE); 1389 } 1390 1391 /** 1392 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1393 * drm_enc: Pointer to drm encoder structure 1394 * phys: Pointer to physical encoder structure 1395 * extra_flush_bits: Additional bit mask to include in flush trigger 1396 */ 1397 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1398 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1399 { 1400 struct dpu_hw_ctl *ctl; 1401 int pending_kickoff_cnt; 1402 u32 ret = UINT_MAX; 1403 1404 if (!phys->hw_pp) { 1405 DPU_ERROR("invalid pingpong hw\n"); 1406 return; 1407 } 1408 1409 ctl = phys->hw_ctl; 1410 if (!ctl->ops.trigger_flush) { 1411 DPU_ERROR("missing trigger cb\n"); 1412 return; 1413 } 1414 1415 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1416 1417 if (extra_flush_bits && ctl->ops.update_pending_flush) 1418 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1419 1420 ctl->ops.trigger_flush(ctl); 1421 1422 if (ctl->ops.get_pending_flush) 1423 ret = ctl->ops.get_pending_flush(ctl); 1424 1425 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1426 pending_kickoff_cnt, ctl->idx, 1427 extra_flush_bits, ret); 1428 } 1429 1430 /** 1431 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1432 * phys: Pointer to physical encoder structure 1433 */ 1434 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1435 { 1436 if (!phys) { 1437 DPU_ERROR("invalid argument(s)\n"); 1438 return; 1439 } 1440 1441 if (!phys->hw_pp) { 1442 DPU_ERROR("invalid pingpong hw\n"); 1443 return; 1444 } 1445 1446 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1447 phys->ops.trigger_start(phys); 1448 } 1449 1450 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1451 { 1452 struct dpu_hw_ctl *ctl; 1453 1454 ctl = phys_enc->hw_ctl; 1455 if (ctl->ops.trigger_start) { 1456 ctl->ops.trigger_start(ctl); 1457 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1458 } 1459 } 1460 1461 static int dpu_encoder_helper_wait_event_timeout( 1462 int32_t drm_id, 1463 int32_t hw_id, 1464 struct dpu_encoder_wait_info *info) 1465 { 1466 int rc = 0; 1467 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1468 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1469 s64 time; 1470 1471 do { 1472 rc = wait_event_timeout(*(info->wq), 1473 atomic_read(info->atomic_cnt) == 0, jiffies); 1474 time = ktime_to_ms(ktime_get()); 1475 1476 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, 1477 expected_time, 1478 atomic_read(info->atomic_cnt)); 1479 /* If we timed out, counter is valid and time is less, wait again */ 1480 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1481 (time < expected_time)); 1482 1483 return rc; 1484 } 1485 1486 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1487 { 1488 struct dpu_encoder_virt *dpu_enc; 1489 struct dpu_hw_ctl *ctl; 1490 int rc; 1491 1492 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1493 ctl = phys_enc->hw_ctl; 1494 1495 if (!ctl->ops.reset) 1496 return; 1497 1498 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), 1499 ctl->idx); 1500 1501 rc = ctl->ops.reset(ctl); 1502 if (rc) 1503 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1504 1505 phys_enc->enable_state = DPU_ENC_ENABLED; 1506 } 1507 1508 /** 1509 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1510 * Iterate through the physical encoders and perform consolidated flush 1511 * and/or control start triggering as needed. This is done in the virtual 1512 * encoder rather than the individual physical ones in order to handle 1513 * use cases that require visibility into multiple physical encoders at 1514 * a time. 1515 * dpu_enc: Pointer to virtual encoder structure 1516 */ 1517 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1518 { 1519 struct dpu_hw_ctl *ctl; 1520 uint32_t i, pending_flush; 1521 unsigned long lock_flags; 1522 1523 pending_flush = 0x0; 1524 1525 /* update pending counts and trigger kickoff ctl flush atomically */ 1526 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1527 1528 /* don't perform flush/start operations for slave encoders */ 1529 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1530 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1531 1532 if (phys->enable_state == DPU_ENC_DISABLED) 1533 continue; 1534 1535 ctl = phys->hw_ctl; 1536 1537 /* 1538 * This is cleared in frame_done worker, which isn't invoked 1539 * for async commits. So don't set this for async, since it'll 1540 * roll over to the next commit. 1541 */ 1542 if (phys->split_role != ENC_ROLE_SLAVE) 1543 set_bit(i, dpu_enc->frame_busy_mask); 1544 1545 if (!phys->ops.needs_single_flush || 1546 !phys->ops.needs_single_flush(phys)) 1547 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1548 else if (ctl->ops.get_pending_flush) 1549 pending_flush |= ctl->ops.get_pending_flush(ctl); 1550 } 1551 1552 /* for split flush, combine pending flush masks and send to master */ 1553 if (pending_flush && dpu_enc->cur_master) { 1554 _dpu_encoder_trigger_flush( 1555 &dpu_enc->base, 1556 dpu_enc->cur_master, 1557 pending_flush); 1558 } 1559 1560 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1561 1562 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1563 } 1564 1565 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1566 { 1567 struct dpu_encoder_virt *dpu_enc; 1568 struct dpu_encoder_phys *phys; 1569 unsigned int i; 1570 struct dpu_hw_ctl *ctl; 1571 struct msm_display_info *disp_info; 1572 1573 if (!drm_enc) { 1574 DPU_ERROR("invalid encoder\n"); 1575 return; 1576 } 1577 dpu_enc = to_dpu_encoder_virt(drm_enc); 1578 disp_info = &dpu_enc->disp_info; 1579 1580 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1581 phys = dpu_enc->phys_encs[i]; 1582 1583 ctl = phys->hw_ctl; 1584 if (ctl->ops.clear_pending_flush) 1585 ctl->ops.clear_pending_flush(ctl); 1586 1587 /* update only for command mode primary ctl */ 1588 if ((phys == dpu_enc->cur_master) && 1589 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1590 && ctl->ops.trigger_pending) 1591 ctl->ops.trigger_pending(ctl); 1592 } 1593 } 1594 1595 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1596 struct drm_display_mode *mode) 1597 { 1598 u64 pclk_rate; 1599 u32 pclk_period; 1600 u32 line_time; 1601 1602 /* 1603 * For linetime calculation, only operate on master encoder. 1604 */ 1605 if (!dpu_enc->cur_master) 1606 return 0; 1607 1608 if (!dpu_enc->cur_master->ops.get_line_count) { 1609 DPU_ERROR("get_line_count function not defined\n"); 1610 return 0; 1611 } 1612 1613 pclk_rate = mode->clock; /* pixel clock in kHz */ 1614 if (pclk_rate == 0) { 1615 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1616 return 0; 1617 } 1618 1619 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1620 if (pclk_period == 0) { 1621 DPU_ERROR("pclk period is 0\n"); 1622 return 0; 1623 } 1624 1625 /* 1626 * Line time calculation based on Pixel clock and HTOTAL. 1627 * Final unit is in ns. 1628 */ 1629 line_time = (pclk_period * mode->htotal) / 1000; 1630 if (line_time == 0) { 1631 DPU_ERROR("line time calculation is 0\n"); 1632 return 0; 1633 } 1634 1635 DPU_DEBUG_ENC(dpu_enc, 1636 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1637 pclk_rate, pclk_period, line_time); 1638 1639 return line_time; 1640 } 1641 1642 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1643 { 1644 struct drm_display_mode *mode; 1645 struct dpu_encoder_virt *dpu_enc; 1646 u32 cur_line; 1647 u32 line_time; 1648 u32 vtotal, time_to_vsync; 1649 ktime_t cur_time; 1650 1651 dpu_enc = to_dpu_encoder_virt(drm_enc); 1652 1653 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1654 DPU_ERROR("crtc/crtc state object is NULL\n"); 1655 return -EINVAL; 1656 } 1657 mode = &drm_enc->crtc->state->adjusted_mode; 1658 1659 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1660 if (!line_time) 1661 return -EINVAL; 1662 1663 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1664 1665 vtotal = mode->vtotal; 1666 if (cur_line >= vtotal) 1667 time_to_vsync = line_time * vtotal; 1668 else 1669 time_to_vsync = line_time * (vtotal - cur_line); 1670 1671 if (time_to_vsync == 0) { 1672 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1673 vtotal); 1674 return -EINVAL; 1675 } 1676 1677 cur_time = ktime_get(); 1678 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1679 1680 DPU_DEBUG_ENC(dpu_enc, 1681 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1682 cur_line, vtotal, time_to_vsync, 1683 ktime_to_ms(cur_time), 1684 ktime_to_ms(*wakeup_time)); 1685 return 0; 1686 } 1687 1688 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1689 { 1690 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1691 vsync_event_timer); 1692 struct drm_encoder *drm_enc = &dpu_enc->base; 1693 struct msm_drm_private *priv; 1694 struct msm_drm_thread *event_thread; 1695 1696 if (!drm_enc->dev || !drm_enc->crtc) { 1697 DPU_ERROR("invalid parameters\n"); 1698 return; 1699 } 1700 1701 priv = drm_enc->dev->dev_private; 1702 1703 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1704 DPU_ERROR("invalid crtc index\n"); 1705 return; 1706 } 1707 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1708 if (!event_thread) { 1709 DPU_ERROR("event_thread not found for crtc:%d\n", 1710 drm_enc->crtc->index); 1711 return; 1712 } 1713 1714 del_timer(&dpu_enc->vsync_event_timer); 1715 } 1716 1717 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1718 { 1719 struct dpu_encoder_virt *dpu_enc = container_of(work, 1720 struct dpu_encoder_virt, vsync_event_work); 1721 ktime_t wakeup_time; 1722 1723 if (!dpu_enc) { 1724 DPU_ERROR("invalid dpu encoder\n"); 1725 return; 1726 } 1727 1728 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) 1729 return; 1730 1731 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1732 mod_timer(&dpu_enc->vsync_event_timer, 1733 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1734 } 1735 1736 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1737 { 1738 struct dpu_encoder_virt *dpu_enc; 1739 struct dpu_encoder_phys *phys; 1740 bool needs_hw_reset = false; 1741 unsigned int i; 1742 1743 dpu_enc = to_dpu_encoder_virt(drm_enc); 1744 1745 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1746 1747 /* prepare for next kickoff, may include waiting on previous kickoff */ 1748 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1749 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1750 phys = dpu_enc->phys_encs[i]; 1751 if (phys->ops.prepare_for_kickoff) 1752 phys->ops.prepare_for_kickoff(phys); 1753 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1754 needs_hw_reset = true; 1755 } 1756 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1757 1758 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1759 1760 /* if any phys needs reset, reset all phys, in-order */ 1761 if (needs_hw_reset) { 1762 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1763 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1764 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1765 } 1766 } 1767 } 1768 1769 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1770 { 1771 struct dpu_encoder_virt *dpu_enc; 1772 struct dpu_encoder_phys *phys; 1773 ktime_t wakeup_time; 1774 unsigned long timeout_ms; 1775 unsigned int i; 1776 1777 DPU_ATRACE_BEGIN("encoder_kickoff"); 1778 dpu_enc = to_dpu_encoder_virt(drm_enc); 1779 1780 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1781 1782 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1783 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1784 1785 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1786 mod_timer(&dpu_enc->frame_done_timer, 1787 jiffies + msecs_to_jiffies(timeout_ms)); 1788 1789 /* All phys encs are ready to go, trigger the kickoff */ 1790 _dpu_encoder_kickoff_phys(dpu_enc); 1791 1792 /* allow phys encs to handle any post-kickoff business */ 1793 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1794 phys = dpu_enc->phys_encs[i]; 1795 if (phys->ops.handle_post_kickoff) 1796 phys->ops.handle_post_kickoff(phys); 1797 } 1798 1799 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1800 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { 1801 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1802 ktime_to_ms(wakeup_time)); 1803 mod_timer(&dpu_enc->vsync_event_timer, 1804 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1805 } 1806 1807 DPU_ATRACE_END("encoder_kickoff"); 1808 } 1809 1810 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1811 { 1812 struct dpu_encoder_virt *dpu_enc; 1813 struct dpu_encoder_phys *phys; 1814 int i; 1815 1816 if (!drm_enc) { 1817 DPU_ERROR("invalid encoder\n"); 1818 return; 1819 } 1820 dpu_enc = to_dpu_encoder_virt(drm_enc); 1821 1822 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1823 phys = dpu_enc->phys_encs[i]; 1824 if (phys->ops.prepare_commit) 1825 phys->ops.prepare_commit(phys); 1826 } 1827 } 1828 1829 #ifdef CONFIG_DEBUG_FS 1830 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1831 { 1832 struct dpu_encoder_virt *dpu_enc = s->private; 1833 int i; 1834 1835 mutex_lock(&dpu_enc->enc_lock); 1836 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1837 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1838 1839 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1840 phys->intf_idx - INTF_0, 1841 atomic_read(&phys->vsync_cnt), 1842 atomic_read(&phys->underrun_cnt)); 1843 1844 switch (phys->intf_mode) { 1845 case INTF_MODE_VIDEO: 1846 seq_puts(s, "mode: video\n"); 1847 break; 1848 case INTF_MODE_CMD: 1849 seq_puts(s, "mode: command\n"); 1850 break; 1851 default: 1852 seq_puts(s, "mode: ???\n"); 1853 break; 1854 } 1855 } 1856 mutex_unlock(&dpu_enc->enc_lock); 1857 1858 return 0; 1859 } 1860 1861 static int _dpu_encoder_debugfs_status_open(struct inode *inode, 1862 struct file *file) 1863 { 1864 return single_open(file, _dpu_encoder_status_show, inode->i_private); 1865 } 1866 1867 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1868 { 1869 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1870 int i; 1871 1872 static const struct file_operations debugfs_status_fops = { 1873 .open = _dpu_encoder_debugfs_status_open, 1874 .read = seq_read, 1875 .llseek = seq_lseek, 1876 .release = single_release, 1877 }; 1878 1879 char name[DPU_NAME_SIZE]; 1880 1881 if (!drm_enc->dev) { 1882 DPU_ERROR("invalid encoder or kms\n"); 1883 return -EINVAL; 1884 } 1885 1886 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1887 1888 /* create overall sub-directory for the encoder */ 1889 dpu_enc->debugfs_root = debugfs_create_dir(name, 1890 drm_enc->dev->primary->debugfs_root); 1891 1892 /* don't error check these */ 1893 debugfs_create_file("status", 0600, 1894 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); 1895 1896 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1897 if (dpu_enc->phys_encs[i]->ops.late_register) 1898 dpu_enc->phys_encs[i]->ops.late_register( 1899 dpu_enc->phys_encs[i], 1900 dpu_enc->debugfs_root); 1901 1902 return 0; 1903 } 1904 #else 1905 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1906 { 1907 return 0; 1908 } 1909 #endif 1910 1911 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1912 { 1913 return _dpu_encoder_init_debugfs(encoder); 1914 } 1915 1916 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1917 { 1918 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1919 1920 debugfs_remove_recursive(dpu_enc->debugfs_root); 1921 } 1922 1923 static int dpu_encoder_virt_add_phys_encs( 1924 u32 display_caps, 1925 struct dpu_encoder_virt *dpu_enc, 1926 struct dpu_enc_phys_init_params *params) 1927 { 1928 struct dpu_encoder_phys *enc = NULL; 1929 1930 DPU_DEBUG_ENC(dpu_enc, "\n"); 1931 1932 /* 1933 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1934 * in this function, check up-front. 1935 */ 1936 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1937 ARRAY_SIZE(dpu_enc->phys_encs)) { 1938 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1939 dpu_enc->num_phys_encs); 1940 return -EINVAL; 1941 } 1942 1943 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1944 enc = dpu_encoder_phys_vid_init(params); 1945 1946 if (IS_ERR_OR_NULL(enc)) { 1947 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1948 PTR_ERR(enc)); 1949 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1950 } 1951 1952 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1953 ++dpu_enc->num_phys_encs; 1954 } 1955 1956 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 1957 enc = dpu_encoder_phys_cmd_init(params); 1958 1959 if (IS_ERR_OR_NULL(enc)) { 1960 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 1961 PTR_ERR(enc)); 1962 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1963 } 1964 1965 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1966 ++dpu_enc->num_phys_encs; 1967 } 1968 1969 if (params->split_role == ENC_ROLE_SLAVE) 1970 dpu_enc->cur_slave = enc; 1971 else 1972 dpu_enc->cur_master = enc; 1973 1974 return 0; 1975 } 1976 1977 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 1978 .handle_vblank_virt = dpu_encoder_vblank_callback, 1979 .handle_underrun_virt = dpu_encoder_underrun_callback, 1980 .handle_frame_done = dpu_encoder_frame_done_callback, 1981 }; 1982 1983 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 1984 struct dpu_kms *dpu_kms, 1985 struct msm_display_info *disp_info) 1986 { 1987 int ret = 0; 1988 int i = 0; 1989 enum dpu_intf_type intf_type; 1990 struct dpu_enc_phys_init_params phys_params; 1991 1992 if (!dpu_enc) { 1993 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 1994 return -EINVAL; 1995 } 1996 1997 dpu_enc->cur_master = NULL; 1998 1999 memset(&phys_params, 0, sizeof(phys_params)); 2000 phys_params.dpu_kms = dpu_kms; 2001 phys_params.parent = &dpu_enc->base; 2002 phys_params.parent_ops = &dpu_encoder_parent_ops; 2003 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2004 2005 DPU_DEBUG("\n"); 2006 2007 switch (disp_info->intf_type) { 2008 case DRM_MODE_ENCODER_DSI: 2009 intf_type = INTF_DSI; 2010 break; 2011 default: 2012 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); 2013 return -EINVAL; 2014 } 2015 2016 WARN_ON(disp_info->num_of_h_tiles < 1); 2017 2018 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2019 2020 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 2021 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 2022 dpu_enc->idle_pc_supported = 2023 dpu_kms->catalog->caps->has_idle_pc; 2024 2025 mutex_lock(&dpu_enc->enc_lock); 2026 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2027 /* 2028 * Left-most tile is at index 0, content is controller id 2029 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2030 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2031 */ 2032 u32 controller_id = disp_info->h_tile_instance[i]; 2033 2034 if (disp_info->num_of_h_tiles > 1) { 2035 if (i == 0) 2036 phys_params.split_role = ENC_ROLE_MASTER; 2037 else 2038 phys_params.split_role = ENC_ROLE_SLAVE; 2039 } else { 2040 phys_params.split_role = ENC_ROLE_SOLO; 2041 } 2042 2043 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2044 i, controller_id, phys_params.split_role); 2045 2046 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 2047 intf_type, 2048 controller_id); 2049 if (phys_params.intf_idx == INTF_MAX) { 2050 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 2051 intf_type, controller_id); 2052 ret = -EINVAL; 2053 } 2054 2055 if (!ret) { 2056 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 2057 dpu_enc, 2058 &phys_params); 2059 if (ret) 2060 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2061 } 2062 } 2063 2064 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2065 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2066 atomic_set(&phys->vsync_cnt, 0); 2067 atomic_set(&phys->underrun_cnt, 0); 2068 } 2069 mutex_unlock(&dpu_enc->enc_lock); 2070 2071 return ret; 2072 } 2073 2074 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2075 { 2076 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2077 frame_done_timer); 2078 struct drm_encoder *drm_enc = &dpu_enc->base; 2079 u32 event; 2080 2081 if (!drm_enc->dev) { 2082 DPU_ERROR("invalid parameters\n"); 2083 return; 2084 } 2085 2086 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2087 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2088 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2089 return; 2090 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2091 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2092 return; 2093 } 2094 2095 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2096 2097 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2098 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2099 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2100 } 2101 2102 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2103 .mode_set = dpu_encoder_virt_mode_set, 2104 .disable = dpu_encoder_virt_disable, 2105 .enable = dpu_kms_encoder_enable, 2106 .atomic_check = dpu_encoder_virt_atomic_check, 2107 2108 /* This is called by dpu_kms_encoder_enable */ 2109 .commit = dpu_encoder_virt_enable, 2110 }; 2111 2112 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2113 .destroy = dpu_encoder_destroy, 2114 .late_register = dpu_encoder_late_register, 2115 .early_unregister = dpu_encoder_early_unregister, 2116 }; 2117 2118 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2119 struct msm_display_info *disp_info) 2120 { 2121 struct msm_drm_private *priv = dev->dev_private; 2122 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2123 struct drm_encoder *drm_enc = NULL; 2124 struct dpu_encoder_virt *dpu_enc = NULL; 2125 int ret = 0; 2126 2127 dpu_enc = to_dpu_encoder_virt(enc); 2128 2129 mutex_init(&dpu_enc->enc_lock); 2130 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2131 if (ret) 2132 goto fail; 2133 2134 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2135 timer_setup(&dpu_enc->frame_done_timer, 2136 dpu_encoder_frame_done_timeout, 0); 2137 2138 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2139 timer_setup(&dpu_enc->vsync_event_timer, 2140 dpu_encoder_vsync_event_handler, 2141 0); 2142 2143 2144 mutex_init(&dpu_enc->rc_lock); 2145 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2146 dpu_encoder_off_work); 2147 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2148 2149 kthread_init_work(&dpu_enc->vsync_event_work, 2150 dpu_encoder_vsync_event_work_handler); 2151 2152 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2153 2154 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2155 2156 return ret; 2157 2158 fail: 2159 DPU_ERROR("failed to create encoder\n"); 2160 if (drm_enc) 2161 dpu_encoder_destroy(drm_enc); 2162 2163 return ret; 2164 2165 2166 } 2167 2168 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2169 int drm_enc_mode) 2170 { 2171 struct dpu_encoder_virt *dpu_enc = NULL; 2172 int rc = 0; 2173 2174 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2175 if (!dpu_enc) 2176 return ERR_PTR(ENOMEM); 2177 2178 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2179 drm_enc_mode, NULL); 2180 if (rc) { 2181 devm_kfree(dev->dev, dpu_enc); 2182 return ERR_PTR(rc); 2183 } 2184 2185 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2186 2187 spin_lock_init(&dpu_enc->enc_spinlock); 2188 dpu_enc->enabled = false; 2189 2190 return &dpu_enc->base; 2191 } 2192 2193 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2194 enum msm_event_wait event) 2195 { 2196 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2197 struct dpu_encoder_virt *dpu_enc = NULL; 2198 int i, ret = 0; 2199 2200 if (!drm_enc) { 2201 DPU_ERROR("invalid encoder\n"); 2202 return -EINVAL; 2203 } 2204 dpu_enc = to_dpu_encoder_virt(drm_enc); 2205 DPU_DEBUG_ENC(dpu_enc, "\n"); 2206 2207 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2208 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2209 2210 switch (event) { 2211 case MSM_ENC_COMMIT_DONE: 2212 fn_wait = phys->ops.wait_for_commit_done; 2213 break; 2214 case MSM_ENC_TX_COMPLETE: 2215 fn_wait = phys->ops.wait_for_tx_complete; 2216 break; 2217 case MSM_ENC_VBLANK: 2218 fn_wait = phys->ops.wait_for_vblank; 2219 break; 2220 default: 2221 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2222 event); 2223 return -EINVAL; 2224 } 2225 2226 if (fn_wait) { 2227 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2228 ret = fn_wait(phys); 2229 DPU_ATRACE_END("wait_for_completion_event"); 2230 if (ret) 2231 return ret; 2232 } 2233 } 2234 2235 return ret; 2236 } 2237 2238 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2239 { 2240 struct dpu_encoder_virt *dpu_enc = NULL; 2241 2242 if (!encoder) { 2243 DPU_ERROR("invalid encoder\n"); 2244 return INTF_MODE_NONE; 2245 } 2246 dpu_enc = to_dpu_encoder_virt(encoder); 2247 2248 if (dpu_enc->cur_master) 2249 return dpu_enc->cur_master->intf_mode; 2250 2251 if (dpu_enc->num_phys_encs) 2252 return dpu_enc->phys_encs[0]->intf_mode; 2253 2254 return INTF_MODE_NONE; 2255 } 2256