1 /* 2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 20 #include <linux/kthread.h> 21 #include <linux/debugfs.h> 22 #include <linux/seq_file.h> 23 24 #include "msm_drv.h" 25 #include "dpu_kms.h" 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_crtc_helper.h> 28 #include "dpu_hwio.h" 29 #include "dpu_hw_catalog.h" 30 #include "dpu_hw_intf.h" 31 #include "dpu_hw_ctl.h" 32 #include "dpu_formats.h" 33 #include "dpu_encoder_phys.h" 34 #include "dpu_crtc.h" 35 #include "dpu_trace.h" 36 #include "dpu_core_irq.h" 37 38 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ 39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 40 41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 43 44 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ 45 (p) ? (p)->parent->base.id : -1, \ 46 (p) ? (p)->intf_idx - INTF_0 : -1, \ 47 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 48 ##__VA_ARGS__) 49 50 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 51 (p) ? (p)->parent->base.id : -1, \ 52 (p) ? (p)->intf_idx - INTF_0 : -1, \ 53 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 54 ##__VA_ARGS__) 55 56 /* 57 * Two to anticipate panels that can do cmd/vid dynamic switching 58 * plan is to create all possible physical encoder types, and switch between 59 * them at runtime 60 */ 61 #define NUM_PHYS_ENCODER_TYPES 2 62 63 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 64 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 65 66 #define MAX_CHANNELS_PER_ENC 2 67 68 #define IDLE_SHORT_TIMEOUT 1 69 70 #define MAX_VDISPLAY_SPLIT 1080 71 72 /** 73 * enum dpu_enc_rc_events - events for resource control state machine 74 * @DPU_ENC_RC_EVENT_KICKOFF: 75 * This event happens at NORMAL priority. 76 * Event that signals the start of the transfer. When this event is 77 * received, enable MDP/DSI core clocks. Regardless of the previous 78 * state, the resource should be in ON state at the end of this event. 79 * @DPU_ENC_RC_EVENT_FRAME_DONE: 80 * This event happens at INTERRUPT level. 81 * Event signals the end of the data transfer after the PP FRAME_DONE 82 * event. At the end of this event, a delayed work is scheduled to go to 83 * IDLE_PC state after IDLE_TIMEOUT time. 84 * @DPU_ENC_RC_EVENT_PRE_STOP: 85 * This event happens at NORMAL priority. 86 * This event, when received during the ON state, leave the RC STATE 87 * in the PRE_OFF state. It should be followed by the STOP event as 88 * part of encoder disable. 89 * If received during IDLE or OFF states, it will do nothing. 90 * @DPU_ENC_RC_EVENT_STOP: 91 * This event happens at NORMAL priority. 92 * When this event is received, disable all the MDP/DSI core clocks, and 93 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 94 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 95 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 96 * Resource state should be in OFF at the end of the event. 97 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 98 * This event happens at NORMAL priority from a work item. 99 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 100 * This would disable MDP/DSI core clocks and change the resource state 101 * to IDLE. 102 */ 103 enum dpu_enc_rc_events { 104 DPU_ENC_RC_EVENT_KICKOFF = 1, 105 DPU_ENC_RC_EVENT_FRAME_DONE, 106 DPU_ENC_RC_EVENT_PRE_STOP, 107 DPU_ENC_RC_EVENT_STOP, 108 DPU_ENC_RC_EVENT_ENTER_IDLE 109 }; 110 111 /* 112 * enum dpu_enc_rc_states - states that the resource control maintains 113 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 114 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 115 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 116 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 117 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 118 */ 119 enum dpu_enc_rc_states { 120 DPU_ENC_RC_STATE_OFF, 121 DPU_ENC_RC_STATE_PRE_OFF, 122 DPU_ENC_RC_STATE_ON, 123 DPU_ENC_RC_STATE_IDLE 124 }; 125 126 /** 127 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 128 * encoders. Virtual encoder manages one "logical" display. Physical 129 * encoders manage one intf block, tied to a specific panel/sub-panel. 130 * Virtual encoder defers as much as possible to the physical encoders. 131 * Virtual encoder registers itself with the DRM Framework as the encoder. 132 * @base: drm_encoder base class for registration with DRM 133 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 134 * @bus_scaling_client: Client handle to the bus scaling interface 135 * @enabled: True if the encoder is active, protected by enc_lock 136 * @num_phys_encs: Actual number of physical encoders contained. 137 * @phys_encs: Container of physical encoders managed. 138 * @cur_master: Pointer to the current master in this mode. Optimization 139 * Only valid after enable. Cleared as disable. 140 * @hw_pp Handle to the pingpong blocks used for the display. No. 141 * pingpong blocks can be different than num_phys_encs. 142 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped 143 * for partial update right-only cases, such as pingpong 144 * split where virtual pingpong does not generate IRQs 145 * @crtc: Pointer to the currently assigned crtc. Normally you 146 * would use crtc->state->encoder_mask to determine the 147 * link between encoder/crtc. However in this case we need 148 * to track crtc in the disable() hook which is called 149 * _after_ encoder_mask is cleared. 150 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 151 * all CTL paths 152 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 153 * @debugfs_root: Debug file system root file node 154 * @enc_lock: Lock around physical encoder 155 * create/destroy/enable/disable 156 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 157 * busy processing current command. 158 * Bit0 = phys_encs[0] etc. 159 * @crtc_frame_event_cb: callback handler for frame event 160 * @crtc_frame_event_cb_data: callback handler private data 161 * @frame_done_timeout: frame done timeout in Hz 162 * @frame_done_timer: watchdog timer for frame done event 163 * @vsync_event_timer: vsync timer 164 * @disp_info: local copy of msm_display_info struct 165 * @idle_pc_supported: indicate if idle power collaps is supported 166 * @rc_lock: resource control mutex lock to protect 167 * virt encoder over various state changes 168 * @rc_state: resource controller state 169 * @delayed_off_work: delayed worker to schedule disabling of 170 * clks and resources after IDLE_TIMEOUT time. 171 * @vsync_event_work: worker to handle vsync event for autorefresh 172 * @topology: topology of the display 173 * @mode_set_complete: flag to indicate modeset completion 174 * @idle_timeout: idle timeout duration in milliseconds 175 */ 176 struct dpu_encoder_virt { 177 struct drm_encoder base; 178 spinlock_t enc_spinlock; 179 uint32_t bus_scaling_client; 180 181 bool enabled; 182 183 unsigned int num_phys_encs; 184 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 185 struct dpu_encoder_phys *cur_master; 186 struct dpu_encoder_phys *cur_slave; 187 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 188 189 bool intfs_swapped; 190 191 struct drm_crtc *crtc; 192 193 struct dentry *debugfs_root; 194 struct mutex enc_lock; 195 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 196 void (*crtc_frame_event_cb)(void *, u32 event); 197 void *crtc_frame_event_cb_data; 198 199 atomic_t frame_done_timeout; 200 struct timer_list frame_done_timer; 201 struct timer_list vsync_event_timer; 202 203 struct msm_display_info disp_info; 204 205 bool idle_pc_supported; 206 struct mutex rc_lock; 207 enum dpu_enc_rc_states rc_state; 208 struct kthread_delayed_work delayed_off_work; 209 struct kthread_work vsync_event_work; 210 struct msm_display_topology topology; 211 bool mode_set_complete; 212 213 u32 idle_timeout; 214 }; 215 216 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 217 218 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 219 enum dpu_intr_idx intr_idx) 220 { 221 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 222 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 223 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 224 225 if (phys_enc->parent_ops->handle_frame_done) 226 phys_enc->parent_ops->handle_frame_done( 227 phys_enc->parent, phys_enc, 228 DPU_ENCODER_FRAME_EVENT_ERROR); 229 } 230 231 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 232 int32_t hw_id, struct dpu_encoder_wait_info *info); 233 234 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 235 enum dpu_intr_idx intr_idx, 236 struct dpu_encoder_wait_info *wait_info) 237 { 238 struct dpu_encoder_irq *irq; 239 u32 irq_status; 240 int ret; 241 242 if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) { 243 DPU_ERROR("invalid params\n"); 244 return -EINVAL; 245 } 246 irq = &phys_enc->irq[intr_idx]; 247 248 /* note: do master / slave checking outside */ 249 250 /* return EWOULDBLOCK since we know the wait isn't necessary */ 251 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 252 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", 253 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 254 irq->irq_idx); 255 return -EWOULDBLOCK; 256 } 257 258 if (irq->irq_idx < 0) { 259 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", 260 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 261 irq->name); 262 return 0; 263 } 264 265 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", 266 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 267 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 268 atomic_read(wait_info->atomic_cnt)); 269 270 ret = dpu_encoder_helper_wait_event_timeout( 271 DRMID(phys_enc->parent), 272 irq->hw_idx, 273 wait_info); 274 275 if (ret <= 0) { 276 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 277 irq->irq_idx, true); 278 if (irq_status) { 279 unsigned long flags; 280 281 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " 282 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 283 DRMID(phys_enc->parent), intr_idx, 284 irq->hw_idx, irq->irq_idx, 285 phys_enc->hw_pp->idx - PINGPONG_0, 286 atomic_read(wait_info->atomic_cnt)); 287 local_irq_save(flags); 288 irq->cb.func(phys_enc, irq->irq_idx); 289 local_irq_restore(flags); 290 ret = 0; 291 } else { 292 ret = -ETIMEDOUT; 293 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " 294 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 295 DRMID(phys_enc->parent), intr_idx, 296 irq->hw_idx, irq->irq_idx, 297 phys_enc->hw_pp->idx - PINGPONG_0, 298 atomic_read(wait_info->atomic_cnt)); 299 } 300 } else { 301 ret = 0; 302 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 303 intr_idx, irq->hw_idx, irq->irq_idx, 304 phys_enc->hw_pp->idx - PINGPONG_0, 305 atomic_read(wait_info->atomic_cnt)); 306 } 307 308 return ret; 309 } 310 311 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 312 enum dpu_intr_idx intr_idx) 313 { 314 struct dpu_encoder_irq *irq; 315 int ret = 0; 316 317 if (!phys_enc || intr_idx >= INTR_IDX_MAX) { 318 DPU_ERROR("invalid params\n"); 319 return -EINVAL; 320 } 321 irq = &phys_enc->irq[intr_idx]; 322 323 if (irq->irq_idx >= 0) { 324 DPU_DEBUG_PHYS(phys_enc, 325 "skipping already registered irq %s type %d\n", 326 irq->name, irq->intr_type); 327 return 0; 328 } 329 330 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, 331 irq->intr_type, irq->hw_idx); 332 if (irq->irq_idx < 0) { 333 DPU_ERROR_PHYS(phys_enc, 334 "failed to lookup IRQ index for %s type:%d\n", 335 irq->name, irq->intr_type); 336 return -EINVAL; 337 } 338 339 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 340 &irq->cb); 341 if (ret) { 342 DPU_ERROR_PHYS(phys_enc, 343 "failed to register IRQ callback for %s\n", 344 irq->name); 345 irq->irq_idx = -EINVAL; 346 return ret; 347 } 348 349 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); 350 if (ret) { 351 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", 352 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 353 irq->irq_idx); 354 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 355 irq->irq_idx, &irq->cb); 356 irq->irq_idx = -EINVAL; 357 return ret; 358 } 359 360 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 361 irq->hw_idx, irq->irq_idx); 362 363 return ret; 364 } 365 366 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 367 enum dpu_intr_idx intr_idx) 368 { 369 struct dpu_encoder_irq *irq; 370 int ret; 371 372 if (!phys_enc) { 373 DPU_ERROR("invalid encoder\n"); 374 return -EINVAL; 375 } 376 irq = &phys_enc->irq[intr_idx]; 377 378 /* silently skip irqs that weren't registered */ 379 if (irq->irq_idx < 0) { 380 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", 381 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 382 irq->irq_idx); 383 return 0; 384 } 385 386 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); 387 if (ret) { 388 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", 389 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 390 irq->irq_idx, ret); 391 } 392 393 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 394 &irq->cb); 395 if (ret) { 396 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", 397 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 398 irq->irq_idx, ret); 399 } 400 401 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 402 irq->hw_idx, irq->irq_idx); 403 404 irq->irq_idx = -EINVAL; 405 406 return 0; 407 } 408 409 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, 410 struct dpu_encoder_hw_resources *hw_res) 411 { 412 struct dpu_encoder_virt *dpu_enc = NULL; 413 int i = 0; 414 415 dpu_enc = to_dpu_encoder_virt(drm_enc); 416 DPU_DEBUG_ENC(dpu_enc, "\n"); 417 418 /* Query resources used by phys encs, expected to be without overlap */ 419 memset(hw_res, 0, sizeof(*hw_res)); 420 421 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 422 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 423 424 if (phys && phys->ops.get_hw_resources) 425 phys->ops.get_hw_resources(phys, hw_res); 426 } 427 } 428 429 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 430 { 431 struct dpu_encoder_virt *dpu_enc = NULL; 432 int i = 0; 433 434 if (!drm_enc) { 435 DPU_ERROR("invalid encoder\n"); 436 return; 437 } 438 439 dpu_enc = to_dpu_encoder_virt(drm_enc); 440 DPU_DEBUG_ENC(dpu_enc, "\n"); 441 442 mutex_lock(&dpu_enc->enc_lock); 443 444 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 445 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 446 447 if (phys && phys->ops.destroy) { 448 phys->ops.destroy(phys); 449 --dpu_enc->num_phys_encs; 450 dpu_enc->phys_encs[i] = NULL; 451 } 452 } 453 454 if (dpu_enc->num_phys_encs) 455 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 456 dpu_enc->num_phys_encs); 457 dpu_enc->num_phys_encs = 0; 458 mutex_unlock(&dpu_enc->enc_lock); 459 460 drm_encoder_cleanup(drm_enc); 461 mutex_destroy(&dpu_enc->enc_lock); 462 } 463 464 void dpu_encoder_helper_split_config( 465 struct dpu_encoder_phys *phys_enc, 466 enum dpu_intf interface) 467 { 468 struct dpu_encoder_virt *dpu_enc; 469 struct split_pipe_cfg cfg = { 0 }; 470 struct dpu_hw_mdp *hw_mdptop; 471 struct msm_display_info *disp_info; 472 473 if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) { 474 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); 475 return; 476 } 477 478 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 479 hw_mdptop = phys_enc->hw_mdptop; 480 disp_info = &dpu_enc->disp_info; 481 482 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 483 return; 484 485 /** 486 * disable split modes since encoder will be operating in as the only 487 * encoder, either for the entire use case in the case of, for example, 488 * single DSI, or for this frame in the case of left/right only partial 489 * update. 490 */ 491 if (phys_enc->split_role == ENC_ROLE_SOLO) { 492 if (hw_mdptop->ops.setup_split_pipe) 493 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 494 return; 495 } 496 497 cfg.en = true; 498 cfg.mode = phys_enc->intf_mode; 499 cfg.intf = interface; 500 501 if (cfg.en && phys_enc->ops.needs_single_flush && 502 phys_enc->ops.needs_single_flush(phys_enc)) 503 cfg.split_flush_en = true; 504 505 if (phys_enc->split_role == ENC_ROLE_MASTER) { 506 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 507 508 if (hw_mdptop->ops.setup_split_pipe) 509 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 510 } 511 } 512 513 static void _dpu_encoder_adjust_mode(struct drm_connector *connector, 514 struct drm_display_mode *adj_mode) 515 { 516 struct drm_display_mode *cur_mode; 517 518 if (!connector || !adj_mode) 519 return; 520 521 list_for_each_entry(cur_mode, &connector->modes, head) { 522 if (cur_mode->vdisplay == adj_mode->vdisplay && 523 cur_mode->hdisplay == adj_mode->hdisplay && 524 cur_mode->vrefresh == adj_mode->vrefresh) { 525 adj_mode->private = cur_mode->private; 526 adj_mode->private_flags |= cur_mode->private_flags; 527 } 528 } 529 } 530 531 static struct msm_display_topology dpu_encoder_get_topology( 532 struct dpu_encoder_virt *dpu_enc, 533 struct dpu_kms *dpu_kms, 534 struct drm_display_mode *mode) 535 { 536 struct msm_display_topology topology; 537 int i, intf_count = 0; 538 539 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 540 if (dpu_enc->phys_encs[i]) 541 intf_count++; 542 543 /* User split topology for width > 1080 */ 544 topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1; 545 topology.num_enc = 0; 546 topology.num_intf = intf_count; 547 548 return topology; 549 } 550 static int dpu_encoder_virt_atomic_check( 551 struct drm_encoder *drm_enc, 552 struct drm_crtc_state *crtc_state, 553 struct drm_connector_state *conn_state) 554 { 555 struct dpu_encoder_virt *dpu_enc; 556 struct msm_drm_private *priv; 557 struct dpu_kms *dpu_kms; 558 const struct drm_display_mode *mode; 559 struct drm_display_mode *adj_mode; 560 struct msm_display_topology topology; 561 int i = 0; 562 int ret = 0; 563 564 if (!drm_enc || !crtc_state || !conn_state) { 565 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 566 drm_enc != 0, crtc_state != 0, conn_state != 0); 567 return -EINVAL; 568 } 569 570 dpu_enc = to_dpu_encoder_virt(drm_enc); 571 DPU_DEBUG_ENC(dpu_enc, "\n"); 572 573 priv = drm_enc->dev->dev_private; 574 dpu_kms = to_dpu_kms(priv->kms); 575 mode = &crtc_state->mode; 576 adj_mode = &crtc_state->adjusted_mode; 577 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 578 579 /* 580 * display drivers may populate private fields of the drm display mode 581 * structure while registering possible modes of a connector with DRM. 582 * These private fields are not populated back while DRM invokes 583 * the mode_set callbacks. This module retrieves and populates the 584 * private fields of the given mode. 585 */ 586 _dpu_encoder_adjust_mode(conn_state->connector, adj_mode); 587 588 /* perform atomic check on the first physical encoder (master) */ 589 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 590 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 591 592 if (phys && phys->ops.atomic_check) 593 ret = phys->ops.atomic_check(phys, crtc_state, 594 conn_state); 595 else if (phys && phys->ops.mode_fixup) 596 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) 597 ret = -EINVAL; 598 599 if (ret) { 600 DPU_ERROR_ENC(dpu_enc, 601 "mode unsupported, phys idx %d\n", i); 602 break; 603 } 604 } 605 606 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 607 608 /* Reserve dynamic resources now. Indicating AtomicTest phase */ 609 if (!ret) { 610 /* 611 * Avoid reserving resources when mode set is pending. Topology 612 * info may not be available to complete reservation. 613 */ 614 if (drm_atomic_crtc_needs_modeset(crtc_state) 615 && dpu_enc->mode_set_complete) { 616 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state, 617 topology, true); 618 dpu_enc->mode_set_complete = false; 619 } 620 } 621 622 if (!ret) 623 drm_mode_set_crtcinfo(adj_mode, 0); 624 625 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags, 626 adj_mode->private_flags); 627 628 return ret; 629 } 630 631 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 632 struct msm_display_info *disp_info) 633 { 634 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 635 struct msm_drm_private *priv; 636 struct dpu_kms *dpu_kms; 637 struct dpu_hw_mdp *hw_mdptop; 638 struct drm_encoder *drm_enc; 639 int i; 640 641 if (!dpu_enc || !disp_info) { 642 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 643 dpu_enc != NULL, disp_info != NULL); 644 return; 645 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 646 DPU_ERROR("invalid num phys enc %d/%d\n", 647 dpu_enc->num_phys_encs, 648 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 649 return; 650 } 651 652 drm_enc = &dpu_enc->base; 653 /* this pointers are checked in virt_enable_helper */ 654 priv = drm_enc->dev->dev_private; 655 656 dpu_kms = to_dpu_kms(priv->kms); 657 if (!dpu_kms) { 658 DPU_ERROR("invalid dpu_kms\n"); 659 return; 660 } 661 662 hw_mdptop = dpu_kms->hw_mdp; 663 if (!hw_mdptop) { 664 DPU_ERROR("invalid mdptop\n"); 665 return; 666 } 667 668 if (hw_mdptop->ops.setup_vsync_source && 669 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 670 for (i = 0; i < dpu_enc->num_phys_encs; i++) 671 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 672 673 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 674 if (disp_info->is_te_using_watchdog_timer) 675 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 676 else 677 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 678 679 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 680 } 681 } 682 683 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 684 { 685 struct dpu_encoder_virt *dpu_enc; 686 int i; 687 688 if (!drm_enc) { 689 DPU_ERROR("invalid encoder\n"); 690 return; 691 } 692 693 dpu_enc = to_dpu_encoder_virt(drm_enc); 694 695 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 696 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 697 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 698 699 if (phys && phys->ops.irq_control) 700 phys->ops.irq_control(phys, enable); 701 } 702 703 } 704 705 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 706 bool enable) 707 { 708 struct msm_drm_private *priv; 709 struct dpu_kms *dpu_kms; 710 struct dpu_encoder_virt *dpu_enc; 711 712 dpu_enc = to_dpu_encoder_virt(drm_enc); 713 priv = drm_enc->dev->dev_private; 714 dpu_kms = to_dpu_kms(priv->kms); 715 716 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 717 718 if (!dpu_enc->cur_master) { 719 DPU_ERROR("encoder master not set\n"); 720 return; 721 } 722 723 if (enable) { 724 /* enable DPU core clks */ 725 pm_runtime_get_sync(&dpu_kms->pdev->dev); 726 727 /* enable all the irq */ 728 _dpu_encoder_irq_control(drm_enc, true); 729 730 } else { 731 /* disable all the irq */ 732 _dpu_encoder_irq_control(drm_enc, false); 733 734 /* disable DPU core clks */ 735 pm_runtime_put_sync(&dpu_kms->pdev->dev); 736 } 737 738 } 739 740 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 741 u32 sw_event) 742 { 743 struct dpu_encoder_virt *dpu_enc; 744 struct msm_drm_private *priv; 745 struct msm_drm_thread *disp_thread; 746 bool is_vid_mode = false; 747 748 if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private || 749 !drm_enc->crtc) { 750 DPU_ERROR("invalid parameters\n"); 751 return -EINVAL; 752 } 753 dpu_enc = to_dpu_encoder_virt(drm_enc); 754 priv = drm_enc->dev->dev_private; 755 is_vid_mode = dpu_enc->disp_info.capabilities & 756 MSM_DISPLAY_CAP_VID_MODE; 757 758 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) { 759 DPU_ERROR("invalid crtc index\n"); 760 return -EINVAL; 761 } 762 disp_thread = &priv->disp_thread[drm_enc->crtc->index]; 763 764 /* 765 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 766 * events and return early for other events (ie wb display). 767 */ 768 if (!dpu_enc->idle_pc_supported && 769 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 770 sw_event != DPU_ENC_RC_EVENT_STOP && 771 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 772 return 0; 773 774 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 775 dpu_enc->rc_state, "begin"); 776 777 switch (sw_event) { 778 case DPU_ENC_RC_EVENT_KICKOFF: 779 /* cancel delayed off work, if any */ 780 if (kthread_cancel_delayed_work_sync( 781 &dpu_enc->delayed_off_work)) 782 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 783 sw_event); 784 785 mutex_lock(&dpu_enc->rc_lock); 786 787 /* return if the resource control is already in ON state */ 788 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 789 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", 790 DRMID(drm_enc), sw_event); 791 mutex_unlock(&dpu_enc->rc_lock); 792 return 0; 793 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 794 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 795 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", 796 DRMID(drm_enc), sw_event, 797 dpu_enc->rc_state); 798 mutex_unlock(&dpu_enc->rc_lock); 799 return -EINVAL; 800 } 801 802 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 803 _dpu_encoder_irq_control(drm_enc, true); 804 else 805 _dpu_encoder_resource_control_helper(drm_enc, true); 806 807 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 808 809 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 810 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 811 "kickoff"); 812 813 mutex_unlock(&dpu_enc->rc_lock); 814 break; 815 816 case DPU_ENC_RC_EVENT_FRAME_DONE: 817 /* 818 * mutex lock is not used as this event happens at interrupt 819 * context. And locking is not required as, the other events 820 * like KICKOFF and STOP does a wait-for-idle before executing 821 * the resource_control 822 */ 823 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 824 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 825 DRMID(drm_enc), sw_event, 826 dpu_enc->rc_state); 827 return -EINVAL; 828 } 829 830 /* 831 * schedule off work item only when there are no 832 * frames pending 833 */ 834 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 835 DRM_DEBUG_KMS("id:%d skip schedule work\n", 836 DRMID(drm_enc)); 837 return 0; 838 } 839 840 kthread_queue_delayed_work( 841 &disp_thread->worker, 842 &dpu_enc->delayed_off_work, 843 msecs_to_jiffies(dpu_enc->idle_timeout)); 844 845 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 846 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 847 "frame done"); 848 break; 849 850 case DPU_ENC_RC_EVENT_PRE_STOP: 851 /* cancel delayed off work, if any */ 852 if (kthread_cancel_delayed_work_sync( 853 &dpu_enc->delayed_off_work)) 854 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 855 sw_event); 856 857 mutex_lock(&dpu_enc->rc_lock); 858 859 if (is_vid_mode && 860 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 861 _dpu_encoder_irq_control(drm_enc, true); 862 } 863 /* skip if is already OFF or IDLE, resources are off already */ 864 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 865 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 866 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 867 DRMID(drm_enc), sw_event, 868 dpu_enc->rc_state); 869 mutex_unlock(&dpu_enc->rc_lock); 870 return 0; 871 } 872 873 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 874 875 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 876 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 877 "pre stop"); 878 879 mutex_unlock(&dpu_enc->rc_lock); 880 break; 881 882 case DPU_ENC_RC_EVENT_STOP: 883 mutex_lock(&dpu_enc->rc_lock); 884 885 /* return if the resource control is already in OFF state */ 886 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 887 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 888 DRMID(drm_enc), sw_event); 889 mutex_unlock(&dpu_enc->rc_lock); 890 return 0; 891 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 892 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 893 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 894 mutex_unlock(&dpu_enc->rc_lock); 895 return -EINVAL; 896 } 897 898 /** 899 * expect to arrive here only if in either idle state or pre-off 900 * and in IDLE state the resources are already disabled 901 */ 902 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 903 _dpu_encoder_resource_control_helper(drm_enc, false); 904 905 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 906 907 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 908 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 909 "stop"); 910 911 mutex_unlock(&dpu_enc->rc_lock); 912 break; 913 914 case DPU_ENC_RC_EVENT_ENTER_IDLE: 915 mutex_lock(&dpu_enc->rc_lock); 916 917 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 918 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 919 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 920 mutex_unlock(&dpu_enc->rc_lock); 921 return 0; 922 } 923 924 /* 925 * if we are in ON but a frame was just kicked off, 926 * ignore the IDLE event, it's probably a stale timer event 927 */ 928 if (dpu_enc->frame_busy_mask[0]) { 929 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 930 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 931 mutex_unlock(&dpu_enc->rc_lock); 932 return 0; 933 } 934 935 if (is_vid_mode) 936 _dpu_encoder_irq_control(drm_enc, false); 937 else 938 _dpu_encoder_resource_control_helper(drm_enc, false); 939 940 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 941 942 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 943 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 944 "idle"); 945 946 mutex_unlock(&dpu_enc->rc_lock); 947 break; 948 949 default: 950 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 951 sw_event); 952 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 953 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 954 "error"); 955 break; 956 } 957 958 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 959 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 960 "end"); 961 return 0; 962 } 963 964 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 965 struct drm_display_mode *mode, 966 struct drm_display_mode *adj_mode) 967 { 968 struct dpu_encoder_virt *dpu_enc; 969 struct msm_drm_private *priv; 970 struct dpu_kms *dpu_kms; 971 struct list_head *connector_list; 972 struct drm_connector *conn = NULL, *conn_iter; 973 struct dpu_rm_hw_iter pp_iter, ctl_iter; 974 struct msm_display_topology topology; 975 struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL }; 976 int i = 0, ret; 977 978 if (!drm_enc) { 979 DPU_ERROR("invalid encoder\n"); 980 return; 981 } 982 983 dpu_enc = to_dpu_encoder_virt(drm_enc); 984 DPU_DEBUG_ENC(dpu_enc, "\n"); 985 986 priv = drm_enc->dev->dev_private; 987 dpu_kms = to_dpu_kms(priv->kms); 988 connector_list = &dpu_kms->dev->mode_config.connector_list; 989 990 trace_dpu_enc_mode_set(DRMID(drm_enc)); 991 992 list_for_each_entry(conn_iter, connector_list, head) 993 if (conn_iter->encoder == drm_enc) 994 conn = conn_iter; 995 996 if (!conn) { 997 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); 998 return; 999 } else if (!conn->state) { 1000 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); 1001 return; 1002 } 1003 1004 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 1005 1006 /* Reserve dynamic resources now. Indicating non-AtomicTest phase */ 1007 ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, drm_enc->crtc->state, 1008 topology, false); 1009 if (ret) { 1010 DPU_ERROR_ENC(dpu_enc, 1011 "failed to reserve hw resources, %d\n", ret); 1012 return; 1013 } 1014 1015 dpu_rm_init_hw_iter(&pp_iter, drm_enc->base.id, DPU_HW_BLK_PINGPONG); 1016 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1017 dpu_enc->hw_pp[i] = NULL; 1018 if (!dpu_rm_get_hw(&dpu_kms->rm, &pp_iter)) 1019 break; 1020 dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw; 1021 } 1022 1023 dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL); 1024 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { 1025 if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter)) 1026 break; 1027 hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw; 1028 } 1029 1030 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1031 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1032 1033 if (phys) { 1034 if (!dpu_enc->hw_pp[i]) { 1035 DPU_ERROR_ENC(dpu_enc, "no pp block assigned" 1036 "at idx: %d\n", i); 1037 return; 1038 } 1039 1040 if (!hw_ctl[i]) { 1041 DPU_ERROR_ENC(dpu_enc, "no ctl block assigned" 1042 "at idx: %d\n", i); 1043 return; 1044 } 1045 1046 phys->hw_pp = dpu_enc->hw_pp[i]; 1047 phys->hw_ctl = hw_ctl[i]; 1048 1049 phys->connector = conn->state->connector; 1050 if (phys->ops.mode_set) 1051 phys->ops.mode_set(phys, mode, adj_mode); 1052 } 1053 } 1054 1055 dpu_enc->mode_set_complete = true; 1056 } 1057 1058 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1059 { 1060 struct dpu_encoder_virt *dpu_enc = NULL; 1061 struct msm_drm_private *priv; 1062 struct dpu_kms *dpu_kms; 1063 1064 if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) { 1065 DPU_ERROR("invalid parameters\n"); 1066 return; 1067 } 1068 1069 priv = drm_enc->dev->dev_private; 1070 dpu_kms = to_dpu_kms(priv->kms); 1071 if (!dpu_kms) { 1072 DPU_ERROR("invalid dpu_kms\n"); 1073 return; 1074 } 1075 1076 dpu_enc = to_dpu_encoder_virt(drm_enc); 1077 if (!dpu_enc || !dpu_enc->cur_master) { 1078 DPU_ERROR("invalid dpu encoder/master\n"); 1079 return; 1080 } 1081 1082 if (dpu_enc->cur_master->hw_mdptop && 1083 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) 1084 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( 1085 dpu_enc->cur_master->hw_mdptop, 1086 dpu_kms->catalog); 1087 1088 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1089 } 1090 1091 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1092 { 1093 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1094 1095 mutex_lock(&dpu_enc->enc_lock); 1096 1097 if (!dpu_enc->enabled) 1098 goto out; 1099 1100 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1101 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1102 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1103 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1104 1105 _dpu_encoder_virt_enable_helper(drm_enc); 1106 1107 out: 1108 mutex_unlock(&dpu_enc->enc_lock); 1109 } 1110 1111 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1112 { 1113 struct dpu_encoder_virt *dpu_enc = NULL; 1114 int ret = 0; 1115 struct drm_display_mode *cur_mode = NULL; 1116 1117 if (!drm_enc) { 1118 DPU_ERROR("invalid encoder\n"); 1119 return; 1120 } 1121 dpu_enc = to_dpu_encoder_virt(drm_enc); 1122 1123 mutex_lock(&dpu_enc->enc_lock); 1124 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1125 1126 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1127 cur_mode->vdisplay); 1128 1129 /* always enable slave encoder before master */ 1130 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1131 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1132 1133 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1134 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1135 1136 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1137 if (ret) { 1138 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1139 ret); 1140 goto out; 1141 } 1142 1143 _dpu_encoder_virt_enable_helper(drm_enc); 1144 1145 dpu_enc->enabled = true; 1146 1147 out: 1148 mutex_unlock(&dpu_enc->enc_lock); 1149 } 1150 1151 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1152 { 1153 struct dpu_encoder_virt *dpu_enc = NULL; 1154 struct msm_drm_private *priv; 1155 struct dpu_kms *dpu_kms; 1156 struct drm_display_mode *mode; 1157 int i = 0; 1158 1159 if (!drm_enc) { 1160 DPU_ERROR("invalid encoder\n"); 1161 return; 1162 } else if (!drm_enc->dev) { 1163 DPU_ERROR("invalid dev\n"); 1164 return; 1165 } else if (!drm_enc->dev->dev_private) { 1166 DPU_ERROR("invalid dev_private\n"); 1167 return; 1168 } 1169 1170 dpu_enc = to_dpu_encoder_virt(drm_enc); 1171 DPU_DEBUG_ENC(dpu_enc, "\n"); 1172 1173 mutex_lock(&dpu_enc->enc_lock); 1174 dpu_enc->enabled = false; 1175 1176 mode = &drm_enc->crtc->state->adjusted_mode; 1177 1178 priv = drm_enc->dev->dev_private; 1179 dpu_kms = to_dpu_kms(priv->kms); 1180 1181 trace_dpu_enc_disable(DRMID(drm_enc)); 1182 1183 /* wait for idle */ 1184 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1185 1186 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1187 1188 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1189 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1190 1191 if (phys && phys->ops.disable) 1192 phys->ops.disable(phys); 1193 } 1194 1195 /* after phys waits for frame-done, should be no more frames pending */ 1196 if (atomic_xchg(&dpu_enc->frame_done_timeout, 0)) { 1197 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1198 del_timer_sync(&dpu_enc->frame_done_timer); 1199 } 1200 1201 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1202 1203 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1204 if (dpu_enc->phys_encs[i]) 1205 dpu_enc->phys_encs[i]->connector = NULL; 1206 } 1207 1208 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1209 1210 dpu_rm_release(&dpu_kms->rm, drm_enc); 1211 1212 mutex_unlock(&dpu_enc->enc_lock); 1213 } 1214 1215 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1216 enum dpu_intf_type type, u32 controller_id) 1217 { 1218 int i = 0; 1219 1220 for (i = 0; i < catalog->intf_count; i++) { 1221 if (catalog->intf[i].type == type 1222 && catalog->intf[i].controller_id == controller_id) { 1223 return catalog->intf[i].id; 1224 } 1225 } 1226 1227 return INTF_MAX; 1228 } 1229 1230 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1231 struct dpu_encoder_phys *phy_enc) 1232 { 1233 struct dpu_encoder_virt *dpu_enc = NULL; 1234 unsigned long lock_flags; 1235 1236 if (!drm_enc || !phy_enc) 1237 return; 1238 1239 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1240 dpu_enc = to_dpu_encoder_virt(drm_enc); 1241 1242 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1243 if (dpu_enc->crtc) 1244 dpu_crtc_vblank_callback(dpu_enc->crtc); 1245 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1246 1247 atomic_inc(&phy_enc->vsync_cnt); 1248 DPU_ATRACE_END("encoder_vblank_callback"); 1249 } 1250 1251 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1252 struct dpu_encoder_phys *phy_enc) 1253 { 1254 if (!phy_enc) 1255 return; 1256 1257 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1258 atomic_inc(&phy_enc->underrun_cnt); 1259 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1260 atomic_read(&phy_enc->underrun_cnt)); 1261 DPU_ATRACE_END("encoder_underrun_callback"); 1262 } 1263 1264 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1265 { 1266 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1267 unsigned long lock_flags; 1268 1269 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1270 /* crtc should always be cleared before re-assigning */ 1271 WARN_ON(crtc && dpu_enc->crtc); 1272 dpu_enc->crtc = crtc; 1273 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1274 } 1275 1276 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1277 struct drm_crtc *crtc, bool enable) 1278 { 1279 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1280 unsigned long lock_flags; 1281 int i; 1282 1283 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1284 1285 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1286 if (dpu_enc->crtc != crtc) { 1287 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1288 return; 1289 } 1290 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1291 1292 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1293 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1294 1295 if (phys && phys->ops.control_vblank_irq) 1296 phys->ops.control_vblank_irq(phys, enable); 1297 } 1298 } 1299 1300 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1301 void (*frame_event_cb)(void *, u32 event), 1302 void *frame_event_cb_data) 1303 { 1304 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1305 unsigned long lock_flags; 1306 bool enable; 1307 1308 enable = frame_event_cb ? true : false; 1309 1310 if (!drm_enc) { 1311 DPU_ERROR("invalid encoder\n"); 1312 return; 1313 } 1314 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1315 1316 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1317 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1318 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1319 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1320 } 1321 1322 static void dpu_encoder_frame_done_callback( 1323 struct drm_encoder *drm_enc, 1324 struct dpu_encoder_phys *ready_phys, u32 event) 1325 { 1326 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1327 unsigned int i; 1328 1329 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1330 | DPU_ENCODER_FRAME_EVENT_ERROR 1331 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1332 1333 if (!dpu_enc->frame_busy_mask[0]) { 1334 /** 1335 * suppress frame_done without waiter, 1336 * likely autorefresh 1337 */ 1338 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1339 event, ready_phys->intf_idx); 1340 return; 1341 } 1342 1343 /* One of the physical encoders has become idle */ 1344 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1345 if (dpu_enc->phys_encs[i] == ready_phys) { 1346 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1347 dpu_enc->frame_busy_mask[0]); 1348 clear_bit(i, dpu_enc->frame_busy_mask); 1349 } 1350 } 1351 1352 if (!dpu_enc->frame_busy_mask[0]) { 1353 atomic_set(&dpu_enc->frame_done_timeout, 0); 1354 del_timer(&dpu_enc->frame_done_timer); 1355 1356 dpu_encoder_resource_control(drm_enc, 1357 DPU_ENC_RC_EVENT_FRAME_DONE); 1358 1359 if (dpu_enc->crtc_frame_event_cb) 1360 dpu_enc->crtc_frame_event_cb( 1361 dpu_enc->crtc_frame_event_cb_data, 1362 event); 1363 } 1364 } else { 1365 if (dpu_enc->crtc_frame_event_cb) 1366 dpu_enc->crtc_frame_event_cb( 1367 dpu_enc->crtc_frame_event_cb_data, event); 1368 } 1369 } 1370 1371 static void dpu_encoder_off_work(struct kthread_work *work) 1372 { 1373 struct dpu_encoder_virt *dpu_enc = container_of(work, 1374 struct dpu_encoder_virt, delayed_off_work.work); 1375 1376 if (!dpu_enc) { 1377 DPU_ERROR("invalid dpu encoder\n"); 1378 return; 1379 } 1380 1381 dpu_encoder_resource_control(&dpu_enc->base, 1382 DPU_ENC_RC_EVENT_ENTER_IDLE); 1383 1384 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1385 DPU_ENCODER_FRAME_EVENT_IDLE); 1386 } 1387 1388 /** 1389 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1390 * drm_enc: Pointer to drm encoder structure 1391 * phys: Pointer to physical encoder structure 1392 * extra_flush_bits: Additional bit mask to include in flush trigger 1393 */ 1394 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1395 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits, 1396 bool async) 1397 { 1398 struct dpu_hw_ctl *ctl; 1399 int pending_kickoff_cnt; 1400 u32 ret = UINT_MAX; 1401 1402 if (!drm_enc || !phys) { 1403 DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n", 1404 drm_enc != 0, phys != 0); 1405 return; 1406 } 1407 1408 if (!phys->hw_pp) { 1409 DPU_ERROR("invalid pingpong hw\n"); 1410 return; 1411 } 1412 1413 ctl = phys->hw_ctl; 1414 if (!ctl || !ctl->ops.trigger_flush) { 1415 DPU_ERROR("missing trigger cb\n"); 1416 return; 1417 } 1418 1419 if (!async) 1420 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1421 else 1422 pending_kickoff_cnt = atomic_read(&phys->pending_kickoff_cnt); 1423 1424 if (extra_flush_bits && ctl->ops.update_pending_flush) 1425 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1426 1427 ctl->ops.trigger_flush(ctl); 1428 1429 if (ctl->ops.get_pending_flush) 1430 ret = ctl->ops.get_pending_flush(ctl); 1431 1432 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1433 pending_kickoff_cnt, ctl->idx, 1434 extra_flush_bits, ret); 1435 } 1436 1437 /** 1438 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1439 * phys: Pointer to physical encoder structure 1440 */ 1441 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1442 { 1443 if (!phys) { 1444 DPU_ERROR("invalid argument(s)\n"); 1445 return; 1446 } 1447 1448 if (!phys->hw_pp) { 1449 DPU_ERROR("invalid pingpong hw\n"); 1450 return; 1451 } 1452 1453 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1454 phys->ops.trigger_start(phys); 1455 } 1456 1457 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1458 { 1459 struct dpu_hw_ctl *ctl; 1460 1461 if (!phys_enc) { 1462 DPU_ERROR("invalid encoder\n"); 1463 return; 1464 } 1465 1466 ctl = phys_enc->hw_ctl; 1467 if (ctl && ctl->ops.trigger_start) { 1468 ctl->ops.trigger_start(ctl); 1469 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1470 } 1471 } 1472 1473 static int dpu_encoder_helper_wait_event_timeout( 1474 int32_t drm_id, 1475 int32_t hw_id, 1476 struct dpu_encoder_wait_info *info) 1477 { 1478 int rc = 0; 1479 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1480 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1481 s64 time; 1482 1483 do { 1484 rc = wait_event_timeout(*(info->wq), 1485 atomic_read(info->atomic_cnt) == 0, jiffies); 1486 time = ktime_to_ms(ktime_get()); 1487 1488 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, 1489 expected_time, 1490 atomic_read(info->atomic_cnt)); 1491 /* If we timed out, counter is valid and time is less, wait again */ 1492 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1493 (time < expected_time)); 1494 1495 return rc; 1496 } 1497 1498 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1499 { 1500 struct dpu_encoder_virt *dpu_enc; 1501 struct dpu_hw_ctl *ctl; 1502 int rc; 1503 1504 if (!phys_enc) { 1505 DPU_ERROR("invalid encoder\n"); 1506 return; 1507 } 1508 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1509 ctl = phys_enc->hw_ctl; 1510 1511 if (!ctl || !ctl->ops.reset) 1512 return; 1513 1514 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), 1515 ctl->idx); 1516 1517 rc = ctl->ops.reset(ctl); 1518 if (rc) 1519 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1520 1521 phys_enc->enable_state = DPU_ENC_ENABLED; 1522 } 1523 1524 /** 1525 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1526 * Iterate through the physical encoders and perform consolidated flush 1527 * and/or control start triggering as needed. This is done in the virtual 1528 * encoder rather than the individual physical ones in order to handle 1529 * use cases that require visibility into multiple physical encoders at 1530 * a time. 1531 * dpu_enc: Pointer to virtual encoder structure 1532 */ 1533 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc, 1534 bool async) 1535 { 1536 struct dpu_hw_ctl *ctl; 1537 uint32_t i, pending_flush; 1538 unsigned long lock_flags; 1539 1540 if (!dpu_enc) { 1541 DPU_ERROR("invalid encoder\n"); 1542 return; 1543 } 1544 1545 pending_flush = 0x0; 1546 1547 /* update pending counts and trigger kickoff ctl flush atomically */ 1548 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1549 1550 /* don't perform flush/start operations for slave encoders */ 1551 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1552 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1553 1554 if (!phys || phys->enable_state == DPU_ENC_DISABLED) 1555 continue; 1556 1557 ctl = phys->hw_ctl; 1558 if (!ctl) 1559 continue; 1560 1561 if (phys->split_role != ENC_ROLE_SLAVE) 1562 set_bit(i, dpu_enc->frame_busy_mask); 1563 if (!phys->ops.needs_single_flush || 1564 !phys->ops.needs_single_flush(phys)) 1565 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0, 1566 async); 1567 else if (ctl->ops.get_pending_flush) 1568 pending_flush |= ctl->ops.get_pending_flush(ctl); 1569 } 1570 1571 /* for split flush, combine pending flush masks and send to master */ 1572 if (pending_flush && dpu_enc->cur_master) { 1573 _dpu_encoder_trigger_flush( 1574 &dpu_enc->base, 1575 dpu_enc->cur_master, 1576 pending_flush, async); 1577 } 1578 1579 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1580 1581 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1582 } 1583 1584 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1585 { 1586 struct dpu_encoder_virt *dpu_enc; 1587 struct dpu_encoder_phys *phys; 1588 unsigned int i; 1589 struct dpu_hw_ctl *ctl; 1590 struct msm_display_info *disp_info; 1591 1592 if (!drm_enc) { 1593 DPU_ERROR("invalid encoder\n"); 1594 return; 1595 } 1596 dpu_enc = to_dpu_encoder_virt(drm_enc); 1597 disp_info = &dpu_enc->disp_info; 1598 1599 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1600 phys = dpu_enc->phys_encs[i]; 1601 1602 if (phys && phys->hw_ctl) { 1603 ctl = phys->hw_ctl; 1604 if (ctl->ops.clear_pending_flush) 1605 ctl->ops.clear_pending_flush(ctl); 1606 1607 /* update only for command mode primary ctl */ 1608 if ((phys == dpu_enc->cur_master) && 1609 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1610 && ctl->ops.trigger_pending) 1611 ctl->ops.trigger_pending(ctl); 1612 } 1613 } 1614 } 1615 1616 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1617 struct drm_display_mode *mode) 1618 { 1619 u64 pclk_rate; 1620 u32 pclk_period; 1621 u32 line_time; 1622 1623 /* 1624 * For linetime calculation, only operate on master encoder. 1625 */ 1626 if (!dpu_enc->cur_master) 1627 return 0; 1628 1629 if (!dpu_enc->cur_master->ops.get_line_count) { 1630 DPU_ERROR("get_line_count function not defined\n"); 1631 return 0; 1632 } 1633 1634 pclk_rate = mode->clock; /* pixel clock in kHz */ 1635 if (pclk_rate == 0) { 1636 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1637 return 0; 1638 } 1639 1640 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1641 if (pclk_period == 0) { 1642 DPU_ERROR("pclk period is 0\n"); 1643 return 0; 1644 } 1645 1646 /* 1647 * Line time calculation based on Pixel clock and HTOTAL. 1648 * Final unit is in ns. 1649 */ 1650 line_time = (pclk_period * mode->htotal) / 1000; 1651 if (line_time == 0) { 1652 DPU_ERROR("line time calculation is 0\n"); 1653 return 0; 1654 } 1655 1656 DPU_DEBUG_ENC(dpu_enc, 1657 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1658 pclk_rate, pclk_period, line_time); 1659 1660 return line_time; 1661 } 1662 1663 static int _dpu_encoder_wakeup_time(struct drm_encoder *drm_enc, 1664 ktime_t *wakeup_time) 1665 { 1666 struct drm_display_mode *mode; 1667 struct dpu_encoder_virt *dpu_enc; 1668 u32 cur_line; 1669 u32 line_time; 1670 u32 vtotal, time_to_vsync; 1671 ktime_t cur_time; 1672 1673 dpu_enc = to_dpu_encoder_virt(drm_enc); 1674 1675 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1676 DPU_ERROR("crtc/crtc state object is NULL\n"); 1677 return -EINVAL; 1678 } 1679 mode = &drm_enc->crtc->state->adjusted_mode; 1680 1681 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1682 if (!line_time) 1683 return -EINVAL; 1684 1685 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1686 1687 vtotal = mode->vtotal; 1688 if (cur_line >= vtotal) 1689 time_to_vsync = line_time * vtotal; 1690 else 1691 time_to_vsync = line_time * (vtotal - cur_line); 1692 1693 if (time_to_vsync == 0) { 1694 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1695 vtotal); 1696 return -EINVAL; 1697 } 1698 1699 cur_time = ktime_get(); 1700 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1701 1702 DPU_DEBUG_ENC(dpu_enc, 1703 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1704 cur_line, vtotal, time_to_vsync, 1705 ktime_to_ms(cur_time), 1706 ktime_to_ms(*wakeup_time)); 1707 return 0; 1708 } 1709 1710 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1711 { 1712 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1713 vsync_event_timer); 1714 struct drm_encoder *drm_enc = &dpu_enc->base; 1715 struct msm_drm_private *priv; 1716 struct msm_drm_thread *event_thread; 1717 1718 if (!drm_enc->dev || !drm_enc->dev->dev_private || 1719 !drm_enc->crtc) { 1720 DPU_ERROR("invalid parameters\n"); 1721 return; 1722 } 1723 1724 priv = drm_enc->dev->dev_private; 1725 1726 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1727 DPU_ERROR("invalid crtc index\n"); 1728 return; 1729 } 1730 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1731 if (!event_thread) { 1732 DPU_ERROR("event_thread not found for crtc:%d\n", 1733 drm_enc->crtc->index); 1734 return; 1735 } 1736 1737 del_timer(&dpu_enc->vsync_event_timer); 1738 } 1739 1740 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1741 { 1742 struct dpu_encoder_virt *dpu_enc = container_of(work, 1743 struct dpu_encoder_virt, vsync_event_work); 1744 ktime_t wakeup_time; 1745 1746 if (!dpu_enc) { 1747 DPU_ERROR("invalid dpu encoder\n"); 1748 return; 1749 } 1750 1751 if (_dpu_encoder_wakeup_time(&dpu_enc->base, &wakeup_time)) 1752 return; 1753 1754 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1755 mod_timer(&dpu_enc->vsync_event_timer, 1756 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1757 } 1758 1759 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 1760 struct dpu_encoder_kickoff_params *params, bool async) 1761 { 1762 struct dpu_encoder_virt *dpu_enc; 1763 struct dpu_encoder_phys *phys; 1764 bool needs_hw_reset = false; 1765 unsigned int i; 1766 1767 if (!drm_enc || !params) { 1768 DPU_ERROR("invalid args\n"); 1769 return; 1770 } 1771 dpu_enc = to_dpu_encoder_virt(drm_enc); 1772 1773 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1774 1775 /* prepare for next kickoff, may include waiting on previous kickoff */ 1776 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1777 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1778 phys = dpu_enc->phys_encs[i]; 1779 if (phys) { 1780 if (phys->ops.prepare_for_kickoff) 1781 phys->ops.prepare_for_kickoff(phys, params); 1782 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1783 needs_hw_reset = true; 1784 } 1785 } 1786 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1787 1788 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1789 1790 /* if any phys needs reset, reset all phys, in-order */ 1791 if (needs_hw_reset) { 1792 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1793 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1794 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1795 } 1796 } 1797 } 1798 1799 void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async) 1800 { 1801 struct dpu_encoder_virt *dpu_enc; 1802 struct dpu_encoder_phys *phys; 1803 ktime_t wakeup_time; 1804 unsigned int i; 1805 1806 if (!drm_enc) { 1807 DPU_ERROR("invalid encoder\n"); 1808 return; 1809 } 1810 DPU_ATRACE_BEGIN("encoder_kickoff"); 1811 dpu_enc = to_dpu_encoder_virt(drm_enc); 1812 1813 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1814 1815 atomic_set(&dpu_enc->frame_done_timeout, 1816 DPU_FRAME_DONE_TIMEOUT * 1000 / 1817 drm_enc->crtc->state->adjusted_mode.vrefresh); 1818 mod_timer(&dpu_enc->frame_done_timer, jiffies + 1819 ((atomic_read(&dpu_enc->frame_done_timeout) * HZ) / 1000)); 1820 1821 /* All phys encs are ready to go, trigger the kickoff */ 1822 _dpu_encoder_kickoff_phys(dpu_enc, async); 1823 1824 /* allow phys encs to handle any post-kickoff business */ 1825 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1826 phys = dpu_enc->phys_encs[i]; 1827 if (phys && phys->ops.handle_post_kickoff) 1828 phys->ops.handle_post_kickoff(phys); 1829 } 1830 1831 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1832 !_dpu_encoder_wakeup_time(drm_enc, &wakeup_time)) { 1833 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1834 ktime_to_ms(wakeup_time)); 1835 mod_timer(&dpu_enc->vsync_event_timer, 1836 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1837 } 1838 1839 DPU_ATRACE_END("encoder_kickoff"); 1840 } 1841 1842 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1843 { 1844 struct dpu_encoder_virt *dpu_enc; 1845 struct dpu_encoder_phys *phys; 1846 int i; 1847 1848 if (!drm_enc) { 1849 DPU_ERROR("invalid encoder\n"); 1850 return; 1851 } 1852 dpu_enc = to_dpu_encoder_virt(drm_enc); 1853 1854 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1855 phys = dpu_enc->phys_encs[i]; 1856 if (phys && phys->ops.prepare_commit) 1857 phys->ops.prepare_commit(phys); 1858 } 1859 } 1860 1861 #ifdef CONFIG_DEBUG_FS 1862 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1863 { 1864 struct dpu_encoder_virt *dpu_enc = s->private; 1865 int i; 1866 1867 mutex_lock(&dpu_enc->enc_lock); 1868 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1869 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1870 1871 if (!phys) 1872 continue; 1873 1874 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1875 phys->intf_idx - INTF_0, 1876 atomic_read(&phys->vsync_cnt), 1877 atomic_read(&phys->underrun_cnt)); 1878 1879 switch (phys->intf_mode) { 1880 case INTF_MODE_VIDEO: 1881 seq_puts(s, "mode: video\n"); 1882 break; 1883 case INTF_MODE_CMD: 1884 seq_puts(s, "mode: command\n"); 1885 break; 1886 default: 1887 seq_puts(s, "mode: ???\n"); 1888 break; 1889 } 1890 } 1891 mutex_unlock(&dpu_enc->enc_lock); 1892 1893 return 0; 1894 } 1895 1896 static int _dpu_encoder_debugfs_status_open(struct inode *inode, 1897 struct file *file) 1898 { 1899 return single_open(file, _dpu_encoder_status_show, inode->i_private); 1900 } 1901 1902 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1903 { 1904 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1905 struct msm_drm_private *priv; 1906 struct dpu_kms *dpu_kms; 1907 int i; 1908 1909 static const struct file_operations debugfs_status_fops = { 1910 .open = _dpu_encoder_debugfs_status_open, 1911 .read = seq_read, 1912 .llseek = seq_lseek, 1913 .release = single_release, 1914 }; 1915 1916 char name[DPU_NAME_SIZE]; 1917 1918 if (!drm_enc->dev || !drm_enc->dev->dev_private) { 1919 DPU_ERROR("invalid encoder or kms\n"); 1920 return -EINVAL; 1921 } 1922 1923 priv = drm_enc->dev->dev_private; 1924 dpu_kms = to_dpu_kms(priv->kms); 1925 1926 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1927 1928 /* create overall sub-directory for the encoder */ 1929 dpu_enc->debugfs_root = debugfs_create_dir(name, 1930 drm_enc->dev->primary->debugfs_root); 1931 if (!dpu_enc->debugfs_root) 1932 return -ENOMEM; 1933 1934 /* don't error check these */ 1935 debugfs_create_file("status", 0600, 1936 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); 1937 1938 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1939 if (dpu_enc->phys_encs[i] && 1940 dpu_enc->phys_encs[i]->ops.late_register) 1941 dpu_enc->phys_encs[i]->ops.late_register( 1942 dpu_enc->phys_encs[i], 1943 dpu_enc->debugfs_root); 1944 1945 return 0; 1946 } 1947 #else 1948 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1949 { 1950 return 0; 1951 } 1952 #endif 1953 1954 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1955 { 1956 return _dpu_encoder_init_debugfs(encoder); 1957 } 1958 1959 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1960 { 1961 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1962 1963 debugfs_remove_recursive(dpu_enc->debugfs_root); 1964 } 1965 1966 static int dpu_encoder_virt_add_phys_encs( 1967 u32 display_caps, 1968 struct dpu_encoder_virt *dpu_enc, 1969 struct dpu_enc_phys_init_params *params) 1970 { 1971 struct dpu_encoder_phys *enc = NULL; 1972 1973 DPU_DEBUG_ENC(dpu_enc, "\n"); 1974 1975 /* 1976 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1977 * in this function, check up-front. 1978 */ 1979 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1980 ARRAY_SIZE(dpu_enc->phys_encs)) { 1981 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1982 dpu_enc->num_phys_encs); 1983 return -EINVAL; 1984 } 1985 1986 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1987 enc = dpu_encoder_phys_vid_init(params); 1988 1989 if (IS_ERR_OR_NULL(enc)) { 1990 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1991 PTR_ERR(enc)); 1992 return enc == 0 ? -EINVAL : PTR_ERR(enc); 1993 } 1994 1995 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1996 ++dpu_enc->num_phys_encs; 1997 } 1998 1999 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 2000 enc = dpu_encoder_phys_cmd_init(params); 2001 2002 if (IS_ERR_OR_NULL(enc)) { 2003 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 2004 PTR_ERR(enc)); 2005 return enc == 0 ? -EINVAL : PTR_ERR(enc); 2006 } 2007 2008 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 2009 ++dpu_enc->num_phys_encs; 2010 } 2011 2012 if (params->split_role == ENC_ROLE_SLAVE) 2013 dpu_enc->cur_slave = enc; 2014 else 2015 dpu_enc->cur_master = enc; 2016 2017 return 0; 2018 } 2019 2020 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 2021 .handle_vblank_virt = dpu_encoder_vblank_callback, 2022 .handle_underrun_virt = dpu_encoder_underrun_callback, 2023 .handle_frame_done = dpu_encoder_frame_done_callback, 2024 }; 2025 2026 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 2027 struct dpu_kms *dpu_kms, 2028 struct msm_display_info *disp_info) 2029 { 2030 int ret = 0; 2031 int i = 0; 2032 enum dpu_intf_type intf_type; 2033 struct dpu_enc_phys_init_params phys_params; 2034 2035 if (!dpu_enc || !dpu_kms) { 2036 DPU_ERROR("invalid arg(s), enc %d kms %d\n", 2037 dpu_enc != 0, dpu_kms != 0); 2038 return -EINVAL; 2039 } 2040 2041 dpu_enc->cur_master = NULL; 2042 2043 memset(&phys_params, 0, sizeof(phys_params)); 2044 phys_params.dpu_kms = dpu_kms; 2045 phys_params.parent = &dpu_enc->base; 2046 phys_params.parent_ops = &dpu_encoder_parent_ops; 2047 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 2048 2049 DPU_DEBUG("\n"); 2050 2051 switch (disp_info->intf_type) { 2052 case DRM_MODE_ENCODER_DSI: 2053 intf_type = INTF_DSI; 2054 break; 2055 default: 2056 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); 2057 return -EINVAL; 2058 } 2059 2060 WARN_ON(disp_info->num_of_h_tiles < 1); 2061 2062 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 2063 2064 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 2065 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 2066 dpu_enc->idle_pc_supported = 2067 dpu_kms->catalog->caps->has_idle_pc; 2068 2069 mutex_lock(&dpu_enc->enc_lock); 2070 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2071 /* 2072 * Left-most tile is at index 0, content is controller id 2073 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2074 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2075 */ 2076 u32 controller_id = disp_info->h_tile_instance[i]; 2077 2078 if (disp_info->num_of_h_tiles > 1) { 2079 if (i == 0) 2080 phys_params.split_role = ENC_ROLE_MASTER; 2081 else 2082 phys_params.split_role = ENC_ROLE_SLAVE; 2083 } else { 2084 phys_params.split_role = ENC_ROLE_SOLO; 2085 } 2086 2087 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2088 i, controller_id, phys_params.split_role); 2089 2090 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 2091 intf_type, 2092 controller_id); 2093 if (phys_params.intf_idx == INTF_MAX) { 2094 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 2095 intf_type, controller_id); 2096 ret = -EINVAL; 2097 } 2098 2099 if (!ret) { 2100 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 2101 dpu_enc, 2102 &phys_params); 2103 if (ret) 2104 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2105 } 2106 } 2107 2108 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2109 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2110 2111 if (phys) { 2112 atomic_set(&phys->vsync_cnt, 0); 2113 atomic_set(&phys->underrun_cnt, 0); 2114 } 2115 } 2116 mutex_unlock(&dpu_enc->enc_lock); 2117 2118 return ret; 2119 } 2120 2121 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2122 { 2123 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2124 frame_done_timer); 2125 struct drm_encoder *drm_enc = &dpu_enc->base; 2126 struct msm_drm_private *priv; 2127 u32 event; 2128 2129 if (!drm_enc->dev || !drm_enc->dev->dev_private) { 2130 DPU_ERROR("invalid parameters\n"); 2131 return; 2132 } 2133 priv = drm_enc->dev->dev_private; 2134 2135 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2136 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2137 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2138 return; 2139 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout, 0)) { 2140 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2141 return; 2142 } 2143 2144 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2145 2146 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2147 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2148 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2149 } 2150 2151 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2152 .mode_set = dpu_encoder_virt_mode_set, 2153 .disable = dpu_encoder_virt_disable, 2154 .enable = dpu_kms_encoder_enable, 2155 .atomic_check = dpu_encoder_virt_atomic_check, 2156 2157 /* This is called by dpu_kms_encoder_enable */ 2158 .commit = dpu_encoder_virt_enable, 2159 }; 2160 2161 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2162 .destroy = dpu_encoder_destroy, 2163 .late_register = dpu_encoder_late_register, 2164 .early_unregister = dpu_encoder_early_unregister, 2165 }; 2166 2167 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2168 struct msm_display_info *disp_info) 2169 { 2170 struct msm_drm_private *priv = dev->dev_private; 2171 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2172 struct drm_encoder *drm_enc = NULL; 2173 struct dpu_encoder_virt *dpu_enc = NULL; 2174 int ret = 0; 2175 2176 dpu_enc = to_dpu_encoder_virt(enc); 2177 2178 mutex_init(&dpu_enc->enc_lock); 2179 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2180 if (ret) 2181 goto fail; 2182 2183 spin_lock_init(&dpu_enc->enc_spinlock); 2184 2185 atomic_set(&dpu_enc->frame_done_timeout, 0); 2186 timer_setup(&dpu_enc->frame_done_timer, 2187 dpu_encoder_frame_done_timeout, 0); 2188 2189 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2190 timer_setup(&dpu_enc->vsync_event_timer, 2191 dpu_encoder_vsync_event_handler, 2192 0); 2193 2194 2195 mutex_init(&dpu_enc->rc_lock); 2196 kthread_init_delayed_work(&dpu_enc->delayed_off_work, 2197 dpu_encoder_off_work); 2198 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2199 2200 kthread_init_work(&dpu_enc->vsync_event_work, 2201 dpu_encoder_vsync_event_work_handler); 2202 2203 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2204 2205 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2206 2207 return ret; 2208 2209 fail: 2210 DPU_ERROR("failed to create encoder\n"); 2211 if (drm_enc) 2212 dpu_encoder_destroy(drm_enc); 2213 2214 return ret; 2215 2216 2217 } 2218 2219 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2220 int drm_enc_mode) 2221 { 2222 struct dpu_encoder_virt *dpu_enc = NULL; 2223 int rc = 0; 2224 2225 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2226 if (!dpu_enc) 2227 return ERR_PTR(ENOMEM); 2228 2229 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2230 drm_enc_mode, NULL); 2231 if (rc) { 2232 devm_kfree(dev->dev, dpu_enc); 2233 return ERR_PTR(rc); 2234 } 2235 2236 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2237 2238 dpu_enc->enabled = false; 2239 2240 return &dpu_enc->base; 2241 } 2242 2243 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2244 enum msm_event_wait event) 2245 { 2246 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2247 struct dpu_encoder_virt *dpu_enc = NULL; 2248 int i, ret = 0; 2249 2250 if (!drm_enc) { 2251 DPU_ERROR("invalid encoder\n"); 2252 return -EINVAL; 2253 } 2254 dpu_enc = to_dpu_encoder_virt(drm_enc); 2255 DPU_DEBUG_ENC(dpu_enc, "\n"); 2256 2257 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2258 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2259 if (!phys) 2260 continue; 2261 2262 switch (event) { 2263 case MSM_ENC_COMMIT_DONE: 2264 fn_wait = phys->ops.wait_for_commit_done; 2265 break; 2266 case MSM_ENC_TX_COMPLETE: 2267 fn_wait = phys->ops.wait_for_tx_complete; 2268 break; 2269 case MSM_ENC_VBLANK: 2270 fn_wait = phys->ops.wait_for_vblank; 2271 break; 2272 default: 2273 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2274 event); 2275 return -EINVAL; 2276 }; 2277 2278 if (fn_wait) { 2279 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2280 ret = fn_wait(phys); 2281 DPU_ATRACE_END("wait_for_completion_event"); 2282 if (ret) 2283 return ret; 2284 } 2285 } 2286 2287 return ret; 2288 } 2289 2290 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2291 { 2292 struct dpu_encoder_virt *dpu_enc = NULL; 2293 int i; 2294 2295 if (!encoder) { 2296 DPU_ERROR("invalid encoder\n"); 2297 return INTF_MODE_NONE; 2298 } 2299 dpu_enc = to_dpu_encoder_virt(encoder); 2300 2301 if (dpu_enc->cur_master) 2302 return dpu_enc->cur_master->intf_mode; 2303 2304 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2305 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2306 2307 if (phys) 2308 return phys->intf_mode; 2309 } 2310 2311 return INTF_MODE_NONE; 2312 } 2313