1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 9 #include <linux/debugfs.h> 10 #include <linux/kthread.h> 11 #include <linux/seq_file.h> 12 13 #include <drm/drm_crtc.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_probe_helper.h> 16 17 #include "msm_drv.h" 18 #include "dpu_kms.h" 19 #include "dpu_hwio.h" 20 #include "dpu_hw_catalog.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_ctl.h" 23 #include "dpu_formats.h" 24 #include "dpu_encoder_phys.h" 25 #include "dpu_crtc.h" 26 #include "dpu_trace.h" 27 #include "dpu_core_irq.h" 28 29 #define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ 30 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 31 32 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ 33 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) 34 35 #define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ 36 (p) ? (p)->parent->base.id : -1, \ 37 (p) ? (p)->intf_idx - INTF_0 : -1, \ 38 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 39 ##__VA_ARGS__) 40 41 #define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\ 42 (p) ? (p)->parent->base.id : -1, \ 43 (p) ? (p)->intf_idx - INTF_0 : -1, \ 44 (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ 45 ##__VA_ARGS__) 46 47 /* 48 * Two to anticipate panels that can do cmd/vid dynamic switching 49 * plan is to create all possible physical encoder types, and switch between 50 * them at runtime 51 */ 52 #define NUM_PHYS_ENCODER_TYPES 2 53 54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ 55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) 56 57 #define MAX_CHANNELS_PER_ENC 2 58 59 #define IDLE_SHORT_TIMEOUT 1 60 61 #define MAX_HDISPLAY_SPLIT 1080 62 63 /* timeout in frames waiting for frame done */ 64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5 65 66 /** 67 * enum dpu_enc_rc_events - events for resource control state machine 68 * @DPU_ENC_RC_EVENT_KICKOFF: 69 * This event happens at NORMAL priority. 70 * Event that signals the start of the transfer. When this event is 71 * received, enable MDP/DSI core clocks. Regardless of the previous 72 * state, the resource should be in ON state at the end of this event. 73 * @DPU_ENC_RC_EVENT_FRAME_DONE: 74 * This event happens at INTERRUPT level. 75 * Event signals the end of the data transfer after the PP FRAME_DONE 76 * event. At the end of this event, a delayed work is scheduled to go to 77 * IDLE_PC state after IDLE_TIMEOUT time. 78 * @DPU_ENC_RC_EVENT_PRE_STOP: 79 * This event happens at NORMAL priority. 80 * This event, when received during the ON state, leave the RC STATE 81 * in the PRE_OFF state. It should be followed by the STOP event as 82 * part of encoder disable. 83 * If received during IDLE or OFF states, it will do nothing. 84 * @DPU_ENC_RC_EVENT_STOP: 85 * This event happens at NORMAL priority. 86 * When this event is received, disable all the MDP/DSI core clocks, and 87 * disable IRQs. It should be called from the PRE_OFF or IDLE states. 88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing. 89 * PRE_OFF is expected when PRE_STOP was executed during the ON state. 90 * Resource state should be in OFF at the end of the event. 91 * @DPU_ENC_RC_EVENT_ENTER_IDLE: 92 * This event happens at NORMAL priority from a work item. 93 * Event signals that there were no frame updates for IDLE_TIMEOUT time. 94 * This would disable MDP/DSI core clocks and change the resource state 95 * to IDLE. 96 */ 97 enum dpu_enc_rc_events { 98 DPU_ENC_RC_EVENT_KICKOFF = 1, 99 DPU_ENC_RC_EVENT_FRAME_DONE, 100 DPU_ENC_RC_EVENT_PRE_STOP, 101 DPU_ENC_RC_EVENT_STOP, 102 DPU_ENC_RC_EVENT_ENTER_IDLE 103 }; 104 105 /* 106 * enum dpu_enc_rc_states - states that the resource control maintains 107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state 108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state 109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state 110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state 111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state 112 */ 113 enum dpu_enc_rc_states { 114 DPU_ENC_RC_STATE_OFF, 115 DPU_ENC_RC_STATE_PRE_OFF, 116 DPU_ENC_RC_STATE_ON, 117 DPU_ENC_RC_STATE_IDLE 118 }; 119 120 /** 121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical 122 * encoders. Virtual encoder manages one "logical" display. Physical 123 * encoders manage one intf block, tied to a specific panel/sub-panel. 124 * Virtual encoder defers as much as possible to the physical encoders. 125 * Virtual encoder registers itself with the DRM Framework as the encoder. 126 * @base: drm_encoder base class for registration with DRM 127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 128 * @bus_scaling_client: Client handle to the bus scaling interface 129 * @enabled: True if the encoder is active, protected by enc_lock 130 * @num_phys_encs: Actual number of physical encoders contained. 131 * @phys_encs: Container of physical encoders managed. 132 * @cur_master: Pointer to the current master in this mode. Optimization 133 * Only valid after enable. Cleared as disable. 134 * @hw_pp Handle to the pingpong blocks used for the display. No. 135 * pingpong blocks can be different than num_phys_encs. 136 * @intfs_swapped Whether or not the phys_enc interfaces have been swapped 137 * for partial update right-only cases, such as pingpong 138 * split where virtual pingpong does not generate IRQs 139 * @crtc: Pointer to the currently assigned crtc. Normally you 140 * would use crtc->state->encoder_mask to determine the 141 * link between encoder/crtc. However in this case we need 142 * to track crtc in the disable() hook which is called 143 * _after_ encoder_mask is cleared. 144 * @crtc_kickoff_cb: Callback into CRTC that will flush & start 145 * all CTL paths 146 * @crtc_kickoff_cb_data: Opaque user data given to crtc_kickoff_cb 147 * @debugfs_root: Debug file system root file node 148 * @enc_lock: Lock around physical encoder 149 * create/destroy/enable/disable 150 * @frame_busy_mask: Bitmask tracking which phys_enc we are still 151 * busy processing current command. 152 * Bit0 = phys_encs[0] etc. 153 * @crtc_frame_event_cb: callback handler for frame event 154 * @crtc_frame_event_cb_data: callback handler private data 155 * @frame_done_timeout_ms: frame done timeout in ms 156 * @frame_done_timer: watchdog timer for frame done event 157 * @vsync_event_timer: vsync timer 158 * @disp_info: local copy of msm_display_info struct 159 * @idle_pc_supported: indicate if idle power collaps is supported 160 * @rc_lock: resource control mutex lock to protect 161 * virt encoder over various state changes 162 * @rc_state: resource controller state 163 * @delayed_off_work: delayed worker to schedule disabling of 164 * clks and resources after IDLE_TIMEOUT time. 165 * @vsync_event_work: worker to handle vsync event for autorefresh 166 * @topology: topology of the display 167 * @idle_timeout: idle timeout duration in milliseconds 168 */ 169 struct dpu_encoder_virt { 170 struct drm_encoder base; 171 spinlock_t enc_spinlock; 172 uint32_t bus_scaling_client; 173 174 bool enabled; 175 176 unsigned int num_phys_encs; 177 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; 178 struct dpu_encoder_phys *cur_master; 179 struct dpu_encoder_phys *cur_slave; 180 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; 181 182 bool intfs_swapped; 183 184 struct drm_crtc *crtc; 185 186 struct dentry *debugfs_root; 187 struct mutex enc_lock; 188 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL); 189 void (*crtc_frame_event_cb)(void *, u32 event); 190 void *crtc_frame_event_cb_data; 191 192 atomic_t frame_done_timeout_ms; 193 struct timer_list frame_done_timer; 194 struct timer_list vsync_event_timer; 195 196 struct msm_display_info disp_info; 197 198 bool idle_pc_supported; 199 struct mutex rc_lock; 200 enum dpu_enc_rc_states rc_state; 201 struct delayed_work delayed_off_work; 202 struct kthread_work vsync_event_work; 203 struct msm_display_topology topology; 204 205 u32 idle_timeout; 206 }; 207 208 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base) 209 210 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 211 enum dpu_intr_idx intr_idx) 212 { 213 DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n", 214 DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, 215 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); 216 217 if (phys_enc->parent_ops->handle_frame_done) 218 phys_enc->parent_ops->handle_frame_done( 219 phys_enc->parent, phys_enc, 220 DPU_ENCODER_FRAME_EVENT_ERROR); 221 } 222 223 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 224 int32_t hw_id, struct dpu_encoder_wait_info *info); 225 226 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 227 enum dpu_intr_idx intr_idx, 228 struct dpu_encoder_wait_info *wait_info) 229 { 230 struct dpu_encoder_irq *irq; 231 u32 irq_status; 232 int ret; 233 234 if (!wait_info || intr_idx >= INTR_IDX_MAX) { 235 DPU_ERROR("invalid params\n"); 236 return -EINVAL; 237 } 238 irq = &phys_enc->irq[intr_idx]; 239 240 /* note: do master / slave checking outside */ 241 242 /* return EWOULDBLOCK since we know the wait isn't necessary */ 243 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 244 DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", 245 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 246 irq->irq_idx); 247 return -EWOULDBLOCK; 248 } 249 250 if (irq->irq_idx < 0) { 251 DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", 252 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 253 irq->name); 254 return 0; 255 } 256 257 DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", 258 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 259 irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, 260 atomic_read(wait_info->atomic_cnt)); 261 262 ret = dpu_encoder_helper_wait_event_timeout( 263 DRMID(phys_enc->parent), 264 irq->hw_idx, 265 wait_info); 266 267 if (ret <= 0) { 268 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, 269 irq->irq_idx, true); 270 if (irq_status) { 271 unsigned long flags; 272 273 DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " 274 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 275 DRMID(phys_enc->parent), intr_idx, 276 irq->hw_idx, irq->irq_idx, 277 phys_enc->hw_pp->idx - PINGPONG_0, 278 atomic_read(wait_info->atomic_cnt)); 279 local_irq_save(flags); 280 irq->cb.func(phys_enc, irq->irq_idx); 281 local_irq_restore(flags); 282 ret = 0; 283 } else { 284 ret = -ETIMEDOUT; 285 DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " 286 "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", 287 DRMID(phys_enc->parent), intr_idx, 288 irq->hw_idx, irq->irq_idx, 289 phys_enc->hw_pp->idx - PINGPONG_0, 290 atomic_read(wait_info->atomic_cnt)); 291 } 292 } else { 293 ret = 0; 294 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), 295 intr_idx, irq->hw_idx, irq->irq_idx, 296 phys_enc->hw_pp->idx - PINGPONG_0, 297 atomic_read(wait_info->atomic_cnt)); 298 } 299 300 return ret; 301 } 302 303 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 304 enum dpu_intr_idx intr_idx) 305 { 306 struct dpu_encoder_irq *irq; 307 int ret = 0; 308 309 if (intr_idx >= INTR_IDX_MAX) { 310 DPU_ERROR("invalid params\n"); 311 return -EINVAL; 312 } 313 irq = &phys_enc->irq[intr_idx]; 314 315 if (irq->irq_idx >= 0) { 316 DPU_DEBUG_PHYS(phys_enc, 317 "skipping already registered irq %s type %d\n", 318 irq->name, irq->intr_type); 319 return 0; 320 } 321 322 irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, 323 irq->intr_type, irq->hw_idx); 324 if (irq->irq_idx < 0) { 325 DPU_ERROR_PHYS(phys_enc, 326 "failed to lookup IRQ index for %s type:%d\n", 327 irq->name, irq->intr_type); 328 return -EINVAL; 329 } 330 331 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, 332 &irq->cb); 333 if (ret) { 334 DPU_ERROR_PHYS(phys_enc, 335 "failed to register IRQ callback for %s\n", 336 irq->name); 337 irq->irq_idx = -EINVAL; 338 return ret; 339 } 340 341 ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); 342 if (ret) { 343 DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", 344 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 345 irq->irq_idx); 346 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 347 irq->irq_idx, &irq->cb); 348 irq->irq_idx = -EINVAL; 349 return ret; 350 } 351 352 trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, 353 irq->hw_idx, irq->irq_idx); 354 355 return ret; 356 } 357 358 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 359 enum dpu_intr_idx intr_idx) 360 { 361 struct dpu_encoder_irq *irq; 362 int ret; 363 364 irq = &phys_enc->irq[intr_idx]; 365 366 /* silently skip irqs that weren't registered */ 367 if (irq->irq_idx < 0) { 368 DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", 369 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 370 irq->irq_idx); 371 return 0; 372 } 373 374 ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); 375 if (ret) { 376 DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", 377 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 378 irq->irq_idx, ret); 379 } 380 381 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, 382 &irq->cb); 383 if (ret) { 384 DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", 385 DRMID(phys_enc->parent), intr_idx, irq->hw_idx, 386 irq->irq_idx, ret); 387 } 388 389 trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, 390 irq->hw_idx, irq->irq_idx); 391 392 irq->irq_idx = -EINVAL; 393 394 return 0; 395 } 396 397 void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, 398 struct dpu_encoder_hw_resources *hw_res) 399 { 400 struct dpu_encoder_virt *dpu_enc = NULL; 401 int i = 0; 402 403 dpu_enc = to_dpu_encoder_virt(drm_enc); 404 DPU_DEBUG_ENC(dpu_enc, "\n"); 405 406 /* Query resources used by phys encs, expected to be without overlap */ 407 memset(hw_res, 0, sizeof(*hw_res)); 408 409 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 410 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 411 412 if (phys->ops.get_hw_resources) 413 phys->ops.get_hw_resources(phys, hw_res); 414 } 415 } 416 417 static void dpu_encoder_destroy(struct drm_encoder *drm_enc) 418 { 419 struct dpu_encoder_virt *dpu_enc = NULL; 420 int i = 0; 421 422 if (!drm_enc) { 423 DPU_ERROR("invalid encoder\n"); 424 return; 425 } 426 427 dpu_enc = to_dpu_encoder_virt(drm_enc); 428 DPU_DEBUG_ENC(dpu_enc, "\n"); 429 430 mutex_lock(&dpu_enc->enc_lock); 431 432 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 433 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 434 435 if (phys->ops.destroy) { 436 phys->ops.destroy(phys); 437 --dpu_enc->num_phys_encs; 438 dpu_enc->phys_encs[i] = NULL; 439 } 440 } 441 442 if (dpu_enc->num_phys_encs) 443 DPU_ERROR_ENC(dpu_enc, "expected 0 num_phys_encs not %d\n", 444 dpu_enc->num_phys_encs); 445 dpu_enc->num_phys_encs = 0; 446 mutex_unlock(&dpu_enc->enc_lock); 447 448 drm_encoder_cleanup(drm_enc); 449 mutex_destroy(&dpu_enc->enc_lock); 450 } 451 452 void dpu_encoder_helper_split_config( 453 struct dpu_encoder_phys *phys_enc, 454 enum dpu_intf interface) 455 { 456 struct dpu_encoder_virt *dpu_enc; 457 struct split_pipe_cfg cfg = { 0 }; 458 struct dpu_hw_mdp *hw_mdptop; 459 struct msm_display_info *disp_info; 460 461 if (!phys_enc->hw_mdptop || !phys_enc->parent) { 462 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL); 463 return; 464 } 465 466 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 467 hw_mdptop = phys_enc->hw_mdptop; 468 disp_info = &dpu_enc->disp_info; 469 470 if (disp_info->intf_type != DRM_MODE_ENCODER_DSI) 471 return; 472 473 /** 474 * disable split modes since encoder will be operating in as the only 475 * encoder, either for the entire use case in the case of, for example, 476 * single DSI, or for this frame in the case of left/right only partial 477 * update. 478 */ 479 if (phys_enc->split_role == ENC_ROLE_SOLO) { 480 if (hw_mdptop->ops.setup_split_pipe) 481 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 482 return; 483 } 484 485 cfg.en = true; 486 cfg.mode = phys_enc->intf_mode; 487 cfg.intf = interface; 488 489 if (cfg.en && phys_enc->ops.needs_single_flush && 490 phys_enc->ops.needs_single_flush(phys_enc)) 491 cfg.split_flush_en = true; 492 493 if (phys_enc->split_role == ENC_ROLE_MASTER) { 494 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); 495 496 if (hw_mdptop->ops.setup_split_pipe) 497 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); 498 } 499 } 500 501 static struct msm_display_topology dpu_encoder_get_topology( 502 struct dpu_encoder_virt *dpu_enc, 503 struct dpu_kms *dpu_kms, 504 struct drm_display_mode *mode) 505 { 506 struct msm_display_topology topology; 507 int i, intf_count = 0; 508 509 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) 510 if (dpu_enc->phys_encs[i]) 511 intf_count++; 512 513 /* Datapath topology selection 514 * 515 * Dual display 516 * 2 LM, 2 INTF ( Split display using 2 interfaces) 517 * 518 * Single display 519 * 1 LM, 1 INTF 520 * 2 LM, 1 INTF (stream merge to support high resolution interfaces) 521 * 522 */ 523 if (intf_count == 2) 524 topology.num_lm = 2; 525 else if (!dpu_kms->catalog->caps->has_3d_merge) 526 topology.num_lm = 1; 527 else 528 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; 529 530 topology.num_enc = 0; 531 topology.num_intf = intf_count; 532 533 return topology; 534 } 535 static int dpu_encoder_virt_atomic_check( 536 struct drm_encoder *drm_enc, 537 struct drm_crtc_state *crtc_state, 538 struct drm_connector_state *conn_state) 539 { 540 struct dpu_encoder_virt *dpu_enc; 541 struct msm_drm_private *priv; 542 struct dpu_kms *dpu_kms; 543 const struct drm_display_mode *mode; 544 struct drm_display_mode *adj_mode; 545 struct msm_display_topology topology; 546 struct dpu_global_state *global_state; 547 int i = 0; 548 int ret = 0; 549 550 if (!drm_enc || !crtc_state || !conn_state) { 551 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n", 552 drm_enc != NULL, crtc_state != NULL, conn_state != NULL); 553 return -EINVAL; 554 } 555 556 dpu_enc = to_dpu_encoder_virt(drm_enc); 557 DPU_DEBUG_ENC(dpu_enc, "\n"); 558 559 priv = drm_enc->dev->dev_private; 560 dpu_kms = to_dpu_kms(priv->kms); 561 mode = &crtc_state->mode; 562 adj_mode = &crtc_state->adjusted_mode; 563 global_state = dpu_kms_get_existing_global_state(dpu_kms); 564 trace_dpu_enc_atomic_check(DRMID(drm_enc)); 565 566 /* perform atomic check on the first physical encoder (master) */ 567 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 568 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 569 570 if (phys->ops.atomic_check) 571 ret = phys->ops.atomic_check(phys, crtc_state, 572 conn_state); 573 else if (phys->ops.mode_fixup) 574 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) 575 ret = -EINVAL; 576 577 if (ret) { 578 DPU_ERROR_ENC(dpu_enc, 579 "mode unsupported, phys idx %d\n", i); 580 break; 581 } 582 } 583 584 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 585 586 /* Reserve dynamic resources now. */ 587 if (!ret) { 588 /* 589 * Avoid reserving resources when mode set is pending. Topology 590 * info may not be available to complete reservation. 591 */ 592 if (drm_atomic_crtc_needs_modeset(crtc_state)) { 593 ret = dpu_rm_reserve(&dpu_kms->rm, global_state, 594 drm_enc, crtc_state, topology); 595 } 596 } 597 598 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); 599 600 return ret; 601 } 602 603 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, 604 struct msm_display_info *disp_info) 605 { 606 struct dpu_vsync_source_cfg vsync_cfg = { 0 }; 607 struct msm_drm_private *priv; 608 struct dpu_kms *dpu_kms; 609 struct dpu_hw_mdp *hw_mdptop; 610 struct drm_encoder *drm_enc; 611 int i; 612 613 if (!dpu_enc || !disp_info) { 614 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n", 615 dpu_enc != NULL, disp_info != NULL); 616 return; 617 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) { 618 DPU_ERROR("invalid num phys enc %d/%d\n", 619 dpu_enc->num_phys_encs, 620 (int) ARRAY_SIZE(dpu_enc->hw_pp)); 621 return; 622 } 623 624 drm_enc = &dpu_enc->base; 625 /* this pointers are checked in virt_enable_helper */ 626 priv = drm_enc->dev->dev_private; 627 628 dpu_kms = to_dpu_kms(priv->kms); 629 hw_mdptop = dpu_kms->hw_mdp; 630 if (!hw_mdptop) { 631 DPU_ERROR("invalid mdptop\n"); 632 return; 633 } 634 635 if (hw_mdptop->ops.setup_vsync_source && 636 disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { 637 for (i = 0; i < dpu_enc->num_phys_encs; i++) 638 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; 639 640 vsync_cfg.pp_count = dpu_enc->num_phys_encs; 641 if (disp_info->is_te_using_watchdog_timer) 642 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; 643 else 644 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; 645 646 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); 647 } 648 } 649 650 static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 651 { 652 struct dpu_encoder_virt *dpu_enc; 653 int i; 654 655 if (!drm_enc) { 656 DPU_ERROR("invalid encoder\n"); 657 return; 658 } 659 660 dpu_enc = to_dpu_encoder_virt(drm_enc); 661 662 DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 663 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 664 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 665 666 if (phys->ops.irq_control) 667 phys->ops.irq_control(phys, enable); 668 } 669 670 } 671 672 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, 673 bool enable) 674 { 675 struct msm_drm_private *priv; 676 struct dpu_kms *dpu_kms; 677 struct dpu_encoder_virt *dpu_enc; 678 679 dpu_enc = to_dpu_encoder_virt(drm_enc); 680 priv = drm_enc->dev->dev_private; 681 dpu_kms = to_dpu_kms(priv->kms); 682 683 trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); 684 685 if (!dpu_enc->cur_master) { 686 DPU_ERROR("encoder master not set\n"); 687 return; 688 } 689 690 if (enable) { 691 /* enable DPU core clks */ 692 pm_runtime_get_sync(&dpu_kms->pdev->dev); 693 694 /* enable all the irq */ 695 _dpu_encoder_irq_control(drm_enc, true); 696 697 } else { 698 /* disable all the irq */ 699 _dpu_encoder_irq_control(drm_enc, false); 700 701 /* disable DPU core clks */ 702 pm_runtime_put_sync(&dpu_kms->pdev->dev); 703 } 704 705 } 706 707 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, 708 u32 sw_event) 709 { 710 struct dpu_encoder_virt *dpu_enc; 711 struct msm_drm_private *priv; 712 bool is_vid_mode = false; 713 714 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) { 715 DPU_ERROR("invalid parameters\n"); 716 return -EINVAL; 717 } 718 dpu_enc = to_dpu_encoder_virt(drm_enc); 719 priv = drm_enc->dev->dev_private; 720 is_vid_mode = dpu_enc->disp_info.capabilities & 721 MSM_DISPLAY_CAP_VID_MODE; 722 723 /* 724 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET 725 * events and return early for other events (ie wb display). 726 */ 727 if (!dpu_enc->idle_pc_supported && 728 (sw_event != DPU_ENC_RC_EVENT_KICKOFF && 729 sw_event != DPU_ENC_RC_EVENT_STOP && 730 sw_event != DPU_ENC_RC_EVENT_PRE_STOP)) 731 return 0; 732 733 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported, 734 dpu_enc->rc_state, "begin"); 735 736 switch (sw_event) { 737 case DPU_ENC_RC_EVENT_KICKOFF: 738 /* cancel delayed off work, if any */ 739 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 740 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 741 sw_event); 742 743 mutex_lock(&dpu_enc->rc_lock); 744 745 /* return if the resource control is already in ON state */ 746 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 747 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", 748 DRMID(drm_enc), sw_event); 749 mutex_unlock(&dpu_enc->rc_lock); 750 return 0; 751 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && 752 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { 753 DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", 754 DRMID(drm_enc), sw_event, 755 dpu_enc->rc_state); 756 mutex_unlock(&dpu_enc->rc_lock); 757 return -EINVAL; 758 } 759 760 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 761 _dpu_encoder_irq_control(drm_enc, true); 762 else 763 _dpu_encoder_resource_control_helper(drm_enc, true); 764 765 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; 766 767 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 768 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 769 "kickoff"); 770 771 mutex_unlock(&dpu_enc->rc_lock); 772 break; 773 774 case DPU_ENC_RC_EVENT_FRAME_DONE: 775 /* 776 * mutex lock is not used as this event happens at interrupt 777 * context. And locking is not required as, the other events 778 * like KICKOFF and STOP does a wait-for-idle before executing 779 * the resource_control 780 */ 781 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 782 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n", 783 DRMID(drm_enc), sw_event, 784 dpu_enc->rc_state); 785 return -EINVAL; 786 } 787 788 /* 789 * schedule off work item only when there are no 790 * frames pending 791 */ 792 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) { 793 DRM_DEBUG_KMS("id:%d skip schedule work\n", 794 DRMID(drm_enc)); 795 return 0; 796 } 797 798 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work, 799 msecs_to_jiffies(dpu_enc->idle_timeout)); 800 801 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 802 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 803 "frame done"); 804 break; 805 806 case DPU_ENC_RC_EVENT_PRE_STOP: 807 /* cancel delayed off work, if any */ 808 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work)) 809 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n", 810 sw_event); 811 812 mutex_lock(&dpu_enc->rc_lock); 813 814 if (is_vid_mode && 815 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 816 _dpu_encoder_irq_control(drm_enc, true); 817 } 818 /* skip if is already OFF or IDLE, resources are off already */ 819 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || 820 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 821 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n", 822 DRMID(drm_enc), sw_event, 823 dpu_enc->rc_state); 824 mutex_unlock(&dpu_enc->rc_lock); 825 return 0; 826 } 827 828 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF; 829 830 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 831 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 832 "pre stop"); 833 834 mutex_unlock(&dpu_enc->rc_lock); 835 break; 836 837 case DPU_ENC_RC_EVENT_STOP: 838 mutex_lock(&dpu_enc->rc_lock); 839 840 /* return if the resource control is already in OFF state */ 841 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) { 842 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n", 843 DRMID(drm_enc), sw_event); 844 mutex_unlock(&dpu_enc->rc_lock); 845 return 0; 846 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { 847 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n", 848 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 849 mutex_unlock(&dpu_enc->rc_lock); 850 return -EINVAL; 851 } 852 853 /** 854 * expect to arrive here only if in either idle state or pre-off 855 * and in IDLE state the resources are already disabled 856 */ 857 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) 858 _dpu_encoder_resource_control_helper(drm_enc, false); 859 860 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; 861 862 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 863 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 864 "stop"); 865 866 mutex_unlock(&dpu_enc->rc_lock); 867 break; 868 869 case DPU_ENC_RC_EVENT_ENTER_IDLE: 870 mutex_lock(&dpu_enc->rc_lock); 871 872 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) { 873 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n", 874 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 875 mutex_unlock(&dpu_enc->rc_lock); 876 return 0; 877 } 878 879 /* 880 * if we are in ON but a frame was just kicked off, 881 * ignore the IDLE event, it's probably a stale timer event 882 */ 883 if (dpu_enc->frame_busy_mask[0]) { 884 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n", 885 DRMID(drm_enc), sw_event, dpu_enc->rc_state); 886 mutex_unlock(&dpu_enc->rc_lock); 887 return 0; 888 } 889 890 if (is_vid_mode) 891 _dpu_encoder_irq_control(drm_enc, false); 892 else 893 _dpu_encoder_resource_control_helper(drm_enc, false); 894 895 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; 896 897 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 898 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 899 "idle"); 900 901 mutex_unlock(&dpu_enc->rc_lock); 902 break; 903 904 default: 905 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc), 906 sw_event); 907 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 908 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 909 "error"); 910 break; 911 } 912 913 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, 914 dpu_enc->idle_pc_supported, dpu_enc->rc_state, 915 "end"); 916 return 0; 917 } 918 919 static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 920 struct drm_display_mode *mode, 921 struct drm_display_mode *adj_mode) 922 { 923 struct dpu_encoder_virt *dpu_enc; 924 struct msm_drm_private *priv; 925 struct dpu_kms *dpu_kms; 926 struct list_head *connector_list; 927 struct drm_connector *conn = NULL, *conn_iter; 928 struct drm_crtc *drm_crtc; 929 struct dpu_crtc_state *cstate; 930 struct dpu_global_state *global_state; 931 struct msm_display_topology topology; 932 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; 933 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; 934 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; 935 int num_lm, num_ctl, num_pp; 936 int i, j; 937 938 if (!drm_enc) { 939 DPU_ERROR("invalid encoder\n"); 940 return; 941 } 942 943 dpu_enc = to_dpu_encoder_virt(drm_enc); 944 DPU_DEBUG_ENC(dpu_enc, "\n"); 945 946 priv = drm_enc->dev->dev_private; 947 dpu_kms = to_dpu_kms(priv->kms); 948 connector_list = &dpu_kms->dev->mode_config.connector_list; 949 950 global_state = dpu_kms_get_existing_global_state(dpu_kms); 951 if (IS_ERR_OR_NULL(global_state)) { 952 DPU_ERROR("Failed to get global state"); 953 return; 954 } 955 956 trace_dpu_enc_mode_set(DRMID(drm_enc)); 957 958 list_for_each_entry(conn_iter, connector_list, head) 959 if (conn_iter->encoder == drm_enc) 960 conn = conn_iter; 961 962 if (!conn) { 963 DPU_ERROR_ENC(dpu_enc, "failed to find attached connector\n"); 964 return; 965 } else if (!conn->state) { 966 DPU_ERROR_ENC(dpu_enc, "invalid connector state\n"); 967 return; 968 } 969 970 drm_for_each_crtc(drm_crtc, drm_enc->dev) 971 if (drm_crtc->state->encoder_mask & drm_encoder_mask(drm_enc)) 972 break; 973 974 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); 975 976 /* Query resource that have been reserved in atomic check step. */ 977 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 978 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, 979 ARRAY_SIZE(hw_pp)); 980 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 981 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); 982 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, 983 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); 984 985 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) 986 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) 987 : NULL; 988 989 cstate = to_dpu_crtc_state(drm_crtc->state); 990 991 for (i = 0; i < num_lm; i++) { 992 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1); 993 994 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); 995 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); 996 } 997 998 cstate->num_mixers = num_lm; 999 1000 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1001 int num_blk; 1002 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; 1003 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1004 1005 if (!dpu_enc->hw_pp[i]) { 1006 DPU_ERROR_ENC(dpu_enc, 1007 "no pp block assigned at idx: %d\n", i); 1008 return; 1009 } 1010 1011 if (!hw_ctl[i]) { 1012 DPU_ERROR_ENC(dpu_enc, 1013 "no ctl block assigned at idx: %d\n", i); 1014 return; 1015 } 1016 1017 phys->hw_pp = dpu_enc->hw_pp[i]; 1018 phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); 1019 1020 num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm, 1021 global_state, drm_enc->base.id, DPU_HW_BLK_INTF, 1022 hw_blk, ARRAY_SIZE(hw_blk)); 1023 for (j = 0; j < num_blk; j++) { 1024 struct dpu_hw_intf *hw_intf; 1025 1026 hw_intf = to_dpu_hw_intf(hw_blk[i]); 1027 if (hw_intf->idx == phys->intf_idx) 1028 phys->hw_intf = hw_intf; 1029 } 1030 1031 if (!phys->hw_intf) { 1032 DPU_ERROR_ENC(dpu_enc, 1033 "no intf block assigned at idx: %d\n", i); 1034 return; 1035 } 1036 1037 phys->connector = conn->state->connector; 1038 if (phys->ops.mode_set) 1039 phys->ops.mode_set(phys, mode, adj_mode); 1040 } 1041 } 1042 1043 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) 1044 { 1045 struct dpu_encoder_virt *dpu_enc = NULL; 1046 struct msm_drm_private *priv; 1047 struct dpu_kms *dpu_kms; 1048 1049 if (!drm_enc || !drm_enc->dev) { 1050 DPU_ERROR("invalid parameters\n"); 1051 return; 1052 } 1053 1054 priv = drm_enc->dev->dev_private; 1055 dpu_kms = to_dpu_kms(priv->kms); 1056 1057 dpu_enc = to_dpu_encoder_virt(drm_enc); 1058 if (!dpu_enc || !dpu_enc->cur_master) { 1059 DPU_ERROR("invalid dpu encoder/master\n"); 1060 return; 1061 } 1062 1063 if (dpu_enc->cur_master->hw_mdptop && 1064 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc) 1065 dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc( 1066 dpu_enc->cur_master->hw_mdptop, 1067 dpu_kms->catalog); 1068 1069 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); 1070 } 1071 1072 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1073 { 1074 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1075 1076 mutex_lock(&dpu_enc->enc_lock); 1077 1078 if (!dpu_enc->enabled) 1079 goto out; 1080 1081 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore) 1082 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave); 1083 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore) 1084 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master); 1085 1086 _dpu_encoder_virt_enable_helper(drm_enc); 1087 1088 out: 1089 mutex_unlock(&dpu_enc->enc_lock); 1090 } 1091 1092 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc) 1093 { 1094 struct dpu_encoder_virt *dpu_enc = NULL; 1095 int ret = 0; 1096 struct drm_display_mode *cur_mode = NULL; 1097 1098 if (!drm_enc) { 1099 DPU_ERROR("invalid encoder\n"); 1100 return; 1101 } 1102 dpu_enc = to_dpu_encoder_virt(drm_enc); 1103 1104 mutex_lock(&dpu_enc->enc_lock); 1105 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; 1106 1107 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, 1108 cur_mode->vdisplay); 1109 1110 /* always enable slave encoder before master */ 1111 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable) 1112 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave); 1113 1114 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable) 1115 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master); 1116 1117 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1118 if (ret) { 1119 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n", 1120 ret); 1121 goto out; 1122 } 1123 1124 _dpu_encoder_virt_enable_helper(drm_enc); 1125 1126 dpu_enc->enabled = true; 1127 1128 out: 1129 mutex_unlock(&dpu_enc->enc_lock); 1130 } 1131 1132 static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) 1133 { 1134 struct dpu_encoder_virt *dpu_enc = NULL; 1135 struct msm_drm_private *priv; 1136 struct dpu_kms *dpu_kms; 1137 struct dpu_global_state *global_state; 1138 int i = 0; 1139 1140 if (!drm_enc) { 1141 DPU_ERROR("invalid encoder\n"); 1142 return; 1143 } else if (!drm_enc->dev) { 1144 DPU_ERROR("invalid dev\n"); 1145 return; 1146 } 1147 1148 dpu_enc = to_dpu_encoder_virt(drm_enc); 1149 DPU_DEBUG_ENC(dpu_enc, "\n"); 1150 1151 mutex_lock(&dpu_enc->enc_lock); 1152 dpu_enc->enabled = false; 1153 1154 priv = drm_enc->dev->dev_private; 1155 dpu_kms = to_dpu_kms(priv->kms); 1156 global_state = dpu_kms_get_existing_global_state(dpu_kms); 1157 1158 trace_dpu_enc_disable(DRMID(drm_enc)); 1159 1160 /* wait for idle */ 1161 dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); 1162 1163 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); 1164 1165 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1166 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1167 1168 if (phys->ops.disable) 1169 phys->ops.disable(phys); 1170 } 1171 1172 /* after phys waits for frame-done, should be no more frames pending */ 1173 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 1174 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id); 1175 del_timer_sync(&dpu_enc->frame_done_timer); 1176 } 1177 1178 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP); 1179 1180 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1181 dpu_enc->phys_encs[i]->connector = NULL; 1182 } 1183 1184 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n"); 1185 1186 dpu_rm_release(global_state, drm_enc); 1187 1188 mutex_unlock(&dpu_enc->enc_lock); 1189 } 1190 1191 static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, 1192 enum dpu_intf_type type, u32 controller_id) 1193 { 1194 int i = 0; 1195 1196 for (i = 0; i < catalog->intf_count; i++) { 1197 if (catalog->intf[i].type == type 1198 && catalog->intf[i].controller_id == controller_id) { 1199 return catalog->intf[i].id; 1200 } 1201 } 1202 1203 return INTF_MAX; 1204 } 1205 1206 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1207 struct dpu_encoder_phys *phy_enc) 1208 { 1209 struct dpu_encoder_virt *dpu_enc = NULL; 1210 unsigned long lock_flags; 1211 1212 if (!drm_enc || !phy_enc) 1213 return; 1214 1215 DPU_ATRACE_BEGIN("encoder_vblank_callback"); 1216 dpu_enc = to_dpu_encoder_virt(drm_enc); 1217 1218 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1219 if (dpu_enc->crtc) 1220 dpu_crtc_vblank_callback(dpu_enc->crtc); 1221 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1222 1223 atomic_inc(&phy_enc->vsync_cnt); 1224 DPU_ATRACE_END("encoder_vblank_callback"); 1225 } 1226 1227 static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1228 struct dpu_encoder_phys *phy_enc) 1229 { 1230 if (!phy_enc) 1231 return; 1232 1233 DPU_ATRACE_BEGIN("encoder_underrun_callback"); 1234 atomic_inc(&phy_enc->underrun_cnt); 1235 trace_dpu_enc_underrun_cb(DRMID(drm_enc), 1236 atomic_read(&phy_enc->underrun_cnt)); 1237 DPU_ATRACE_END("encoder_underrun_callback"); 1238 } 1239 1240 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1241 { 1242 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1243 unsigned long lock_flags; 1244 1245 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1246 /* crtc should always be cleared before re-assigning */ 1247 WARN_ON(crtc && dpu_enc->crtc); 1248 dpu_enc->crtc = crtc; 1249 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1250 } 1251 1252 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1253 struct drm_crtc *crtc, bool enable) 1254 { 1255 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1256 unsigned long lock_flags; 1257 int i; 1258 1259 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable); 1260 1261 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1262 if (dpu_enc->crtc != crtc) { 1263 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1264 return; 1265 } 1266 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1267 1268 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1269 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1270 1271 if (phys->ops.control_vblank_irq) 1272 phys->ops.control_vblank_irq(phys, enable); 1273 } 1274 } 1275 1276 void dpu_encoder_register_frame_event_callback(struct drm_encoder *drm_enc, 1277 void (*frame_event_cb)(void *, u32 event), 1278 void *frame_event_cb_data) 1279 { 1280 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1281 unsigned long lock_flags; 1282 bool enable; 1283 1284 enable = frame_event_cb ? true : false; 1285 1286 if (!drm_enc) { 1287 DPU_ERROR("invalid encoder\n"); 1288 return; 1289 } 1290 trace_dpu_enc_frame_event_cb(DRMID(drm_enc), enable); 1291 1292 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1293 dpu_enc->crtc_frame_event_cb = frame_event_cb; 1294 dpu_enc->crtc_frame_event_cb_data = frame_event_cb_data; 1295 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1296 } 1297 1298 static void dpu_encoder_frame_done_callback( 1299 struct drm_encoder *drm_enc, 1300 struct dpu_encoder_phys *ready_phys, u32 event) 1301 { 1302 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1303 unsigned int i; 1304 1305 if (event & (DPU_ENCODER_FRAME_EVENT_DONE 1306 | DPU_ENCODER_FRAME_EVENT_ERROR 1307 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 1308 1309 if (!dpu_enc->frame_busy_mask[0]) { 1310 /** 1311 * suppress frame_done without waiter, 1312 * likely autorefresh 1313 */ 1314 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 1315 event, ready_phys->intf_idx); 1316 return; 1317 } 1318 1319 /* One of the physical encoders has become idle */ 1320 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1321 if (dpu_enc->phys_encs[i] == ready_phys) { 1322 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i, 1323 dpu_enc->frame_busy_mask[0]); 1324 clear_bit(i, dpu_enc->frame_busy_mask); 1325 } 1326 } 1327 1328 if (!dpu_enc->frame_busy_mask[0]) { 1329 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 1330 del_timer(&dpu_enc->frame_done_timer); 1331 1332 dpu_encoder_resource_control(drm_enc, 1333 DPU_ENC_RC_EVENT_FRAME_DONE); 1334 1335 if (dpu_enc->crtc_frame_event_cb) 1336 dpu_enc->crtc_frame_event_cb( 1337 dpu_enc->crtc_frame_event_cb_data, 1338 event); 1339 } 1340 } else { 1341 if (dpu_enc->crtc_frame_event_cb) 1342 dpu_enc->crtc_frame_event_cb( 1343 dpu_enc->crtc_frame_event_cb_data, event); 1344 } 1345 } 1346 1347 static void dpu_encoder_off_work(struct work_struct *work) 1348 { 1349 struct dpu_encoder_virt *dpu_enc = container_of(work, 1350 struct dpu_encoder_virt, delayed_off_work.work); 1351 1352 if (!dpu_enc) { 1353 DPU_ERROR("invalid dpu encoder\n"); 1354 return; 1355 } 1356 1357 dpu_encoder_resource_control(&dpu_enc->base, 1358 DPU_ENC_RC_EVENT_ENTER_IDLE); 1359 1360 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL, 1361 DPU_ENCODER_FRAME_EVENT_IDLE); 1362 } 1363 1364 /** 1365 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder 1366 * drm_enc: Pointer to drm encoder structure 1367 * phys: Pointer to physical encoder structure 1368 * extra_flush_bits: Additional bit mask to include in flush trigger 1369 */ 1370 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 1371 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) 1372 { 1373 struct dpu_hw_ctl *ctl; 1374 int pending_kickoff_cnt; 1375 u32 ret = UINT_MAX; 1376 1377 if (!phys->hw_pp) { 1378 DPU_ERROR("invalid pingpong hw\n"); 1379 return; 1380 } 1381 1382 ctl = phys->hw_ctl; 1383 if (!ctl->ops.trigger_flush) { 1384 DPU_ERROR("missing trigger cb\n"); 1385 return; 1386 } 1387 1388 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); 1389 1390 if (extra_flush_bits && ctl->ops.update_pending_flush) 1391 ctl->ops.update_pending_flush(ctl, extra_flush_bits); 1392 1393 ctl->ops.trigger_flush(ctl); 1394 1395 if (ctl->ops.get_pending_flush) 1396 ret = ctl->ops.get_pending_flush(ctl); 1397 1398 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, 1399 pending_kickoff_cnt, ctl->idx, 1400 extra_flush_bits, ret); 1401 } 1402 1403 /** 1404 * _dpu_encoder_trigger_start - trigger start for a physical encoder 1405 * phys: Pointer to physical encoder structure 1406 */ 1407 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) 1408 { 1409 if (!phys) { 1410 DPU_ERROR("invalid argument(s)\n"); 1411 return; 1412 } 1413 1414 if (!phys->hw_pp) { 1415 DPU_ERROR("invalid pingpong hw\n"); 1416 return; 1417 } 1418 1419 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) 1420 phys->ops.trigger_start(phys); 1421 } 1422 1423 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1424 { 1425 struct dpu_hw_ctl *ctl; 1426 1427 ctl = phys_enc->hw_ctl; 1428 if (ctl->ops.trigger_start) { 1429 ctl->ops.trigger_start(ctl); 1430 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); 1431 } 1432 } 1433 1434 static int dpu_encoder_helper_wait_event_timeout( 1435 int32_t drm_id, 1436 int32_t hw_id, 1437 struct dpu_encoder_wait_info *info) 1438 { 1439 int rc = 0; 1440 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms; 1441 s64 jiffies = msecs_to_jiffies(info->timeout_ms); 1442 s64 time; 1443 1444 do { 1445 rc = wait_event_timeout(*(info->wq), 1446 atomic_read(info->atomic_cnt) == 0, jiffies); 1447 time = ktime_to_ms(ktime_get()); 1448 1449 trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, 1450 expected_time, 1451 atomic_read(info->atomic_cnt)); 1452 /* If we timed out, counter is valid and time is less, wait again */ 1453 } while (atomic_read(info->atomic_cnt) && (rc == 0) && 1454 (time < expected_time)); 1455 1456 return rc; 1457 } 1458 1459 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) 1460 { 1461 struct dpu_encoder_virt *dpu_enc; 1462 struct dpu_hw_ctl *ctl; 1463 int rc; 1464 1465 dpu_enc = to_dpu_encoder_virt(phys_enc->parent); 1466 ctl = phys_enc->hw_ctl; 1467 1468 if (!ctl->ops.reset) 1469 return; 1470 1471 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), 1472 ctl->idx); 1473 1474 rc = ctl->ops.reset(ctl); 1475 if (rc) 1476 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); 1477 1478 phys_enc->enable_state = DPU_ENC_ENABLED; 1479 } 1480 1481 /** 1482 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff 1483 * Iterate through the physical encoders and perform consolidated flush 1484 * and/or control start triggering as needed. This is done in the virtual 1485 * encoder rather than the individual physical ones in order to handle 1486 * use cases that require visibility into multiple physical encoders at 1487 * a time. 1488 * dpu_enc: Pointer to virtual encoder structure 1489 */ 1490 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc) 1491 { 1492 struct dpu_hw_ctl *ctl; 1493 uint32_t i, pending_flush; 1494 unsigned long lock_flags; 1495 1496 pending_flush = 0x0; 1497 1498 /* update pending counts and trigger kickoff ctl flush atomically */ 1499 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags); 1500 1501 /* don't perform flush/start operations for slave encoders */ 1502 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1503 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1504 1505 if (phys->enable_state == DPU_ENC_DISABLED) 1506 continue; 1507 1508 ctl = phys->hw_ctl; 1509 1510 /* 1511 * This is cleared in frame_done worker, which isn't invoked 1512 * for async commits. So don't set this for async, since it'll 1513 * roll over to the next commit. 1514 */ 1515 if (phys->split_role != ENC_ROLE_SLAVE) 1516 set_bit(i, dpu_enc->frame_busy_mask); 1517 1518 if (!phys->ops.needs_single_flush || 1519 !phys->ops.needs_single_flush(phys)) 1520 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); 1521 else if (ctl->ops.get_pending_flush) 1522 pending_flush |= ctl->ops.get_pending_flush(ctl); 1523 } 1524 1525 /* for split flush, combine pending flush masks and send to master */ 1526 if (pending_flush && dpu_enc->cur_master) { 1527 _dpu_encoder_trigger_flush( 1528 &dpu_enc->base, 1529 dpu_enc->cur_master, 1530 pending_flush); 1531 } 1532 1533 _dpu_encoder_trigger_start(dpu_enc->cur_master); 1534 1535 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1536 } 1537 1538 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1539 { 1540 struct dpu_encoder_virt *dpu_enc; 1541 struct dpu_encoder_phys *phys; 1542 unsigned int i; 1543 struct dpu_hw_ctl *ctl; 1544 struct msm_display_info *disp_info; 1545 1546 if (!drm_enc) { 1547 DPU_ERROR("invalid encoder\n"); 1548 return; 1549 } 1550 dpu_enc = to_dpu_encoder_virt(drm_enc); 1551 disp_info = &dpu_enc->disp_info; 1552 1553 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1554 phys = dpu_enc->phys_encs[i]; 1555 1556 ctl = phys->hw_ctl; 1557 if (ctl->ops.clear_pending_flush) 1558 ctl->ops.clear_pending_flush(ctl); 1559 1560 /* update only for command mode primary ctl */ 1561 if ((phys == dpu_enc->cur_master) && 1562 (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) 1563 && ctl->ops.trigger_pending) 1564 ctl->ops.trigger_pending(ctl); 1565 } 1566 } 1567 1568 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc, 1569 struct drm_display_mode *mode) 1570 { 1571 u64 pclk_rate; 1572 u32 pclk_period; 1573 u32 line_time; 1574 1575 /* 1576 * For linetime calculation, only operate on master encoder. 1577 */ 1578 if (!dpu_enc->cur_master) 1579 return 0; 1580 1581 if (!dpu_enc->cur_master->ops.get_line_count) { 1582 DPU_ERROR("get_line_count function not defined\n"); 1583 return 0; 1584 } 1585 1586 pclk_rate = mode->clock; /* pixel clock in kHz */ 1587 if (pclk_rate == 0) { 1588 DPU_ERROR("pclk is 0, cannot calculate line time\n"); 1589 return 0; 1590 } 1591 1592 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); 1593 if (pclk_period == 0) { 1594 DPU_ERROR("pclk period is 0\n"); 1595 return 0; 1596 } 1597 1598 /* 1599 * Line time calculation based on Pixel clock and HTOTAL. 1600 * Final unit is in ns. 1601 */ 1602 line_time = (pclk_period * mode->htotal) / 1000; 1603 if (line_time == 0) { 1604 DPU_ERROR("line time calculation is 0\n"); 1605 return 0; 1606 } 1607 1608 DPU_DEBUG_ENC(dpu_enc, 1609 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n", 1610 pclk_rate, pclk_period, line_time); 1611 1612 return line_time; 1613 } 1614 1615 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1616 { 1617 struct drm_display_mode *mode; 1618 struct dpu_encoder_virt *dpu_enc; 1619 u32 cur_line; 1620 u32 line_time; 1621 u32 vtotal, time_to_vsync; 1622 ktime_t cur_time; 1623 1624 dpu_enc = to_dpu_encoder_virt(drm_enc); 1625 1626 if (!drm_enc->crtc || !drm_enc->crtc->state) { 1627 DPU_ERROR("crtc/crtc state object is NULL\n"); 1628 return -EINVAL; 1629 } 1630 mode = &drm_enc->crtc->state->adjusted_mode; 1631 1632 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode); 1633 if (!line_time) 1634 return -EINVAL; 1635 1636 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master); 1637 1638 vtotal = mode->vtotal; 1639 if (cur_line >= vtotal) 1640 time_to_vsync = line_time * vtotal; 1641 else 1642 time_to_vsync = line_time * (vtotal - cur_line); 1643 1644 if (time_to_vsync == 0) { 1645 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n", 1646 vtotal); 1647 return -EINVAL; 1648 } 1649 1650 cur_time = ktime_get(); 1651 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync); 1652 1653 DPU_DEBUG_ENC(dpu_enc, 1654 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n", 1655 cur_line, vtotal, time_to_vsync, 1656 ktime_to_ms(cur_time), 1657 ktime_to_ms(*wakeup_time)); 1658 return 0; 1659 } 1660 1661 static void dpu_encoder_vsync_event_handler(struct timer_list *t) 1662 { 1663 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 1664 vsync_event_timer); 1665 struct drm_encoder *drm_enc = &dpu_enc->base; 1666 struct msm_drm_private *priv; 1667 struct msm_drm_thread *event_thread; 1668 1669 if (!drm_enc->dev || !drm_enc->crtc) { 1670 DPU_ERROR("invalid parameters\n"); 1671 return; 1672 } 1673 1674 priv = drm_enc->dev->dev_private; 1675 1676 if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { 1677 DPU_ERROR("invalid crtc index\n"); 1678 return; 1679 } 1680 event_thread = &priv->event_thread[drm_enc->crtc->index]; 1681 if (!event_thread) { 1682 DPU_ERROR("event_thread not found for crtc:%d\n", 1683 drm_enc->crtc->index); 1684 return; 1685 } 1686 1687 del_timer(&dpu_enc->vsync_event_timer); 1688 } 1689 1690 static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) 1691 { 1692 struct dpu_encoder_virt *dpu_enc = container_of(work, 1693 struct dpu_encoder_virt, vsync_event_work); 1694 ktime_t wakeup_time; 1695 1696 if (!dpu_enc) { 1697 DPU_ERROR("invalid dpu encoder\n"); 1698 return; 1699 } 1700 1701 if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) 1702 return; 1703 1704 trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); 1705 mod_timer(&dpu_enc->vsync_event_timer, 1706 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1707 } 1708 1709 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 1710 { 1711 struct dpu_encoder_virt *dpu_enc; 1712 struct dpu_encoder_phys *phys; 1713 bool needs_hw_reset = false; 1714 unsigned int i; 1715 1716 dpu_enc = to_dpu_encoder_virt(drm_enc); 1717 1718 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc)); 1719 1720 /* prepare for next kickoff, may include waiting on previous kickoff */ 1721 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff"); 1722 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1723 phys = dpu_enc->phys_encs[i]; 1724 if (phys->ops.prepare_for_kickoff) 1725 phys->ops.prepare_for_kickoff(phys); 1726 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) 1727 needs_hw_reset = true; 1728 } 1729 DPU_ATRACE_END("enc_prepare_for_kickoff"); 1730 1731 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF); 1732 1733 /* if any phys needs reset, reset all phys, in-order */ 1734 if (needs_hw_reset) { 1735 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc)); 1736 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1737 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]); 1738 } 1739 } 1740 } 1741 1742 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 1743 { 1744 struct dpu_encoder_virt *dpu_enc; 1745 struct dpu_encoder_phys *phys; 1746 ktime_t wakeup_time; 1747 unsigned long timeout_ms; 1748 unsigned int i; 1749 1750 DPU_ATRACE_BEGIN("encoder_kickoff"); 1751 dpu_enc = to_dpu_encoder_virt(drm_enc); 1752 1753 trace_dpu_enc_kickoff(DRMID(drm_enc)); 1754 1755 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 / 1756 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode); 1757 1758 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms); 1759 mod_timer(&dpu_enc->frame_done_timer, 1760 jiffies + msecs_to_jiffies(timeout_ms)); 1761 1762 /* All phys encs are ready to go, trigger the kickoff */ 1763 _dpu_encoder_kickoff_phys(dpu_enc); 1764 1765 /* allow phys encs to handle any post-kickoff business */ 1766 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1767 phys = dpu_enc->phys_encs[i]; 1768 if (phys->ops.handle_post_kickoff) 1769 phys->ops.handle_post_kickoff(phys); 1770 } 1771 1772 if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI && 1773 !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { 1774 trace_dpu_enc_early_kickoff(DRMID(drm_enc), 1775 ktime_to_ms(wakeup_time)); 1776 mod_timer(&dpu_enc->vsync_event_timer, 1777 nsecs_to_jiffies(ktime_to_ns(wakeup_time))); 1778 } 1779 1780 DPU_ATRACE_END("encoder_kickoff"); 1781 } 1782 1783 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) 1784 { 1785 struct dpu_encoder_virt *dpu_enc; 1786 struct dpu_encoder_phys *phys; 1787 int i; 1788 1789 if (!drm_enc) { 1790 DPU_ERROR("invalid encoder\n"); 1791 return; 1792 } 1793 dpu_enc = to_dpu_encoder_virt(drm_enc); 1794 1795 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1796 phys = dpu_enc->phys_encs[i]; 1797 if (phys->ops.prepare_commit) 1798 phys->ops.prepare_commit(phys); 1799 } 1800 } 1801 1802 #ifdef CONFIG_DEBUG_FS 1803 static int _dpu_encoder_status_show(struct seq_file *s, void *data) 1804 { 1805 struct dpu_encoder_virt *dpu_enc = s->private; 1806 int i; 1807 1808 mutex_lock(&dpu_enc->enc_lock); 1809 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 1810 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 1811 1812 seq_printf(s, "intf:%d vsync:%8d underrun:%8d ", 1813 phys->intf_idx - INTF_0, 1814 atomic_read(&phys->vsync_cnt), 1815 atomic_read(&phys->underrun_cnt)); 1816 1817 switch (phys->intf_mode) { 1818 case INTF_MODE_VIDEO: 1819 seq_puts(s, "mode: video\n"); 1820 break; 1821 case INTF_MODE_CMD: 1822 seq_puts(s, "mode: command\n"); 1823 break; 1824 default: 1825 seq_puts(s, "mode: ???\n"); 1826 break; 1827 } 1828 } 1829 mutex_unlock(&dpu_enc->enc_lock); 1830 1831 return 0; 1832 } 1833 1834 static int _dpu_encoder_debugfs_status_open(struct inode *inode, 1835 struct file *file) 1836 { 1837 return single_open(file, _dpu_encoder_status_show, inode->i_private); 1838 } 1839 1840 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1841 { 1842 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); 1843 int i; 1844 1845 static const struct file_operations debugfs_status_fops = { 1846 .open = _dpu_encoder_debugfs_status_open, 1847 .read = seq_read, 1848 .llseek = seq_lseek, 1849 .release = single_release, 1850 }; 1851 1852 char name[DPU_NAME_SIZE]; 1853 1854 if (!drm_enc->dev) { 1855 DPU_ERROR("invalid encoder or kms\n"); 1856 return -EINVAL; 1857 } 1858 1859 snprintf(name, DPU_NAME_SIZE, "encoder%u", drm_enc->base.id); 1860 1861 /* create overall sub-directory for the encoder */ 1862 dpu_enc->debugfs_root = debugfs_create_dir(name, 1863 drm_enc->dev->primary->debugfs_root); 1864 1865 /* don't error check these */ 1866 debugfs_create_file("status", 0600, 1867 dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops); 1868 1869 for (i = 0; i < dpu_enc->num_phys_encs; i++) 1870 if (dpu_enc->phys_encs[i]->ops.late_register) 1871 dpu_enc->phys_encs[i]->ops.late_register( 1872 dpu_enc->phys_encs[i], 1873 dpu_enc->debugfs_root); 1874 1875 return 0; 1876 } 1877 #else 1878 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc) 1879 { 1880 return 0; 1881 } 1882 #endif 1883 1884 static int dpu_encoder_late_register(struct drm_encoder *encoder) 1885 { 1886 return _dpu_encoder_init_debugfs(encoder); 1887 } 1888 1889 static void dpu_encoder_early_unregister(struct drm_encoder *encoder) 1890 { 1891 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); 1892 1893 debugfs_remove_recursive(dpu_enc->debugfs_root); 1894 } 1895 1896 static int dpu_encoder_virt_add_phys_encs( 1897 u32 display_caps, 1898 struct dpu_encoder_virt *dpu_enc, 1899 struct dpu_enc_phys_init_params *params) 1900 { 1901 struct dpu_encoder_phys *enc = NULL; 1902 1903 DPU_DEBUG_ENC(dpu_enc, "\n"); 1904 1905 /* 1906 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types 1907 * in this function, check up-front. 1908 */ 1909 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >= 1910 ARRAY_SIZE(dpu_enc->phys_encs)) { 1911 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n", 1912 dpu_enc->num_phys_encs); 1913 return -EINVAL; 1914 } 1915 1916 if (display_caps & MSM_DISPLAY_CAP_VID_MODE) { 1917 enc = dpu_encoder_phys_vid_init(params); 1918 1919 if (IS_ERR_OR_NULL(enc)) { 1920 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", 1921 PTR_ERR(enc)); 1922 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1923 } 1924 1925 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1926 ++dpu_enc->num_phys_encs; 1927 } 1928 1929 if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) { 1930 enc = dpu_encoder_phys_cmd_init(params); 1931 1932 if (IS_ERR_OR_NULL(enc)) { 1933 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", 1934 PTR_ERR(enc)); 1935 return enc == NULL ? -EINVAL : PTR_ERR(enc); 1936 } 1937 1938 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; 1939 ++dpu_enc->num_phys_encs; 1940 } 1941 1942 if (params->split_role == ENC_ROLE_SLAVE) 1943 dpu_enc->cur_slave = enc; 1944 else 1945 dpu_enc->cur_master = enc; 1946 1947 return 0; 1948 } 1949 1950 static const struct dpu_encoder_virt_ops dpu_encoder_parent_ops = { 1951 .handle_vblank_virt = dpu_encoder_vblank_callback, 1952 .handle_underrun_virt = dpu_encoder_underrun_callback, 1953 .handle_frame_done = dpu_encoder_frame_done_callback, 1954 }; 1955 1956 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 1957 struct dpu_kms *dpu_kms, 1958 struct msm_display_info *disp_info) 1959 { 1960 int ret = 0; 1961 int i = 0; 1962 enum dpu_intf_type intf_type; 1963 struct dpu_enc_phys_init_params phys_params; 1964 1965 if (!dpu_enc) { 1966 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL); 1967 return -EINVAL; 1968 } 1969 1970 dpu_enc->cur_master = NULL; 1971 1972 memset(&phys_params, 0, sizeof(phys_params)); 1973 phys_params.dpu_kms = dpu_kms; 1974 phys_params.parent = &dpu_enc->base; 1975 phys_params.parent_ops = &dpu_encoder_parent_ops; 1976 phys_params.enc_spinlock = &dpu_enc->enc_spinlock; 1977 1978 DPU_DEBUG("\n"); 1979 1980 switch (disp_info->intf_type) { 1981 case DRM_MODE_ENCODER_DSI: 1982 intf_type = INTF_DSI; 1983 break; 1984 default: 1985 DPU_ERROR_ENC(dpu_enc, "unsupported display interface type\n"); 1986 return -EINVAL; 1987 } 1988 1989 WARN_ON(disp_info->num_of_h_tiles < 1); 1990 1991 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); 1992 1993 if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || 1994 (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) 1995 dpu_enc->idle_pc_supported = 1996 dpu_kms->catalog->caps->has_idle_pc; 1997 1998 mutex_lock(&dpu_enc->enc_lock); 1999 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { 2000 /* 2001 * Left-most tile is at index 0, content is controller id 2002 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right 2003 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right 2004 */ 2005 u32 controller_id = disp_info->h_tile_instance[i]; 2006 2007 if (disp_info->num_of_h_tiles > 1) { 2008 if (i == 0) 2009 phys_params.split_role = ENC_ROLE_MASTER; 2010 else 2011 phys_params.split_role = ENC_ROLE_SLAVE; 2012 } else { 2013 phys_params.split_role = ENC_ROLE_SOLO; 2014 } 2015 2016 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n", 2017 i, controller_id, phys_params.split_role); 2018 2019 phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog, 2020 intf_type, 2021 controller_id); 2022 if (phys_params.intf_idx == INTF_MAX) { 2023 DPU_ERROR_ENC(dpu_enc, "could not get intf: type %d, id %d\n", 2024 intf_type, controller_id); 2025 ret = -EINVAL; 2026 } 2027 2028 if (!ret) { 2029 ret = dpu_encoder_virt_add_phys_encs(disp_info->capabilities, 2030 dpu_enc, 2031 &phys_params); 2032 if (ret) 2033 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n"); 2034 } 2035 } 2036 2037 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2038 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2039 atomic_set(&phys->vsync_cnt, 0); 2040 atomic_set(&phys->underrun_cnt, 0); 2041 } 2042 mutex_unlock(&dpu_enc->enc_lock); 2043 2044 return ret; 2045 } 2046 2047 static void dpu_encoder_frame_done_timeout(struct timer_list *t) 2048 { 2049 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, 2050 frame_done_timer); 2051 struct drm_encoder *drm_enc = &dpu_enc->base; 2052 u32 event; 2053 2054 if (!drm_enc->dev) { 2055 DPU_ERROR("invalid parameters\n"); 2056 return; 2057 } 2058 2059 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc_frame_event_cb) { 2060 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n", 2061 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]); 2062 return; 2063 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) { 2064 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc)); 2065 return; 2066 } 2067 2068 DPU_ERROR_ENC(dpu_enc, "frame done timeout\n"); 2069 2070 event = DPU_ENCODER_FRAME_EVENT_ERROR; 2071 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event); 2072 dpu_enc->crtc_frame_event_cb(dpu_enc->crtc_frame_event_cb_data, event); 2073 } 2074 2075 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = { 2076 .mode_set = dpu_encoder_virt_mode_set, 2077 .disable = dpu_encoder_virt_disable, 2078 .enable = dpu_kms_encoder_enable, 2079 .atomic_check = dpu_encoder_virt_atomic_check, 2080 2081 /* This is called by dpu_kms_encoder_enable */ 2082 .commit = dpu_encoder_virt_enable, 2083 }; 2084 2085 static const struct drm_encoder_funcs dpu_encoder_funcs = { 2086 .destroy = dpu_encoder_destroy, 2087 .late_register = dpu_encoder_late_register, 2088 .early_unregister = dpu_encoder_early_unregister, 2089 }; 2090 2091 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 2092 struct msm_display_info *disp_info) 2093 { 2094 struct msm_drm_private *priv = dev->dev_private; 2095 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); 2096 struct drm_encoder *drm_enc = NULL; 2097 struct dpu_encoder_virt *dpu_enc = NULL; 2098 int ret = 0; 2099 2100 dpu_enc = to_dpu_encoder_virt(enc); 2101 2102 mutex_init(&dpu_enc->enc_lock); 2103 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info); 2104 if (ret) 2105 goto fail; 2106 2107 atomic_set(&dpu_enc->frame_done_timeout_ms, 0); 2108 timer_setup(&dpu_enc->frame_done_timer, 2109 dpu_encoder_frame_done_timeout, 0); 2110 2111 if (disp_info->intf_type == DRM_MODE_ENCODER_DSI) 2112 timer_setup(&dpu_enc->vsync_event_timer, 2113 dpu_encoder_vsync_event_handler, 2114 0); 2115 2116 2117 mutex_init(&dpu_enc->rc_lock); 2118 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, 2119 dpu_encoder_off_work); 2120 dpu_enc->idle_timeout = IDLE_TIMEOUT; 2121 2122 kthread_init_work(&dpu_enc->vsync_event_work, 2123 dpu_encoder_vsync_event_work_handler); 2124 2125 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); 2126 2127 DPU_DEBUG_ENC(dpu_enc, "created\n"); 2128 2129 return ret; 2130 2131 fail: 2132 DPU_ERROR("failed to create encoder\n"); 2133 if (drm_enc) 2134 dpu_encoder_destroy(drm_enc); 2135 2136 return ret; 2137 2138 2139 } 2140 2141 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2142 int drm_enc_mode) 2143 { 2144 struct dpu_encoder_virt *dpu_enc = NULL; 2145 int rc = 0; 2146 2147 dpu_enc = devm_kzalloc(dev->dev, sizeof(*dpu_enc), GFP_KERNEL); 2148 if (!dpu_enc) 2149 return ERR_PTR(ENOMEM); 2150 2151 rc = drm_encoder_init(dev, &dpu_enc->base, &dpu_encoder_funcs, 2152 drm_enc_mode, NULL); 2153 if (rc) { 2154 devm_kfree(dev->dev, dpu_enc); 2155 return ERR_PTR(rc); 2156 } 2157 2158 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); 2159 2160 spin_lock_init(&dpu_enc->enc_spinlock); 2161 dpu_enc->enabled = false; 2162 2163 return &dpu_enc->base; 2164 } 2165 2166 int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, 2167 enum msm_event_wait event) 2168 { 2169 int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; 2170 struct dpu_encoder_virt *dpu_enc = NULL; 2171 int i, ret = 0; 2172 2173 if (!drm_enc) { 2174 DPU_ERROR("invalid encoder\n"); 2175 return -EINVAL; 2176 } 2177 dpu_enc = to_dpu_encoder_virt(drm_enc); 2178 DPU_DEBUG_ENC(dpu_enc, "\n"); 2179 2180 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 2181 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 2182 2183 switch (event) { 2184 case MSM_ENC_COMMIT_DONE: 2185 fn_wait = phys->ops.wait_for_commit_done; 2186 break; 2187 case MSM_ENC_TX_COMPLETE: 2188 fn_wait = phys->ops.wait_for_tx_complete; 2189 break; 2190 case MSM_ENC_VBLANK: 2191 fn_wait = phys->ops.wait_for_vblank; 2192 break; 2193 default: 2194 DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", 2195 event); 2196 return -EINVAL; 2197 } 2198 2199 if (fn_wait) { 2200 DPU_ATRACE_BEGIN("wait_for_completion_event"); 2201 ret = fn_wait(phys); 2202 DPU_ATRACE_END("wait_for_completion_event"); 2203 if (ret) 2204 return ret; 2205 } 2206 } 2207 2208 return ret; 2209 } 2210 2211 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2212 { 2213 struct dpu_encoder_virt *dpu_enc = NULL; 2214 2215 if (!encoder) { 2216 DPU_ERROR("invalid encoder\n"); 2217 return INTF_MODE_NONE; 2218 } 2219 dpu_enc = to_dpu_encoder_virt(encoder); 2220 2221 if (dpu_enc->cur_master) 2222 return dpu_enc->cur_master->intf_mode; 2223 2224 if (dpu_enc->num_phys_encs) 2225 return dpu_enc->phys_encs[0]->intf_mode; 2226 2227 return INTF_MODE_NONE; 2228 } 2229