1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
21 #define REG_SKIP ~0
22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
23 
24 extern bool snapshot_debugbus;
25 
26 /**
27  * adreno_regs: List of registers that are used in across all
28  * 3D devices. Each device type has different offset value for the same
29  * register, so an array of register offsets are declared for every device
30  * and are indexed by the enumeration values defined in this enum
31  */
32 enum adreno_regs {
33 	REG_ADRENO_CP_RB_BASE,
34 	REG_ADRENO_CP_RB_BASE_HI,
35 	REG_ADRENO_CP_RB_RPTR_ADDR,
36 	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
37 	REG_ADRENO_CP_RB_RPTR,
38 	REG_ADRENO_CP_RB_WPTR,
39 	REG_ADRENO_CP_RB_CNTL,
40 	REG_ADRENO_REGISTER_MAX,
41 };
42 
43 enum {
44 	ADRENO_FW_PM4 = 0,
45 	ADRENO_FW_SQE = 0, /* a6xx */
46 	ADRENO_FW_PFP = 1,
47 	ADRENO_FW_GMU = 1, /* a6xx */
48 	ADRENO_FW_GPMU = 2,
49 	ADRENO_FW_MAX,
50 };
51 
52 enum adreno_quirks {
53 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
54 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
55 	ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
56 };
57 
58 struct adreno_rev {
59 	uint8_t  core;
60 	uint8_t  major;
61 	uint8_t  minor;
62 	uint8_t  patchid;
63 };
64 
65 #define ADRENO_REV(core, major, minor, patchid) \
66 	((struct adreno_rev){ core, major, minor, patchid })
67 
68 struct adreno_gpu_funcs {
69 	struct msm_gpu_funcs base;
70 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
71 };
72 
73 struct adreno_reglist {
74 	u32 offset;
75 	u32 value;
76 };
77 
78 extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
79 
80 struct adreno_info {
81 	struct adreno_rev rev;
82 	uint32_t revn;
83 	const char *name;
84 	const char *fw[ADRENO_FW_MAX];
85 	uint32_t gmem;
86 	enum adreno_quirks quirks;
87 	struct msm_gpu *(*init)(struct drm_device *dev);
88 	const char *zapfw;
89 	u32 inactive_period;
90 	const struct adreno_reglist *hwcg;
91 };
92 
93 const struct adreno_info *adreno_info(struct adreno_rev rev);
94 
95 struct adreno_gpu {
96 	struct msm_gpu base;
97 	struct adreno_rev rev;
98 	const struct adreno_info *info;
99 	uint32_t gmem;  /* actual gmem size */
100 	uint32_t revn;  /* numeric revision name */
101 	const struct adreno_gpu_funcs *funcs;
102 
103 	/* interesting register offsets to dump: */
104 	const unsigned int *registers;
105 
106 	/*
107 	 * Are we loading fw from legacy path?  Prior to addition
108 	 * of gpu firmware to linux-firmware, the fw files were
109 	 * placed in toplevel firmware directory, following qcom's
110 	 * android kernel.  But linux-firmware preferred they be
111 	 * placed in a 'qcom' subdirectory.
112 	 *
113 	 * For backwards compatibility, we try first to load from
114 	 * the new path, using request_firmware_direct() to avoid
115 	 * any potential timeout waiting for usermode helper, then
116 	 * fall back to the old path (with direct load).  And
117 	 * finally fall back to request_firmware() with the new
118 	 * path to allow the usermode helper.
119 	 */
120 	enum {
121 		FW_LOCATION_UNKNOWN = 0,
122 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
123 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
124 		FW_LOCATION_HELPER,
125 	} fwloc;
126 
127 	/* firmware: */
128 	const struct firmware *fw[ADRENO_FW_MAX];
129 
130 	/*
131 	 * Register offsets are different between some GPUs.
132 	 * GPU specific offsets will be exported by GPU specific
133 	 * code (a3xx_gpu.c) and stored in this common location.
134 	 */
135 	const unsigned int *reg_offsets;
136 };
137 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
138 
139 struct adreno_ocmem {
140 	struct ocmem *ocmem;
141 	unsigned long base;
142 	void *hdl;
143 };
144 
145 /* platform config data (ie. from DT, or pdata) */
146 struct adreno_platform_config {
147 	struct adreno_rev rev;
148 };
149 
150 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
151 
152 #define spin_until(X) ({                                   \
153 	int __ret = -ETIMEDOUT;                            \
154 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
155 	do {                                               \
156 		if (X) {                                   \
157 			__ret = 0;                         \
158 			break;                             \
159 		}                                          \
160 	} while (time_before(jiffies, __t));               \
161 	__ret;                                             \
162 })
163 
164 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
165 {
166 	return (gpu->revn < 300);
167 }
168 
169 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
170 {
171 	return (gpu->revn < 210);
172 }
173 
174 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
175 {
176 	return gpu->revn == 225;
177 }
178 
179 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
180 {
181 	return (gpu->revn >= 300) && (gpu->revn < 400);
182 }
183 
184 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
185 {
186 	return gpu->revn == 305;
187 }
188 
189 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
190 {
191 	/* yes, 307, because a305c is 306 */
192 	return gpu->revn == 307;
193 }
194 
195 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
196 {
197 	return gpu->revn == 320;
198 }
199 
200 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
201 {
202 	return gpu->revn == 330;
203 }
204 
205 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
206 {
207 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
208 }
209 
210 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
211 {
212 	return (gpu->revn >= 400) && (gpu->revn < 500);
213 }
214 
215 static inline int adreno_is_a405(struct adreno_gpu *gpu)
216 {
217 	return gpu->revn == 405;
218 }
219 
220 static inline int adreno_is_a420(struct adreno_gpu *gpu)
221 {
222 	return gpu->revn == 420;
223 }
224 
225 static inline int adreno_is_a430(struct adreno_gpu *gpu)
226 {
227        return gpu->revn == 430;
228 }
229 
230 static inline int adreno_is_a510(struct adreno_gpu *gpu)
231 {
232 	return gpu->revn == 510;
233 }
234 
235 static inline int adreno_is_a530(struct adreno_gpu *gpu)
236 {
237 	return gpu->revn == 530;
238 }
239 
240 static inline int adreno_is_a540(struct adreno_gpu *gpu)
241 {
242 	return gpu->revn == 540;
243 }
244 
245 static inline int adreno_is_a618(struct adreno_gpu *gpu)
246 {
247        return gpu->revn == 618;
248 }
249 
250 static inline int adreno_is_a630(struct adreno_gpu *gpu)
251 {
252        return gpu->revn == 630;
253 }
254 
255 static inline int adreno_is_a640(struct adreno_gpu *gpu)
256 {
257        return gpu->revn == 640;
258 }
259 
260 static inline int adreno_is_a650(struct adreno_gpu *gpu)
261 {
262        return gpu->revn == 650;
263 }
264 
265 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
266 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
267 		const char *fwname);
268 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
269 		const struct firmware *fw, u64 *iova);
270 int adreno_hw_init(struct msm_gpu *gpu);
271 void adreno_recover(struct msm_gpu *gpu);
272 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
273 		struct msm_file_private *ctx);
274 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
275 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
276 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
277 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
278 		struct drm_printer *p);
279 #endif
280 void adreno_dump_info(struct msm_gpu *gpu);
281 void adreno_dump(struct msm_gpu *gpu);
282 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
283 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
284 
285 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
286 			  struct adreno_ocmem *ocmem);
287 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
288 
289 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
290 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
291 		int nr_rings);
292 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
293 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
294 
295 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
296 
297 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
298 int adreno_gpu_state_put(struct msm_gpu_state *state);
299 
300 /*
301  * Common helper function to initialize the default address space for arm-smmu
302  * attached targets
303  */
304 struct msm_gem_address_space *
305 adreno_iommu_create_address_space(struct msm_gpu *gpu,
306 		struct platform_device *pdev);
307 
308 /*
309  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
310  * out of secure mode
311  */
312 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
313 
314 /* ringbuffer helpers (the parts that are adreno specific) */
315 
316 static inline void
317 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
318 {
319 	adreno_wait_ring(ring, cnt+1);
320 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
321 }
322 
323 /* no-op packet: */
324 static inline void
325 OUT_PKT2(struct msm_ringbuffer *ring)
326 {
327 	adreno_wait_ring(ring, 1);
328 	OUT_RING(ring, CP_TYPE2_PKT);
329 }
330 
331 static inline void
332 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
333 {
334 	adreno_wait_ring(ring, cnt+1);
335 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
336 }
337 
338 static inline u32 PM4_PARITY(u32 val)
339 {
340 	return (0x9669 >> (0xF & (val ^
341 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
342 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
343 		(val >> 28)))) & 1;
344 }
345 
346 /* Maximum number of values that can be executed for one opcode */
347 #define TYPE4_MAX_PAYLOAD 127
348 
349 #define PKT4(_reg, _cnt) \
350 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
351 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
352 
353 static inline void
354 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
355 {
356 	adreno_wait_ring(ring, cnt + 1);
357 	OUT_RING(ring, PKT4(regindx, cnt));
358 }
359 
360 static inline void
361 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
362 {
363 	adreno_wait_ring(ring, cnt + 1);
364 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
365 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
366 }
367 
368 /*
369  * adreno_reg_check() - Checks the validity of a register enum
370  * @gpu:		Pointer to struct adreno_gpu
371  * @offset_name:	The register enum that is checked
372  */
373 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
374 		enum adreno_regs offset_name)
375 {
376 	BUG_ON(offset_name >= REG_ADRENO_REGISTER_MAX || !gpu->reg_offsets[offset_name]);
377 
378 	/*
379 	 * REG_SKIP is a special value that tell us that the register in
380 	 * question isn't implemented on target but don't trigger a BUG(). This
381 	 * is used to cleanly implement adreno_gpu_write64() and
382 	 * adreno_gpu_read64() in a generic fashion
383 	 */
384 	if (gpu->reg_offsets[offset_name] == REG_SKIP)
385 		return false;
386 
387 	return true;
388 }
389 
390 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
391 		enum adreno_regs offset_name)
392 {
393 	u32 reg = gpu->reg_offsets[offset_name];
394 	u32 val = 0;
395 	if(adreno_reg_check(gpu,offset_name))
396 		val = gpu_read(&gpu->base, reg - 1);
397 	return val;
398 }
399 
400 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
401 		enum adreno_regs offset_name, u32 data)
402 {
403 	u32 reg = gpu->reg_offsets[offset_name];
404 	if(adreno_reg_check(gpu, offset_name))
405 		gpu_write(&gpu->base, reg - 1, data);
406 }
407 
408 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
409 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
410 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
411 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
412 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
413 
414 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
415 		enum adreno_regs lo, enum adreno_regs hi, u64 data)
416 {
417 	adreno_gpu_write(gpu, lo, lower_32_bits(data));
418 	adreno_gpu_write(gpu, hi, upper_32_bits(data));
419 }
420 
421 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
422 {
423 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
424 }
425 
426 /*
427  * Given a register and a count, return a value to program into
428  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
429  * registers starting at _reg.
430  *
431  * The register base needs to be a multiple of the length. If it is not, the
432  * hardware will quietly mask off the bits for you and shift the size. For
433  * example, if you intend the protection to start at 0x07 for a length of 4
434  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
435  * expose registers you intended to protect!
436  */
437 #define ADRENO_PROTECT_RW(_reg, _len) \
438 	((1 << 30) | (1 << 29) | \
439 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
440 
441 /*
442  * Same as above, but allow reads over the range. For areas of mixed use (such
443  * as performance counters) this allows us to protect a much larger range with a
444  * single register
445  */
446 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
447 	((1 << 29) \
448 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
449 
450 
451 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
452 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
453 		interval, timeout)
454 
455 #endif /* __ADRENO_GPU_H__ */
456