1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef __ADRENO_GPU_H__
21 #define __ADRENO_GPU_H__
22 
23 #include <linux/firmware.h>
24 #include <linux/iopoll.h>
25 
26 #include "msm_gpu.h"
27 
28 #include "adreno_common.xml.h"
29 #include "adreno_pm4.xml.h"
30 
31 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
32 #define REG_SKIP ~0
33 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
34 
35 /**
36  * adreno_regs: List of registers that are used in across all
37  * 3D devices. Each device type has different offset value for the same
38  * register, so an array of register offsets are declared for every device
39  * and are indexed by the enumeration values defined in this enum
40  */
41 enum adreno_regs {
42 	REG_ADRENO_CP_RB_BASE,
43 	REG_ADRENO_CP_RB_BASE_HI,
44 	REG_ADRENO_CP_RB_RPTR_ADDR,
45 	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
46 	REG_ADRENO_CP_RB_RPTR,
47 	REG_ADRENO_CP_RB_WPTR,
48 	REG_ADRENO_CP_RB_CNTL,
49 	REG_ADRENO_REGISTER_MAX,
50 };
51 
52 enum {
53 	ADRENO_FW_PM4 = 0,
54 	ADRENO_FW_SQE = 0, /* a6xx */
55 	ADRENO_FW_PFP = 1,
56 	ADRENO_FW_GMU = 1, /* a6xx */
57 	ADRENO_FW_GPMU = 2,
58 	ADRENO_FW_MAX,
59 };
60 
61 enum adreno_quirks {
62 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
63 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
64 };
65 
66 struct adreno_rev {
67 	uint8_t  core;
68 	uint8_t  major;
69 	uint8_t  minor;
70 	uint8_t  patchid;
71 };
72 
73 #define ADRENO_REV(core, major, minor, patchid) \
74 	((struct adreno_rev){ core, major, minor, patchid })
75 
76 struct adreno_gpu_funcs {
77 	struct msm_gpu_funcs base;
78 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
79 };
80 
81 struct adreno_info {
82 	struct adreno_rev rev;
83 	uint32_t revn;
84 	const char *name;
85 	const char *fw[ADRENO_FW_MAX];
86 	uint32_t gmem;
87 	enum adreno_quirks quirks;
88 	struct msm_gpu *(*init)(struct drm_device *dev);
89 	const char *zapfw;
90 	u32 inactive_period;
91 };
92 
93 const struct adreno_info *adreno_info(struct adreno_rev rev);
94 
95 struct adreno_gpu {
96 	struct msm_gpu base;
97 	struct adreno_rev rev;
98 	const struct adreno_info *info;
99 	uint32_t gmem;  /* actual gmem size */
100 	uint32_t revn;  /* numeric revision name */
101 	const struct adreno_gpu_funcs *funcs;
102 
103 	/* interesting register offsets to dump: */
104 	const unsigned int *registers;
105 
106 	/*
107 	 * Are we loading fw from legacy path?  Prior to addition
108 	 * of gpu firmware to linux-firmware, the fw files were
109 	 * placed in toplevel firmware directory, following qcom's
110 	 * android kernel.  But linux-firmware preferred they be
111 	 * placed in a 'qcom' subdirectory.
112 	 *
113 	 * For backwards compatibility, we try first to load from
114 	 * the new path, using request_firmware_direct() to avoid
115 	 * any potential timeout waiting for usermode helper, then
116 	 * fall back to the old path (with direct load).  And
117 	 * finally fall back to request_firmware() with the new
118 	 * path to allow the usermode helper.
119 	 */
120 	enum {
121 		FW_LOCATION_UNKNOWN = 0,
122 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
123 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
124 		FW_LOCATION_HELPER,
125 	} fwloc;
126 
127 	/* firmware: */
128 	const struct firmware *fw[ADRENO_FW_MAX];
129 
130 	/*
131 	 * Register offsets are different between some GPUs.
132 	 * GPU specific offsets will be exported by GPU specific
133 	 * code (a3xx_gpu.c) and stored in this common location.
134 	 */
135 	const unsigned int *reg_offsets;
136 };
137 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
138 
139 /* platform config data (ie. from DT, or pdata) */
140 struct adreno_platform_config {
141 	struct adreno_rev rev;
142 };
143 
144 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
145 
146 #define spin_until(X) ({                                   \
147 	int __ret = -ETIMEDOUT;                            \
148 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
149 	do {                                               \
150 		if (X) {                                   \
151 			__ret = 0;                         \
152 			break;                             \
153 		}                                          \
154 	} while (time_before(jiffies, __t));               \
155 	__ret;                                             \
156 })
157 
158 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
159 {
160 	return (gpu->revn < 300);
161 }
162 
163 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
164 {
165 	return (gpu->revn < 210);
166 }
167 
168 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
169 {
170 	return gpu->revn == 225;
171 }
172 
173 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
174 {
175 	return (gpu->revn >= 300) && (gpu->revn < 400);
176 }
177 
178 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
179 {
180 	return gpu->revn == 305;
181 }
182 
183 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
184 {
185 	/* yes, 307, because a305c is 306 */
186 	return gpu->revn == 307;
187 }
188 
189 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
190 {
191 	return gpu->revn == 320;
192 }
193 
194 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
195 {
196 	return gpu->revn == 330;
197 }
198 
199 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
200 {
201 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
202 }
203 
204 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
205 {
206 	return (gpu->revn >= 400) && (gpu->revn < 500);
207 }
208 
209 static inline int adreno_is_a420(struct adreno_gpu *gpu)
210 {
211 	return gpu->revn == 420;
212 }
213 
214 static inline int adreno_is_a430(struct adreno_gpu *gpu)
215 {
216        return gpu->revn == 430;
217 }
218 
219 static inline int adreno_is_a530(struct adreno_gpu *gpu)
220 {
221 	return gpu->revn == 530;
222 }
223 
224 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
225 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
226 		const char *fwname);
227 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
228 		const struct firmware *fw, u64 *iova);
229 int adreno_hw_init(struct msm_gpu *gpu);
230 void adreno_recover(struct msm_gpu *gpu);
231 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
232 		struct msm_file_private *ctx);
233 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
234 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
235 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
236 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
237 		struct drm_printer *p);
238 #endif
239 void adreno_dump_info(struct msm_gpu *gpu);
240 void adreno_dump(struct msm_gpu *gpu);
241 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
242 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
243 
244 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
245 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
246 		int nr_rings);
247 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
248 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
249 
250 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
251 
252 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
253 int adreno_gpu_state_put(struct msm_gpu_state *state);
254 
255 /* ringbuffer helpers (the parts that are adreno specific) */
256 
257 static inline void
258 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
259 {
260 	adreno_wait_ring(ring, cnt+1);
261 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
262 }
263 
264 /* no-op packet: */
265 static inline void
266 OUT_PKT2(struct msm_ringbuffer *ring)
267 {
268 	adreno_wait_ring(ring, 1);
269 	OUT_RING(ring, CP_TYPE2_PKT);
270 }
271 
272 static inline void
273 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
274 {
275 	adreno_wait_ring(ring, cnt+1);
276 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
277 }
278 
279 static inline u32 PM4_PARITY(u32 val)
280 {
281 	return (0x9669 >> (0xF & (val ^
282 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
283 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
284 		(val >> 28)))) & 1;
285 }
286 
287 /* Maximum number of values that can be executed for one opcode */
288 #define TYPE4_MAX_PAYLOAD 127
289 
290 #define PKT4(_reg, _cnt) \
291 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
292 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
293 
294 static inline void
295 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
296 {
297 	adreno_wait_ring(ring, cnt + 1);
298 	OUT_RING(ring, PKT4(regindx, cnt));
299 }
300 
301 static inline void
302 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
303 {
304 	adreno_wait_ring(ring, cnt + 1);
305 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
306 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
307 }
308 
309 /*
310  * adreno_reg_check() - Checks the validity of a register enum
311  * @gpu:		Pointer to struct adreno_gpu
312  * @offset_name:	The register enum that is checked
313  */
314 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
315 		enum adreno_regs offset_name)
316 {
317 	if (offset_name >= REG_ADRENO_REGISTER_MAX ||
318 			!gpu->reg_offsets[offset_name]) {
319 		BUG();
320 	}
321 
322 	/*
323 	 * REG_SKIP is a special value that tell us that the register in
324 	 * question isn't implemented on target but don't trigger a BUG(). This
325 	 * is used to cleanly implement adreno_gpu_write64() and
326 	 * adreno_gpu_read64() in a generic fashion
327 	 */
328 	if (gpu->reg_offsets[offset_name] == REG_SKIP)
329 		return false;
330 
331 	return true;
332 }
333 
334 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
335 		enum adreno_regs offset_name)
336 {
337 	u32 reg = gpu->reg_offsets[offset_name];
338 	u32 val = 0;
339 	if(adreno_reg_check(gpu,offset_name))
340 		val = gpu_read(&gpu->base, reg - 1);
341 	return val;
342 }
343 
344 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
345 		enum adreno_regs offset_name, u32 data)
346 {
347 	u32 reg = gpu->reg_offsets[offset_name];
348 	if(adreno_reg_check(gpu, offset_name))
349 		gpu_write(&gpu->base, reg - 1, data);
350 }
351 
352 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
353 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
354 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
355 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
356 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
357 
358 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
359 		enum adreno_regs lo, enum adreno_regs hi, u64 data)
360 {
361 	adreno_gpu_write(gpu, lo, lower_32_bits(data));
362 	adreno_gpu_write(gpu, hi, upper_32_bits(data));
363 }
364 
365 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
366 {
367 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
368 }
369 
370 /*
371  * Given a register and a count, return a value to program into
372  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
373  * registers starting at _reg.
374  *
375  * The register base needs to be a multiple of the length. If it is not, the
376  * hardware will quietly mask off the bits for you and shift the size. For
377  * example, if you intend the protection to start at 0x07 for a length of 4
378  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
379  * expose registers you intended to protect!
380  */
381 #define ADRENO_PROTECT_RW(_reg, _len) \
382 	((1 << 30) | (1 << 29) | \
383 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
384 
385 /*
386  * Same as above, but allow reads over the range. For areas of mixed use (such
387  * as performance counters) this allows us to protect a much larger range with a
388  * single register
389  */
390 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
391 	((1 << 29) \
392 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
393 
394 
395 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
396 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
397 		interval, timeout)
398 
399 #endif /* __ADRENO_GPU_H__ */
400