1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ADRENO_GPU_H__ 21 #define __ADRENO_GPU_H__ 22 23 #include <linux/firmware.h> 24 25 #include "msm_gpu.h" 26 27 #include "adreno_common.xml.h" 28 #include "adreno_pm4.xml.h" 29 30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 31 /** 32 * adreno_regs: List of registers that are used in across all 33 * 3D devices. Each device type has different offset value for the same 34 * register, so an array of register offsets are declared for every device 35 * and are indexed by the enumeration values defined in this enum 36 */ 37 enum adreno_regs { 38 REG_ADRENO_CP_RB_BASE, 39 REG_ADRENO_CP_RB_RPTR_ADDR, 40 REG_ADRENO_CP_RB_RPTR, 41 REG_ADRENO_CP_RB_WPTR, 42 REG_ADRENO_CP_RB_CNTL, 43 REG_ADRENO_REGISTER_MAX, 44 }; 45 46 struct adreno_rev { 47 uint8_t core; 48 uint8_t major; 49 uint8_t minor; 50 uint8_t patchid; 51 }; 52 53 #define ADRENO_REV(core, major, minor, patchid) \ 54 ((struct adreno_rev){ core, major, minor, patchid }) 55 56 struct adreno_gpu_funcs { 57 struct msm_gpu_funcs base; 58 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 59 }; 60 61 struct adreno_info { 62 struct adreno_rev rev; 63 uint32_t revn; 64 const char *name; 65 const char *pm4fw, *pfpfw; 66 uint32_t gmem; 67 struct msm_gpu *(*init)(struct drm_device *dev); 68 }; 69 70 const struct adreno_info *adreno_info(struct adreno_rev rev); 71 72 struct adreno_rbmemptrs { 73 volatile uint32_t rptr; 74 volatile uint32_t wptr; 75 volatile uint32_t fence; 76 }; 77 78 struct adreno_gpu { 79 struct msm_gpu base; 80 struct adreno_rev rev; 81 const struct adreno_info *info; 82 uint32_t gmem; /* actual gmem size */ 83 uint32_t revn; /* numeric revision name */ 84 const struct adreno_gpu_funcs *funcs; 85 86 /* interesting register offsets to dump: */ 87 const unsigned int *registers; 88 89 /* firmware: */ 90 const struct firmware *pm4, *pfp; 91 92 /* ringbuffer rptr/wptr: */ 93 // TODO should this be in msm_ringbuffer? I think it would be 94 // different for z180.. 95 struct adreno_rbmemptrs *memptrs; 96 struct drm_gem_object *memptrs_bo; 97 uint64_t memptrs_iova; 98 99 /* 100 * Register offsets are different between some GPUs. 101 * GPU specific offsets will be exported by GPU specific 102 * code (a3xx_gpu.c) and stored in this common location. 103 */ 104 const unsigned int *reg_offsets; 105 }; 106 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 107 108 /* platform config data (ie. from DT, or pdata) */ 109 struct adreno_platform_config { 110 struct adreno_rev rev; 111 uint32_t fast_rate, slow_rate, bus_freq; 112 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 113 struct msm_bus_scale_pdata *bus_scale_table; 114 #endif 115 }; 116 117 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 118 119 #define spin_until(X) ({ \ 120 int __ret = -ETIMEDOUT; \ 121 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 122 do { \ 123 if (X) { \ 124 __ret = 0; \ 125 break; \ 126 } \ 127 } while (time_before(jiffies, __t)); \ 128 __ret; \ 129 }) 130 131 132 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) 133 { 134 return (gpu->revn >= 300) && (gpu->revn < 400); 135 } 136 137 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 138 { 139 return gpu->revn == 305; 140 } 141 142 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 143 { 144 /* yes, 307, because a305c is 306 */ 145 return gpu->revn == 307; 146 } 147 148 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 149 { 150 return gpu->revn == 320; 151 } 152 153 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 154 { 155 return gpu->revn == 330; 156 } 157 158 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 159 { 160 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 161 } 162 163 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 164 { 165 return (gpu->revn >= 400) && (gpu->revn < 500); 166 } 167 168 static inline int adreno_is_a420(struct adreno_gpu *gpu) 169 { 170 return gpu->revn == 420; 171 } 172 173 static inline int adreno_is_a430(struct adreno_gpu *gpu) 174 { 175 return gpu->revn == 430; 176 } 177 178 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 179 int adreno_hw_init(struct msm_gpu *gpu); 180 uint32_t adreno_last_fence(struct msm_gpu *gpu); 181 void adreno_recover(struct msm_gpu *gpu); 182 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 183 struct msm_file_private *ctx); 184 void adreno_flush(struct msm_gpu *gpu); 185 void adreno_idle(struct msm_gpu *gpu); 186 #ifdef CONFIG_DEBUG_FS 187 void adreno_show(struct msm_gpu *gpu, struct seq_file *m); 188 #endif 189 void adreno_dump_info(struct msm_gpu *gpu); 190 void adreno_dump(struct msm_gpu *gpu); 191 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); 192 193 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 194 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs); 195 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 196 197 198 /* ringbuffer helpers (the parts that are adreno specific) */ 199 200 static inline void 201 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 202 { 203 adreno_wait_ring(ring->gpu, cnt+1); 204 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 205 } 206 207 /* no-op packet: */ 208 static inline void 209 OUT_PKT2(struct msm_ringbuffer *ring) 210 { 211 adreno_wait_ring(ring->gpu, 1); 212 OUT_RING(ring, CP_TYPE2_PKT); 213 } 214 215 static inline void 216 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 217 { 218 adreno_wait_ring(ring->gpu, cnt+1); 219 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 220 } 221 222 /* 223 * adreno_checkreg_off() - Checks the validity of a register enum 224 * @gpu: Pointer to struct adreno_gpu 225 * @offset_name: The register enum that is checked 226 */ 227 static inline bool adreno_reg_check(struct adreno_gpu *gpu, 228 enum adreno_regs offset_name) 229 { 230 if (offset_name >= REG_ADRENO_REGISTER_MAX || 231 !gpu->reg_offsets[offset_name]) { 232 BUG(); 233 } 234 return true; 235 } 236 237 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu, 238 enum adreno_regs offset_name) 239 { 240 u32 reg = gpu->reg_offsets[offset_name]; 241 u32 val = 0; 242 if(adreno_reg_check(gpu,offset_name)) 243 val = gpu_read(&gpu->base, reg - 1); 244 return val; 245 } 246 247 static inline void adreno_gpu_write(struct adreno_gpu *gpu, 248 enum adreno_regs offset_name, u32 data) 249 { 250 u32 reg = gpu->reg_offsets[offset_name]; 251 if(adreno_reg_check(gpu, offset_name)) 252 gpu_write(&gpu->base, reg - 1, data); 253 } 254 255 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 256 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 257 258 #endif /* __ADRENO_GPU_H__ */ 259