1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ADRENO_GPU_H__ 21 #define __ADRENO_GPU_H__ 22 23 #include <linux/firmware.h> 24 25 #include "msm_gpu.h" 26 27 #include "adreno_common.xml.h" 28 #include "adreno_pm4.xml.h" 29 30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 31 #define REG_SKIP ~0 32 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP 33 34 /** 35 * adreno_regs: List of registers that are used in across all 36 * 3D devices. Each device type has different offset value for the same 37 * register, so an array of register offsets are declared for every device 38 * and are indexed by the enumeration values defined in this enum 39 */ 40 enum adreno_regs { 41 REG_ADRENO_CP_RB_BASE, 42 REG_ADRENO_CP_RB_BASE_HI, 43 REG_ADRENO_CP_RB_RPTR_ADDR, 44 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 45 REG_ADRENO_CP_RB_RPTR, 46 REG_ADRENO_CP_RB_WPTR, 47 REG_ADRENO_CP_RB_CNTL, 48 REG_ADRENO_REGISTER_MAX, 49 }; 50 51 enum { 52 ADRENO_FW_PM4 = 0, 53 ADRENO_FW_PFP = 1, 54 ADRENO_FW_GPMU = 2, 55 ADRENO_FW_MAX, 56 }; 57 58 enum adreno_quirks { 59 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, 60 ADRENO_QUIRK_FAULT_DETECT_MASK = 2, 61 }; 62 63 struct adreno_rev { 64 uint8_t core; 65 uint8_t major; 66 uint8_t minor; 67 uint8_t patchid; 68 }; 69 70 #define ADRENO_REV(core, major, minor, patchid) \ 71 ((struct adreno_rev){ core, major, minor, patchid }) 72 73 struct adreno_gpu_funcs { 74 struct msm_gpu_funcs base; 75 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 76 }; 77 78 struct adreno_info { 79 struct adreno_rev rev; 80 uint32_t revn; 81 const char *name; 82 const char *fw[ADRENO_FW_MAX]; 83 uint32_t gmem; 84 enum adreno_quirks quirks; 85 struct msm_gpu *(*init)(struct drm_device *dev); 86 const char *zapfw; 87 }; 88 89 const struct adreno_info *adreno_info(struct adreno_rev rev); 90 91 struct adreno_gpu { 92 struct msm_gpu base; 93 struct adreno_rev rev; 94 const struct adreno_info *info; 95 uint32_t gmem; /* actual gmem size */ 96 uint32_t revn; /* numeric revision name */ 97 const struct adreno_gpu_funcs *funcs; 98 99 /* interesting register offsets to dump: */ 100 const unsigned int *registers; 101 102 /* 103 * Are we loading fw from legacy path? Prior to addition 104 * of gpu firmware to linux-firmware, the fw files were 105 * placed in toplevel firmware directory, following qcom's 106 * android kernel. But linux-firmware preferred they be 107 * placed in a 'qcom' subdirectory. 108 * 109 * For backwards compatibility, we try first to load from 110 * the new path, using request_firmware_direct() to avoid 111 * any potential timeout waiting for usermode helper, then 112 * fall back to the old path (with direct load). And 113 * finally fall back to request_firmware() with the new 114 * path to allow the usermode helper. 115 */ 116 enum { 117 FW_LOCATION_UNKNOWN = 0, 118 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 119 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 120 FW_LOCATION_HELPER, 121 } fwloc; 122 123 /* firmware: */ 124 const struct firmware *fw[ADRENO_FW_MAX]; 125 126 /* 127 * Register offsets are different between some GPUs. 128 * GPU specific offsets will be exported by GPU specific 129 * code (a3xx_gpu.c) and stored in this common location. 130 */ 131 const unsigned int *reg_offsets; 132 }; 133 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 134 135 /* platform config data (ie. from DT, or pdata) */ 136 struct adreno_platform_config { 137 struct adreno_rev rev; 138 }; 139 140 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 141 142 #define spin_until(X) ({ \ 143 int __ret = -ETIMEDOUT; \ 144 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 145 do { \ 146 if (X) { \ 147 __ret = 0; \ 148 break; \ 149 } \ 150 } while (time_before(jiffies, __t)); \ 151 __ret; \ 152 }) 153 154 155 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) 156 { 157 return (gpu->revn >= 300) && (gpu->revn < 400); 158 } 159 160 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 161 { 162 return gpu->revn == 305; 163 } 164 165 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 166 { 167 /* yes, 307, because a305c is 306 */ 168 return gpu->revn == 307; 169 } 170 171 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 172 { 173 return gpu->revn == 320; 174 } 175 176 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 177 { 178 return gpu->revn == 330; 179 } 180 181 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 182 { 183 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 184 } 185 186 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 187 { 188 return (gpu->revn >= 400) && (gpu->revn < 500); 189 } 190 191 static inline int adreno_is_a420(struct adreno_gpu *gpu) 192 { 193 return gpu->revn == 420; 194 } 195 196 static inline int adreno_is_a430(struct adreno_gpu *gpu) 197 { 198 return gpu->revn == 430; 199 } 200 201 static inline int adreno_is_a530(struct adreno_gpu *gpu) 202 { 203 return gpu->revn == 530; 204 } 205 206 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 207 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 208 const char *fwname); 209 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 210 const struct firmware *fw, u64 *iova); 211 int adreno_hw_init(struct msm_gpu *gpu); 212 void adreno_recover(struct msm_gpu *gpu); 213 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 214 struct msm_file_private *ctx); 215 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 216 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 217 #ifdef CONFIG_DEBUG_FS 218 void adreno_show(struct msm_gpu *gpu, struct seq_file *m); 219 #endif 220 void adreno_dump_info(struct msm_gpu *gpu); 221 void adreno_dump(struct msm_gpu *gpu); 222 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 223 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 224 225 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 226 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 227 int nr_rings); 228 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 229 230 231 /* ringbuffer helpers (the parts that are adreno specific) */ 232 233 static inline void 234 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 235 { 236 adreno_wait_ring(ring, cnt+1); 237 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 238 } 239 240 /* no-op packet: */ 241 static inline void 242 OUT_PKT2(struct msm_ringbuffer *ring) 243 { 244 adreno_wait_ring(ring, 1); 245 OUT_RING(ring, CP_TYPE2_PKT); 246 } 247 248 static inline void 249 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 250 { 251 adreno_wait_ring(ring, cnt+1); 252 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 253 } 254 255 static inline u32 PM4_PARITY(u32 val) 256 { 257 return (0x9669 >> (0xF & (val ^ 258 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 259 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 260 (val >> 28)))) & 1; 261 } 262 263 /* Maximum number of values that can be executed for one opcode */ 264 #define TYPE4_MAX_PAYLOAD 127 265 266 #define PKT4(_reg, _cnt) \ 267 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 268 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 269 270 static inline void 271 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 272 { 273 adreno_wait_ring(ring, cnt + 1); 274 OUT_RING(ring, PKT4(regindx, cnt)); 275 } 276 277 static inline void 278 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 279 { 280 adreno_wait_ring(ring, cnt + 1); 281 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 282 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 283 } 284 285 /* 286 * adreno_reg_check() - Checks the validity of a register enum 287 * @gpu: Pointer to struct adreno_gpu 288 * @offset_name: The register enum that is checked 289 */ 290 static inline bool adreno_reg_check(struct adreno_gpu *gpu, 291 enum adreno_regs offset_name) 292 { 293 if (offset_name >= REG_ADRENO_REGISTER_MAX || 294 !gpu->reg_offsets[offset_name]) { 295 BUG(); 296 } 297 298 /* 299 * REG_SKIP is a special value that tell us that the register in 300 * question isn't implemented on target but don't trigger a BUG(). This 301 * is used to cleanly implement adreno_gpu_write64() and 302 * adreno_gpu_read64() in a generic fashion 303 */ 304 if (gpu->reg_offsets[offset_name] == REG_SKIP) 305 return false; 306 307 return true; 308 } 309 310 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu, 311 enum adreno_regs offset_name) 312 { 313 u32 reg = gpu->reg_offsets[offset_name]; 314 u32 val = 0; 315 if(adreno_reg_check(gpu,offset_name)) 316 val = gpu_read(&gpu->base, reg - 1); 317 return val; 318 } 319 320 static inline void adreno_gpu_write(struct adreno_gpu *gpu, 321 enum adreno_regs offset_name, u32 data) 322 { 323 u32 reg = gpu->reg_offsets[offset_name]; 324 if(adreno_reg_check(gpu, offset_name)) 325 gpu_write(&gpu->base, reg - 1, data); 326 } 327 328 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 329 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 330 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 331 332 static inline void adreno_gpu_write64(struct adreno_gpu *gpu, 333 enum adreno_regs lo, enum adreno_regs hi, u64 data) 334 { 335 adreno_gpu_write(gpu, lo, lower_32_bits(data)); 336 adreno_gpu_write(gpu, hi, upper_32_bits(data)); 337 } 338 339 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 340 { 341 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 342 } 343 344 /* 345 * Given a register and a count, return a value to program into 346 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 347 * registers starting at _reg. 348 * 349 * The register base needs to be a multiple of the length. If it is not, the 350 * hardware will quietly mask off the bits for you and shift the size. For 351 * example, if you intend the protection to start at 0x07 for a length of 4 352 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 353 * expose registers you intended to protect! 354 */ 355 #define ADRENO_PROTECT_RW(_reg, _len) \ 356 ((1 << 30) | (1 << 29) | \ 357 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 358 359 /* 360 * Same as above, but allow reads over the range. For areas of mixed use (such 361 * as performance counters) this allows us to protect a much larger range with a 362 * single register 363 */ 364 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 365 ((1 << 29) \ 366 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 367 368 #endif /* __ADRENO_GPU_H__ */ 369